DE2150836A1 - Logikglied, insbesondere decodierer, mit redudanten elementen - Google Patents

Logikglied, insbesondere decodierer, mit redudanten elementen

Info

Publication number
DE2150836A1
DE2150836A1 DE19712150836 DE2150836A DE2150836A1 DE 2150836 A1 DE2150836 A1 DE 2150836A1 DE 19712150836 DE19712150836 DE 19712150836 DE 2150836 A DE2150836 A DE 2150836A DE 2150836 A1 DE2150836 A1 DE 2150836A1
Authority
DE
Germany
Prior art keywords
decoder
redundant
memory cell
elements
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19712150836
Other languages
German (de)
English (en)
Inventor
Karl Dr Goser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to BE789991D priority Critical patent/BE789991A/xx
Application filed by Siemens Corp filed Critical Siemens Corp
Priority to DE19712150836 priority patent/DE2150836A1/de
Priority to US295584A priority patent/US3860831A/en
Priority to LU66272A priority patent/LU66272A1/xx
Priority to FR7235934A priority patent/FR2156234A1/fr
Priority to IT30338/72A priority patent/IT968835B/it
Priority to JP47101622A priority patent/JPS4847732A/ja
Priority to NL7213811A priority patent/NL7213811A/xx
Publication of DE2150836A1 publication Critical patent/DE2150836A1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
DE19712150836 1971-10-12 1971-10-12 Logikglied, insbesondere decodierer, mit redudanten elementen Pending DE2150836A1 (de)

Priority Applications (8)

Application Number Priority Date Filing Date Title
BE789991D BE789991A (fr) 1971-10-12 Dispositif logique, en particulier decodeur a elements redondants
DE19712150836 DE2150836A1 (de) 1971-10-12 1971-10-12 Logikglied, insbesondere decodierer, mit redudanten elementen
US295584A US3860831A (en) 1971-10-12 1972-10-06 Logic circuit, in particular a decoder, with redundant elements
LU66272A LU66272A1 (enExample) 1971-10-12 1972-10-11
FR7235934A FR2156234A1 (enExample) 1971-10-12 1972-10-11
IT30338/72A IT968835B (it) 1971-10-12 1972-10-11 Circuito logico in particolare decodificatore con elementi ridondanti
JP47101622A JPS4847732A (enExample) 1971-10-12 1972-10-12
NL7213811A NL7213811A (enExample) 1971-10-12 1972-10-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19712150836 DE2150836A1 (de) 1971-10-12 1971-10-12 Logikglied, insbesondere decodierer, mit redudanten elementen

Publications (1)

Publication Number Publication Date
DE2150836A1 true DE2150836A1 (de) 1973-04-19

Family

ID=5822136

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19712150836 Pending DE2150836A1 (de) 1971-10-12 1971-10-12 Logikglied, insbesondere decodierer, mit redudanten elementen

Country Status (8)

Country Link
US (1) US3860831A (enExample)
JP (1) JPS4847732A (enExample)
BE (1) BE789991A (enExample)
DE (1) DE2150836A1 (enExample)
FR (1) FR2156234A1 (enExample)
IT (1) IT968835B (enExample)
LU (1) LU66272A1 (enExample)
NL (1) NL7213811A (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51146125A (en) * 1975-06-11 1976-12-15 Hitachi Ltd Memory circuit
US4051354A (en) * 1975-07-03 1977-09-27 Texas Instruments Incorporated Fault-tolerant cell addressable array
FR2319953A1 (fr) * 1975-07-28 1977-02-25 Labo Cent Telecommunicat Dispositif de reconfiguration de memoire
JPS5928560Y2 (ja) * 1979-11-13 1984-08-17 富士通株式会社 冗長ビットを有する記憶装置
JPS6051199B2 (ja) * 1980-11-13 1985-11-12 富士通株式会社 半導体装置
US4435791A (en) 1981-09-09 1984-03-06 Harris Corporation CMOS Address buffer for a semiconductor memory
US4674007A (en) * 1985-06-07 1987-06-16 Microscience Corporation Method and apparatus for facilitating production of electronic circuit boards
US4800302A (en) * 1987-07-17 1989-01-24 Trw Inc. Redundancy system with distributed mapping
US4978869A (en) * 1988-03-02 1990-12-18 Dallas Semiconductor Corporation ESD resistant latch circuit
US6408402B1 (en) 1994-03-22 2002-06-18 Hyperchip Inc. Efficient direct replacement cell fault tolerant architecture
AU700629B2 (en) * 1994-03-22 1999-01-07 Hyperchip Inc. Efficient direct cell replacement fault tolerant architecture supporting completely integrated systems with means for direct communication with system operator

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3500148A (en) * 1968-08-28 1970-03-10 Bell Telephone Labor Inc Multipurpose integrated circuit arrangement
US3665174A (en) * 1968-09-03 1972-05-23 Ibm Error tolerant arithmetic logic unit
US3634929A (en) * 1968-11-02 1972-01-18 Tokyo Shibaura Electric Co Method of manufacturing semiconductor integrated circuits
US3721838A (en) * 1970-12-21 1973-03-20 Ibm Repairable semiconductor circuit element and method of manufacture

Also Published As

Publication number Publication date
IT968835B (it) 1974-03-20
LU66272A1 (enExample) 1973-04-13
FR2156234A1 (enExample) 1973-05-25
BE789991A (fr) 1973-04-12
US3860831A (en) 1975-01-14
JPS4847732A (enExample) 1973-07-06
NL7213811A (enExample) 1973-04-16

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