IT968835B - Circuito logico in particolare decodificatore con elementi ridondanti - Google Patents
Circuito logico in particolare decodificatore con elementi ridondantiInfo
- Publication number
- IT968835B IT968835B IT30338/72A IT3033872A IT968835B IT 968835 B IT968835 B IT 968835B IT 30338/72 A IT30338/72 A IT 30338/72A IT 3033872 A IT3033872 A IT 3033872A IT 968835 B IT968835 B IT 968835B
- Authority
- IT
- Italy
- Prior art keywords
- logical circuit
- redundant elements
- particular decoder
- decoder
- redundant
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19712150836 DE2150836A1 (de) | 1971-10-12 | 1971-10-12 | Logikglied, insbesondere decodierer, mit redudanten elementen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT968835B true IT968835B (it) | 1974-03-20 |
Family
ID=5822136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT30338/72A IT968835B (it) | 1971-10-12 | 1972-10-11 | Circuito logico in particolare decodificatore con elementi ridondanti |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US3860831A (enExample) |
| JP (1) | JPS4847732A (enExample) |
| BE (1) | BE789991A (enExample) |
| DE (1) | DE2150836A1 (enExample) |
| FR (1) | FR2156234A1 (enExample) |
| IT (1) | IT968835B (enExample) |
| LU (1) | LU66272A1 (enExample) |
| NL (1) | NL7213811A (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51146125A (en) * | 1975-06-11 | 1976-12-15 | Hitachi Ltd | Memory circuit |
| US4051354A (en) * | 1975-07-03 | 1977-09-27 | Texas Instruments Incorporated | Fault-tolerant cell addressable array |
| FR2319953A1 (fr) * | 1975-07-28 | 1977-02-25 | Labo Cent Telecommunicat | Dispositif de reconfiguration de memoire |
| JPS5928560Y2 (ja) * | 1979-11-13 | 1984-08-17 | 富士通株式会社 | 冗長ビットを有する記憶装置 |
| JPS6051199B2 (ja) * | 1980-11-13 | 1985-11-12 | 富士通株式会社 | 半導体装置 |
| US4435791A (en) | 1981-09-09 | 1984-03-06 | Harris Corporation | CMOS Address buffer for a semiconductor memory |
| US4674007A (en) * | 1985-06-07 | 1987-06-16 | Microscience Corporation | Method and apparatus for facilitating production of electronic circuit boards |
| US4800302A (en) * | 1987-07-17 | 1989-01-24 | Trw Inc. | Redundancy system with distributed mapping |
| US4978869A (en) * | 1988-03-02 | 1990-12-18 | Dallas Semiconductor Corporation | ESD resistant latch circuit |
| CA2185787A1 (en) * | 1994-03-22 | 1995-09-28 | Richard S. Norman | Efficient direct cell replacement fault tolerant architecture supporting completely integrated systems with means for direct communication with system operator |
| US6408402B1 (en) | 1994-03-22 | 2002-06-18 | Hyperchip Inc. | Efficient direct replacement cell fault tolerant architecture |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3500148A (en) * | 1968-08-28 | 1970-03-10 | Bell Telephone Labor Inc | Multipurpose integrated circuit arrangement |
| US3665174A (en) * | 1968-09-03 | 1972-05-23 | Ibm | Error tolerant arithmetic logic unit |
| US3634929A (en) * | 1968-11-02 | 1972-01-18 | Tokyo Shibaura Electric Co | Method of manufacturing semiconductor integrated circuits |
| US3721838A (en) * | 1970-12-21 | 1973-03-20 | Ibm | Repairable semiconductor circuit element and method of manufacture |
-
0
- BE BE789991D patent/BE789991A/xx unknown
-
1971
- 1971-10-12 DE DE19712150836 patent/DE2150836A1/de active Pending
-
1972
- 1972-10-06 US US295584A patent/US3860831A/en not_active Expired - Lifetime
- 1972-10-11 FR FR7235934A patent/FR2156234A1/fr not_active Withdrawn
- 1972-10-11 IT IT30338/72A patent/IT968835B/it active
- 1972-10-11 LU LU66272A patent/LU66272A1/xx unknown
- 1972-10-12 JP JP47101622A patent/JPS4847732A/ja active Pending
- 1972-10-12 NL NL7213811A patent/NL7213811A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| LU66272A1 (enExample) | 1973-04-13 |
| US3860831A (en) | 1975-01-14 |
| BE789991A (fr) | 1973-04-12 |
| FR2156234A1 (enExample) | 1973-05-25 |
| DE2150836A1 (de) | 1973-04-19 |
| JPS4847732A (enExample) | 1973-07-06 |
| NL7213811A (enExample) | 1973-04-16 |
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