FR2319953A1 - Dispositif de reconfiguration de memoire - Google Patents

Dispositif de reconfiguration de memoire

Info

Publication number
FR2319953A1
FR2319953A1 FR7523418A FR7523418A FR2319953A1 FR 2319953 A1 FR2319953 A1 FR 2319953A1 FR 7523418 A FR7523418 A FR 7523418A FR 7523418 A FR7523418 A FR 7523418A FR 2319953 A1 FR2319953 A1 FR 2319953A1
Authority
FR
France
Prior art keywords
reconfiguration device
memory reconfiguration
memory
reconfiguration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7523418A
Other languages
English (en)
Other versions
FR2319953B1 (fr
Inventor
Marc Gustave Marie Baudhuin
Robert Raoul Charles Bonami
Louis Pierre Castellan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Laboratoire Central de Telecommunications SA
Original Assignee
Laboratoire Central de Telecommunications SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Laboratoire Central de Telecommunications SA filed Critical Laboratoire Central de Telecommunications SA
Priority to FR7523418A priority Critical patent/FR2319953A1/fr
Priority to GB3060376A priority patent/GB1536436A/en
Priority to BE2055208A priority patent/BE844571A/fr
Publication of FR2319953A1 publication Critical patent/FR2319953A1/fr
Application granted granted Critical
Publication of FR2319953B1 publication Critical patent/FR2319953B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
FR7523418A 1975-07-28 1975-07-28 Dispositif de reconfiguration de memoire Granted FR2319953A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR7523418A FR2319953A1 (fr) 1975-07-28 1975-07-28 Dispositif de reconfiguration de memoire
GB3060376A GB1536436A (en) 1975-07-28 1976-07-22 Memory reconfiguration device
BE2055208A BE844571A (fr) 1975-07-28 1976-07-28 Dispositif de reconfiguration de memoire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7523418A FR2319953A1 (fr) 1975-07-28 1975-07-28 Dispositif de reconfiguration de memoire

Publications (2)

Publication Number Publication Date
FR2319953A1 true FR2319953A1 (fr) 1977-02-25
FR2319953B1 FR2319953B1 (fr) 1979-08-24

Family

ID=9158412

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7523418A Granted FR2319953A1 (fr) 1975-07-28 1975-07-28 Dispositif de reconfiguration de memoire

Country Status (3)

Country Link
BE (1) BE844571A (fr)
FR (1) FR2319953A1 (fr)
GB (1) GB1536436A (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2375654A1 (fr) * 1976-12-27 1978-07-21 Rca Corp Circuit de rearrangement des bits d'un mot
FR2427647A1 (fr) * 1978-05-30 1979-12-28 Int Standard Electric Corp Procede et circuit pour l'execution de controles d'erreurs dans des systemes a memoire de calculateurs numeriques
EP0046976A2 (fr) * 1980-08-29 1982-03-10 Siemens Aktiengesellschaft Mémoire à semiconducteurs constituée de blocs fonctionnels comprenant des zones de mémoire redondantes
EP0076629A2 (fr) * 1981-10-01 1983-04-13 Honeywell Bull Inc. Système de mémoire reconfigurable
EP0028312B1 (fr) * 1979-10-31 1984-12-27 International Business Machines Corporation Procédé de connection de mémoires additionnelles dans un dispositif de traitement de données avec vérification de leur disposibilité et validité
EP0259859A2 (fr) * 1986-09-10 1988-03-16 Nec Corporation Système de traitement d'information pouvant réduire des opérations de mémoire non valables en détectant une erreur dans la mémoire principale

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8902365D0 (en) * 1989-02-03 1989-03-22 Int Computers Ltd Data processing system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3312947A (en) * 1963-12-31 1967-04-04 Bell Telephone Labor Inc Plural memory system with internal memory transfer and duplicated information
FR2156234A1 (fr) * 1971-10-12 1973-05-25 Siemens Ag
FR2217769A1 (fr) * 1973-02-09 1974-09-06 Honeywell Bull Soc Ind

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3312947A (en) * 1963-12-31 1967-04-04 Bell Telephone Labor Inc Plural memory system with internal memory transfer and duplicated information
FR2156234A1 (fr) * 1971-10-12 1973-05-25 Siemens Ag
FR2217769A1 (fr) * 1973-02-09 1974-09-06 Honeywell Bull Soc Ind

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, Vol. 13, No. 2, JUILLET 1970, PAGES 400-402, NEW YORK, US. BEE ET AL: "REMOVAL OF FAILING BUFFER SECTIONS IN A BUFFER-BACKING STORE" *
IBM TECHNICAL DISCLOSURE BULLETIN. Vol. 16, No. 11, AVRIL 1974, PAGE 3629, NEW YORK, US. DOGGETT ET AL: "TRANSPARENT RECOVERY OF SOLID STORAGE KEY ERRORS IN A PAGING SYSTEM" *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2375654A1 (fr) * 1976-12-27 1978-07-21 Rca Corp Circuit de rearrangement des bits d'un mot
FR2427647A1 (fr) * 1978-05-30 1979-12-28 Int Standard Electric Corp Procede et circuit pour l'execution de controles d'erreurs dans des systemes a memoire de calculateurs numeriques
EP0028312B1 (fr) * 1979-10-31 1984-12-27 International Business Machines Corporation Procédé de connection de mémoires additionnelles dans un dispositif de traitement de données avec vérification de leur disposibilité et validité
EP0046976A2 (fr) * 1980-08-29 1982-03-10 Siemens Aktiengesellschaft Mémoire à semiconducteurs constituée de blocs fonctionnels comprenant des zones de mémoire redondantes
EP0046976A3 (fr) * 1980-08-29 1984-05-16 Siemens Aktiengesellschaft Mémoire à semiconducteurs constituée de blocs fonctionnels comprenant des zones de mémoire redondantes
EP0076629A2 (fr) * 1981-10-01 1983-04-13 Honeywell Bull Inc. Système de mémoire reconfigurable
EP0076629A3 (en) * 1981-10-01 1985-12-18 Honeywell Information Systems Inc. Reconfigureable memory system
EP0259859A2 (fr) * 1986-09-10 1988-03-16 Nec Corporation Système de traitement d'information pouvant réduire des opérations de mémoire non valables en détectant une erreur dans la mémoire principale
EP0259859A3 (en) * 1986-09-10 1989-11-23 Nec Corporation Information processing system capable of reducing invalid memory operations by detecting an error in a main memory

Also Published As

Publication number Publication date
GB1536436A (en) 1978-12-20
FR2319953B1 (fr) 1979-08-24
BE844571A (fr) 1977-01-28

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Legal Events

Date Code Title Description
ST Notification of lapse