FR2375654A1 - Circuit de rearrangement des bits d'un mot - Google Patents

Circuit de rearrangement des bits d'un mot

Info

Publication number
FR2375654A1
FR2375654A1 FR7731798A FR7731798A FR2375654A1 FR 2375654 A1 FR2375654 A1 FR 2375654A1 FR 7731798 A FR7731798 A FR 7731798A FR 7731798 A FR7731798 A FR 7731798A FR 2375654 A1 FR2375654 A1 FR 2375654A1
Authority
FR
France
Prior art keywords
lines
conductor
group
common
word bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7731798A
Other languages
English (en)
Other versions
FR2375654B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of FR2375654A1 publication Critical patent/FR2375654A1/fr
Application granted granted Critical
Publication of FR2375654B1 publication Critical patent/FR2375654B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
  • Microcomputers (AREA)

Abstract

L'invention concerne des circuits logiques permettant de réarranger l'ordre des bits d'un mot dans les traitements informatiques. Le circuit utilisé dans l'invention compone un processeur 11, un conducteur commun de données 15 et un conducteur commun d'adresses 13 se divisant en un premier groupe de lignes et un second groupe de lignes. Un organe de décodage 17 est couplé aux lignes du second groupe et délivre des signaux de commande à un réseau de portes de transmission 19 qui, en fonction des signaux de commande reçus, raccorde des lignes du conducteur commun 13 à des lignes du conducteur commun 15 par l'intermédiaire d'un organe de couplage 12. L'invention s'applique notamment aux microprocesseurs.
FR7731798A 1976-12-27 1977-10-21 Circuit de rearrangement des bits d'un mot Granted FR2375654A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/754,692 US4130886A (en) 1976-12-27 1976-12-27 Circuit for rearranging word bits

Publications (2)

Publication Number Publication Date
FR2375654A1 true FR2375654A1 (fr) 1978-07-21
FR2375654B1 FR2375654B1 (fr) 1980-10-17

Family

ID=25035893

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7731798A Granted FR2375654A1 (fr) 1976-12-27 1977-10-21 Circuit de rearrangement des bits d'un mot

Country Status (6)

Country Link
US (1) US4130886A (fr)
JP (1) JPS5382140A (fr)
DE (1) DE2747800C3 (fr)
FR (1) FR2375654A1 (fr)
GB (1) GB1591427A (fr)
IT (1) IT1088614B (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56109156U (fr) * 1980-01-18 1981-08-24
JPS60204032A (ja) * 1984-03-28 1985-10-15 Res Dev Corp Of Japan 擬似乱数発生回路
JPS6151268A (ja) * 1984-08-21 1986-03-13 Nec Corp デ−タ処理装置
JPS6151269A (ja) * 1984-08-21 1986-03-13 Nec Corp デ−タ処理装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3425036A (en) * 1966-03-25 1969-01-28 Burroughs Corp Digital computer having a generalized literal operation
US3584781A (en) * 1968-07-01 1971-06-15 Bell Telephone Labor Inc Fft method and apparatus for real valued inputs
FR2319953A1 (fr) * 1975-07-28 1977-02-25 Labo Cent Telecommunicat Dispositif de reconfiguration de memoire

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3374463A (en) * 1964-12-23 1968-03-19 Bell Telephone Labor Inc Shift and rotate circuit for a data processor
US3436737A (en) * 1967-01-30 1969-04-01 Sperry Rand Corp Shift enable algorithm implementation means
US3839705A (en) * 1972-12-14 1974-10-01 Gen Electric Data processor including microprogram control means
US3887799A (en) * 1973-12-03 1975-06-03 Theodore P Lindgren Asynchronous n bit position data shifter
US3911405A (en) * 1974-03-20 1975-10-07 Sperry Rand Corp General purpose edit unit
US3953833A (en) * 1974-08-21 1976-04-27 Technology Marketing Incorporated Microprogrammable computer having a dual function secondary storage element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3425036A (en) * 1966-03-25 1969-01-28 Burroughs Corp Digital computer having a generalized literal operation
US3584781A (en) * 1968-07-01 1971-06-15 Bell Telephone Labor Inc Fft method and apparatus for real valued inputs
FR2319953A1 (fr) * 1975-07-28 1977-02-25 Labo Cent Telecommunicat Dispositif de reconfiguration de memoire

Also Published As

Publication number Publication date
JPS5382140A (en) 1978-07-20
IT1088614B (it) 1985-06-10
DE2747800A1 (de) 1978-06-29
FR2375654B1 (fr) 1980-10-17
US4130886A (en) 1978-12-19
DE2747800B2 (de) 1979-07-12
DE2747800C3 (de) 1980-03-27
GB1591427A (en) 1981-06-24

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Legal Events

Date Code Title Description
ST Notification of lapse