DE2130624A1 - Verfahren zur Herstellung ultraduenner Halbleiter-Wafer - Google Patents

Verfahren zur Herstellung ultraduenner Halbleiter-Wafer

Info

Publication number
DE2130624A1
DE2130624A1 DE19712130624 DE2130624A DE2130624A1 DE 2130624 A1 DE2130624 A1 DE 2130624A1 DE 19712130624 DE19712130624 DE 19712130624 DE 2130624 A DE2130624 A DE 2130624A DE 2130624 A1 DE2130624 A1 DE 2130624A1
Authority
DE
Germany
Prior art keywords
layer
substrate
thin
contact
production
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19712130624
Other languages
German (de)
English (en)
Inventor
Irvin John Calhoun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE2130624A1 publication Critical patent/DE2130624A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/61—Electrolytic etching
    • H10P50/613—Electrolytic etching of Group IV materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
DE19712130624 1970-06-22 1971-06-21 Verfahren zur Herstellung ultraduenner Halbleiter-Wafer Pending DE2130624A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US4831570A 1970-06-22 1970-06-22

Publications (1)

Publication Number Publication Date
DE2130624A1 true DE2130624A1 (de) 1971-12-30

Family

ID=21953887

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19712130624 Pending DE2130624A1 (de) 1970-06-22 1971-06-21 Verfahren zur Herstellung ultraduenner Halbleiter-Wafer

Country Status (7)

Country Link
US (1) US3655540A (enExample)
BE (1) BE768643A (enExample)
DE (1) DE2130624A1 (enExample)
FR (1) FR2096402B1 (enExample)
GB (1) GB1345800A (enExample)
NL (1) NL7108279A (enExample)
SE (1) SE373233B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2707372A1 (de) * 1976-03-15 1977-09-22 Ibm Verfahren zum aetzen von silicium unter anlegung einer elektrischen spannung

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3867272A (en) * 1970-06-30 1975-02-18 Hughes Aircraft Co Electrolytic anticompromise apparatus
US3902979A (en) * 1974-06-24 1975-09-02 Westinghouse Electric Corp Insulator substrate with a thin mono-crystalline semiconductive layer and method of fabrication
US4141621A (en) * 1977-08-05 1979-02-27 Honeywell Inc. Three layer waveguide for thin film lens fabrication
FR2684801B1 (fr) * 1991-12-06 1997-01-24 Picogiga Sa Procede de realisation de composants semiconducteurs, notamment sur gaas ou inp, avec recuperation du substrat par voie chimique.
US5344517A (en) * 1993-04-22 1994-09-06 Bandgap Technology Corporation Method for lift-off of epitaxial layers and applications thereof
US6882045B2 (en) * 1999-10-28 2005-04-19 Thomas J. Massingill Multi-chip module and method for forming and method for deplating defective capacitors

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2656496A (en) * 1951-07-31 1953-10-20 Bell Telephone Labor Inc Semiconductor translating device
US3096262A (en) * 1958-10-23 1963-07-02 Shockley William Method of making thin slices of semiconductive material
NL6703014A (enExample) * 1967-02-25 1968-08-26
US3550260A (en) * 1968-12-26 1970-12-29 Motorola Inc Method for making a hot carrier pn-diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2707372A1 (de) * 1976-03-15 1977-09-22 Ibm Verfahren zum aetzen von silicium unter anlegung einer elektrischen spannung

Also Published As

Publication number Publication date
GB1345800A (en) 1974-02-06
FR2096402A1 (enExample) 1972-02-18
NL7108279A (enExample) 1971-12-24
SE373233B (enExample) 1975-01-27
BE768643A (fr) 1971-11-03
FR2096402B1 (enExample) 1977-06-03
US3655540A (en) 1972-04-11

Similar Documents

Publication Publication Date Title
DE1614283C3 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE69504495T2 (de) Spannungsdurchbruchfeste halbleiterbauelemente aus einkristall-siliziumkarbid und verfahren zu deren herstellung
DE1439935A1 (de) Halbleitereinrichtung und Verfahren zu deren Herstellung
DE1764281C3 (de) Verfahren zum Herstellen einer Halbleitervorrichtung
DE4232886C2 (de) Kaltkathoden-Emitterelement
DE1197549B (de) Halbleiterbauelement mit mindestens einem pn-UEbergang und mindestens einer Kontakt-elektrode auf einer Isolierschicht
DE4231310C1 (de) Verfahren zur Herstellung eines Bauelementes mit porösem Silizium
DE2031333C3 (de) Verfahren zum Herstellen eines Halbleiterbauelementes
DE4130555A1 (de) Halbleitervorrichtung mit hoher durchbruchsspannung und geringem widerstand, sowie herstellungsverfahren
DE1130522B (de) Flaechentransistor mit anlegierten Emitter- und Kollektorelektroden und Legierungs-verfahren zu seiner Herstellung
DE2130624A1 (de) Verfahren zur Herstellung ultraduenner Halbleiter-Wafer
DE2953394C2 (enExample)
DE1949646C3 (de) Verfahren zum Herstellen eines Halbleiterbauelements, mit einer Schottky-Sperrschicht
DE2517049A1 (de) Sperrschicht-feldeffekttransistor und verfahren zu dessen herstellung
DE2639364C3 (de) Thyristor
DE2924702C2 (de) Verfahren und Vorrichtung zur Herstellung von Halbleitervorrichtungen
DE2357640B2 (de) Kontaktierung eines planaren Gunn-Effekt-Halbleiterbauelementes
DE2018027A1 (de) Verfahren zum Einbringen extrem feiner öffnungen
DE69001016T2 (de) Verfahren zur herstellung von wolfram-antimon ohmischen kontakten mit niedrigem widerstand auf iii-iv halbleitermaterialien.
DE6802215U (de) Halbleiterbauelement.
DE1908901B2 (de) Verfahren zum herstellen von halbleiterbauelementen unter verwendung einer maske mit einem feinen markierungsmuster
DE2008397C3 (de) Verfahren zum Herstellen eines Kontaktes auf einem n-leitenden Galliumarsenidsubstrat
DE1954443C3 (de) Halbleiterbauelement mit einem Schottky-Übergang und Verfahren zu seiner Herstellung
US2818537A (en) Germanium diodes
DE1564608C3 (de) Verfahren zum Herstellen eines Transistors