DE2129676A1 - Halbleiter-Einrichtung und Verfahren zu ihrer Herstellung - Google Patents

Halbleiter-Einrichtung und Verfahren zu ihrer Herstellung

Info

Publication number
DE2129676A1
DE2129676A1 DE19712129676 DE2129676A DE2129676A1 DE 2129676 A1 DE2129676 A1 DE 2129676A1 DE 19712129676 DE19712129676 DE 19712129676 DE 2129676 A DE2129676 A DE 2129676A DE 2129676 A1 DE2129676 A1 DE 2129676A1
Authority
DE
Germany
Prior art keywords
semiconductor
layer
conductivity type
substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19712129676
Other languages
German (de)
English (en)
Inventor
Hiroto Kawagoe
Seiichi Tachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2129676A1 publication Critical patent/DE2129676A1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
DE19712129676 1970-06-15 1971-06-15 Halbleiter-Einrichtung und Verfahren zu ihrer Herstellung Pending DE2129676A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5100070 1970-06-15

Publications (1)

Publication Number Publication Date
DE2129676A1 true DE2129676A1 (de) 1972-02-10

Family

ID=12874501

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19712129676 Pending DE2129676A1 (de) 1970-06-15 1971-06-15 Halbleiter-Einrichtung und Verfahren zu ihrer Herstellung

Country Status (4)

Country Link
DE (1) DE2129676A1 (enrdf_load_stackoverflow)
FR (1) FR2095258B1 (enrdf_load_stackoverflow)
GB (2) GB1362512A (enrdf_load_stackoverflow)
NL (1) NL7108101A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19643143A1 (de) * 1996-10-18 1998-04-23 Inventa Ag Haftvermittler für Polyamid-Verbunde

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1086607A (en) * 1965-06-03 1967-10-11 Ncr Co Method of electrically isolating components in solid-state electronic circuits
NL153374B (nl) * 1966-10-05 1977-05-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19643143A1 (de) * 1996-10-18 1998-04-23 Inventa Ag Haftvermittler für Polyamid-Verbunde
DE19643143C2 (de) * 1996-10-18 2002-06-20 Inventa Ag Haftvermittler für Polyamid-Verbunde, Verfahren zu deren Herstellung sowie deren Verwendung

Also Published As

Publication number Publication date
FR2095258B1 (enrdf_load_stackoverflow) 1977-04-22
GB1362512A (en) 1974-08-07
FR2095258A1 (enrdf_load_stackoverflow) 1972-02-11
GB1360996A (en) 1974-07-24
NL7108101A (enrdf_load_stackoverflow) 1971-12-17

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