GB1086607A - Method of electrically isolating components in solid-state electronic circuits - Google Patents

Method of electrically isolating components in solid-state electronic circuits

Info

Publication number
GB1086607A
GB1086607A GB2223066A GB2223066A GB1086607A GB 1086607 A GB1086607 A GB 1086607A GB 2223066 A GB2223066 A GB 2223066A GB 2223066 A GB2223066 A GB 2223066A GB 1086607 A GB1086607 A GB 1086607A
Authority
GB
United Kingdom
Prior art keywords
layer
channels
silicon
semi
applied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2223066A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US46103065A priority Critical
Application filed by NCR Corp filed Critical NCR Corp
Publication of GB1086607A publication Critical patent/GB1086607A/en
Application status is Expired legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31608Deposition of SiO2
    • H01L21/31612Deposition of SiO2 on a silicon body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Abstract

1,086,607. Semi-conductor devices; resistors. NATIONAL CASH REGISTER CO. May 19, 1966 [June 3, 1965], No. 22230/66. Headings H1K and H1S. The separate components of an integrated circuit formed in a semi-conducting layer 11 on a semi-conducting substrate 10 are isolated from each other by insulating material 21 vapour deposited in channels extending completely through the layer 11. In the preferred form the layer 11 is of silicon epitaxially deposited on a monocrystalline silicon substrate 10 of opposite conductivity type. Separate devices are formed by diffusion into the layer 11, e.g. to comprise a transistor 15, 14, 11 and a resistor layer 16 of opposite conductivity type to the layer 11, and the channels are then etched using an oxide masking technique, the mask being shaped by etching with HF using a photo-resist masking method. A layer 21 of silicon dioxide is then vapour deposited, e.g. by pyrolytic hydrolysis of silicon tetrabromide, over the entire surface, and is subsequently lapped or etched down to the upper surface of the layer 11, leaving the channels filled. A new silicon dioxide layer is then applied to the device surfaces, and openings 22 are provided therein by masking and etching to enable metal contacts to be made, interconnections being applied to complete the circuit. In an alternative embodiment a silicon dioxide layer (27), Fig. 6 (not shown), is provided between a monocrystalline silicon layer (25) and a polycrystalline layer (26) vapour deposited thereon. The method of the previous embodiment is then applied to the layer (25), the channels being etched down to the oxide layer (27).
GB2223066A 1965-06-03 1966-05-19 Method of electrically isolating components in solid-state electronic circuits Expired GB1086607A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US46103065A true 1965-06-03 1965-06-03

Publications (1)

Publication Number Publication Date
GB1086607A true GB1086607A (en) 1967-10-11

Family

ID=23830953

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2223066A Expired GB1086607A (en) 1965-06-03 1966-05-19 Method of electrically isolating components in solid-state electronic circuits

Country Status (3)

Country Link
BE (1) BE681959A (en)
CH (1) CH452709A (en)
GB (1) GB1086607A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2095258A1 (en) * 1970-06-15 1972-02-11 Hitachi Ltd
DE2218680A1 (en) * 1971-06-08 1972-12-28 Philips Nv
US6849918B1 (en) 1965-09-28 2005-02-01 Chou H. Li Miniaturized dielectrically isolated solid state device
US6979877B1 (en) * 1965-09-28 2005-12-27 Li Chou H Solid-state device
US7038290B1 (en) 1965-09-28 2006-05-02 Li Chou H Integrated circuit device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849918B1 (en) 1965-09-28 2005-02-01 Chou H. Li Miniaturized dielectrically isolated solid state device
US6979877B1 (en) * 1965-09-28 2005-12-27 Li Chou H Solid-state device
US7038290B1 (en) 1965-09-28 2006-05-02 Li Chou H Integrated circuit device
FR2095258A1 (en) * 1970-06-15 1972-02-11 Hitachi Ltd
DE2218680A1 (en) * 1971-06-08 1972-12-28 Philips Nv

Also Published As

Publication number Publication date
CH452709A (en) 1968-03-15
BE681959A (en) 1966-11-14

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