DE2108320A1 - Einrichtung zur Frequenz- und Phasenregelung - Google Patents
Einrichtung zur Frequenz- und PhasenregelungInfo
- Publication number
- DE2108320A1 DE2108320A1 DE19712108320 DE2108320A DE2108320A1 DE 2108320 A1 DE2108320 A1 DE 2108320A1 DE 19712108320 DE19712108320 DE 19712108320 DE 2108320 A DE2108320 A DE 2108320A DE 2108320 A1 DE2108320 A1 DE 2108320A1
- Authority
- DE
- Germany
- Prior art keywords
- voltage
- signals
- error
- signal
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000007704 transition Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 6
- 238000013016 damping Methods 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US24310A US3599110A (en) | 1970-03-31 | 1970-03-31 | Self-clocking system having a variable frequency oscillator locked to leading edge of data and clock |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2108320A1 true DE2108320A1 (de) | 1971-10-28 |
Family
ID=21819928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19712108320 Pending DE2108320A1 (de) | 1970-03-31 | 1971-02-22 | Einrichtung zur Frequenz- und Phasenregelung |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3599110A (enExample) |
| JP (1) | JPS463612A (enExample) |
| CA (1) | CA951383A (enExample) |
| DE (1) | DE2108320A1 (enExample) |
| FR (1) | FR2083976A5 (enExample) |
| GB (1) | GB1338309A (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3805180A (en) * | 1972-12-27 | 1974-04-16 | A Widmer | Binary-coded signal timing recovery circuit |
| US3806827A (en) * | 1973-07-16 | 1974-04-23 | Honeywell Inc | Frequency locked oscillator system in which input and oscillator frequencies are compared on half-cycle basis |
| US3982194A (en) * | 1975-02-18 | 1976-09-21 | Digital Equipment Corporation | Phase lock loop with delay circuits for relative digital decoding over a range of frequencies |
| US3986125A (en) * | 1975-10-31 | 1976-10-12 | Sperry Univac Corporation | Phase detector having a 360 linear range for periodic and aperiodic input pulse streams |
| US4034309A (en) * | 1975-12-23 | 1977-07-05 | International Business Machines Corporation | Apparatus and method for phase synchronization |
| USRE31851E (en) * | 1977-08-04 | 1985-03-19 | Dickey-John Corporation | Signal processing system |
| US4359734A (en) * | 1977-08-04 | 1982-11-16 | Dickey-John Corporation | Signal processing system |
| US4222013A (en) * | 1978-11-24 | 1980-09-09 | Bowers Thomas E | Phase locked loop for deriving clock signal from aperiodic data signal |
| US4246545A (en) * | 1979-02-02 | 1981-01-20 | Burroughs Corporation | Data signal responsive phase locked loop using averaging and initializing techniques |
| US4745372A (en) * | 1985-10-17 | 1988-05-17 | Matsushita Electric Industrial Co., Ltd. | Phase-locked-loop circuit having a charge pump |
| GB2352941B (en) * | 1999-08-03 | 2004-03-03 | Motorola Ltd | Synchronisation arrangement and method for synchronising a network |
-
1970
- 1970-03-31 US US24310A patent/US3599110A/en not_active Expired - Lifetime
-
1971
- 1971-01-24 JP JP868971A patent/JPS463612A/ja active Pending
- 1971-01-27 CA CA103,749,A patent/CA951383A/en not_active Expired
- 1971-02-16 FR FR7106545A patent/FR2083976A5/fr not_active Expired
- 1971-02-22 DE DE19712108320 patent/DE2108320A1/de active Pending
- 1971-04-19 GB GB2176271A patent/GB1338309A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US3599110A (en) | 1971-08-10 |
| GB1338309A (en) | 1973-11-21 |
| JPS463612A (enExample) | 1971-11-02 |
| FR2083976A5 (enExample) | 1971-12-17 |
| CA951383A (en) | 1974-07-16 |
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