DE2057608A1 - RST-Master-Slave-Flip-Flop - Google Patents

RST-Master-Slave-Flip-Flop

Info

Publication number
DE2057608A1
DE2057608A1 DE19702057608 DE2057608A DE2057608A1 DE 2057608 A1 DE2057608 A1 DE 2057608A1 DE 19702057608 DE19702057608 DE 19702057608 DE 2057608 A DE2057608 A DE 2057608A DE 2057608 A1 DE2057608 A1 DE 2057608A1
Authority
DE
Germany
Prior art keywords
input
flip
flop
master
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19702057608
Other languages
German (de)
English (en)
Inventor
Klaus Dipl-Ing Wiechert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
INST ELEKTRO ANLAGEN
Original Assignee
INST ELEKTRO ANLAGEN
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INST ELEKTRO ANLAGEN filed Critical INST ELEKTRO ANLAGEN
Publication of DE2057608A1 publication Critical patent/DE2057608A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the primary-secondary type

Landscapes

  • Logic Circuits (AREA)
DE19702057608 1969-11-28 1970-11-24 RST-Master-Slave-Flip-Flop Pending DE2057608A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DD14398069 1969-11-28

Publications (1)

Publication Number Publication Date
DE2057608A1 true DE2057608A1 (de) 1971-06-16

Family

ID=5481878

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19702057608 Pending DE2057608A1 (de) 1969-11-28 1970-11-24 RST-Master-Slave-Flip-Flop

Country Status (3)

Country Link
CS (1) CS151573B2 (enrdf_load_stackoverflow)
DE (1) DE2057608A1 (enrdf_load_stackoverflow)
SU (1) SU459857A1 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4160173A (en) * 1976-12-14 1979-07-03 Tokyo Shibaura Electric Co., Ltd. Logic circuit with two pairs of cross-coupled nand/nor gates

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4160173A (en) * 1976-12-14 1979-07-03 Tokyo Shibaura Electric Co., Ltd. Logic circuit with two pairs of cross-coupled nand/nor gates

Also Published As

Publication number Publication date
SU459857A1 (ru) 1975-02-05
CS151573B2 (enrdf_load_stackoverflow) 1973-10-19

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