DE19830475A1 - Halbleiterbauelement und Herstellungsverfahren - Google Patents

Halbleiterbauelement und Herstellungsverfahren

Info

Publication number
DE19830475A1
DE19830475A1 DE19830475A DE19830475A DE19830475A1 DE 19830475 A1 DE19830475 A1 DE 19830475A1 DE 19830475 A DE19830475 A DE 19830475A DE 19830475 A DE19830475 A DE 19830475A DE 19830475 A1 DE19830475 A1 DE 19830475A1
Authority
DE
Germany
Prior art keywords
component
lead frame
electronic component
electronic
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19830475A
Other languages
German (de)
English (en)
Inventor
Mahesh K Shah
Jun John W Hart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE19830475A1 publication Critical patent/DE19830475A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P1/00—Details of instruments
    • G01P1/02—Housings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measuring Fluid Pressure (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Pressure Sensors (AREA)
DE19830475A 1997-07-24 1998-07-08 Halbleiterbauelement und Herstellungsverfahren Ceased DE19830475A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/899,672 US5918112A (en) 1997-07-24 1997-07-24 Semiconductor component and method of fabrication

Publications (1)

Publication Number Publication Date
DE19830475A1 true DE19830475A1 (de) 1999-01-28

Family

ID=25411375

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19830475A Ceased DE19830475A1 (de) 1997-07-24 1998-07-08 Halbleiterbauelement und Herstellungsverfahren

Country Status (4)

Country Link
US (1) US5918112A (https=)
JP (1) JPH1154692A (https=)
KR (1) KR100559062B1 (https=)
DE (1) DE19830475A1 (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10012883A1 (de) * 2000-03-16 2001-09-27 Infineon Technologies Ag Verfahren zum Herstellen eines Packages mit mindestens zwei Speicherchips
US7807502B2 (en) 2007-05-17 2010-10-05 Micron Technology, Inc. Method for fabricating semiconductor packages with discrete components
DE102014016565B3 (de) * 2014-11-11 2015-11-12 Micronas Gmbh Schaltkreisgehäuse

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777785B1 (en) * 1999-08-25 2004-08-17 Winbond Electronics Corp. Lead frame containing a master and a slave IC chips and a testing circuit embedded within the master IC chip
DE10010461A1 (de) * 2000-03-03 2001-09-13 Infineon Technologies Ag Vorrichtung zum Verpacken elektronischer Bauteile mittels Spritzgußtechnik
AT410727B (de) * 2000-03-14 2003-07-25 Austria Mikrosysteme Int Verfahren zum unterbringen von sensoren in einem gehäuse
JP4614586B2 (ja) * 2001-06-28 2011-01-19 三洋電機株式会社 混成集積回路装置の製造方法
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US7176506B2 (en) * 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
JP3744828B2 (ja) * 2001-09-14 2006-02-15 ユーディナデバイス株式会社 半導体装置
US7754537B2 (en) * 2003-02-25 2010-07-13 Tessera, Inc. Manufacture of mountable capped chips
US6683370B1 (en) 2003-04-15 2004-01-27 Motorola, Inc. Semiconductor component and method of manufacturing same
US6972480B2 (en) 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
JP2007528120A (ja) 2003-07-03 2007-10-04 テッセラ テクノロジーズ ハンガリー コルラートルト フェレロェセーギュー タールシャシャーグ 集積回路装置をパッケージングする方法及び装置
US20050095835A1 (en) 2003-09-26 2005-05-05 Tessera, Inc. Structure and method of making capped chips having vertical interconnects
US8143095B2 (en) 2005-03-22 2012-03-27 Tessera, Inc. Sequential fabrication of vertical conductive interconnects in capped chips
US20070096269A1 (en) * 2005-10-31 2007-05-03 Mediatek Inc. Leadframe for semiconductor packages
US7622684B2 (en) * 2005-11-02 2009-11-24 Panasonic Corporation Electronic component package
US7936062B2 (en) 2006-01-23 2011-05-03 Tessera Technologies Ireland Limited Wafer level chip packaging
US20080067641A1 (en) * 2006-09-15 2008-03-20 En-Min Jow Package semiconductor and fabrication method thereof
US8604605B2 (en) 2007-01-05 2013-12-10 Invensas Corp. Microelectronic assembly with multi-layer support structure
US8395247B1 (en) * 2009-06-29 2013-03-12 Integrated Device Technology, Inc. Method and apparatus for placing quartz SAW devices together with clock/oscillator
US8359927B2 (en) * 2009-08-12 2013-01-29 Freescale Semiconductor, Inc. Molded differential PRT pressure sensor
JP5796956B2 (ja) 2010-12-24 2015-10-21 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 回路装置およびその製造方法
US9236331B2 (en) 2014-02-25 2016-01-12 Freescale Semiconductor, Inc. Multiple die lead frame
US11088055B2 (en) * 2018-12-14 2021-08-10 Texas Instruments Incorporated Package with dies mounted on opposing surfaces of a leadframe

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2582013B2 (ja) * 1991-02-08 1997-02-19 株式会社東芝 樹脂封止型半導体装置及びその製造方法
US5096852A (en) * 1988-06-02 1992-03-17 Burr-Brown Corporation Method of making plastic encapsulated multichip hybrid integrated circuits
EP0408779B1 (en) * 1989-07-18 1993-03-17 International Business Machines Corporation High density semiconductor memory module
JPH05206365A (ja) * 1992-01-30 1993-08-13 Fuji Electric Co Ltd 半導体装置およびその組立用リードフレーム
JP2843464B2 (ja) * 1992-09-01 1999-01-06 シャープ株式会社 固体撮像装置
JPH06244231A (ja) * 1993-02-01 1994-09-02 Motorola Inc 気密半導体デバイスおよびその製造方法
US5796164A (en) * 1993-05-11 1998-08-18 Micromodule Systems, Inc. Packaging and interconnect system for integrated circuits
US5661336A (en) * 1994-05-03 1997-08-26 Phelps, Jr.; Douglas Wallace Tape application platform and processes therefor
JPH0846098A (ja) * 1994-07-22 1996-02-16 Internatl Business Mach Corp <Ibm> 直接的熱伝導路を形成する装置および方法
US5504370A (en) * 1994-09-15 1996-04-02 National Semiconductor Corporation Electronic system circuit package directly supporting components on isolated subsegments
US5523617A (en) * 1994-12-27 1996-06-04 National Semiconductor Corporation Fuse frames, programmable fuse frames, and methods for programming by fusing
US5608261A (en) * 1994-12-28 1997-03-04 Intel Corporation High performance and high capacitance package with improved thermal dissipation
US5796165A (en) * 1996-03-19 1998-08-18 Matsushita Electronics Corporation High-frequency integrated circuit device having a multilayer structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10012883A1 (de) * 2000-03-16 2001-09-27 Infineon Technologies Ag Verfahren zum Herstellen eines Packages mit mindestens zwei Speicherchips
US7807502B2 (en) 2007-05-17 2010-10-05 Micron Technology, Inc. Method for fabricating semiconductor packages with discrete components
US7964946B2 (en) 2007-05-17 2011-06-21 Micron Technology, Inc. Semiconductor package having discrete components and system containing the package
DE102014016565B3 (de) * 2014-11-11 2015-11-12 Micronas Gmbh Schaltkreisgehäuse
US10080288B2 (en) 2014-11-11 2018-09-18 Tdk-Micronas Gmbh Circuit package

Also Published As

Publication number Publication date
KR19990013381A (ko) 1999-02-25
KR100559062B1 (ko) 2006-06-19
JPH1154692A (ja) 1999-02-26
US5918112A (en) 1999-06-29

Similar Documents

Publication Publication Date Title
DE19830475A1 (de) Halbleiterbauelement und Herstellungsverfahren
DE69414291T2 (de) Eine Halbleiteranordnung und Packung
DE69131784T2 (de) Halbleiteranordnung mit einer Packung
DE68910738T2 (de) Hohle Plastikpackung für Halbleiteranordnungen.
DE102011053871B4 (de) Multichip-Halbleitergehäuse und deren Zusammenbau
DE10351761B4 (de) Sensor für eine dynamische Grösse
DE10147955A1 (de) Halbleitervorrichtung
DE68920603T2 (de) Gehäuse von integrierten Schaltungen und Herstellungsverfahren.
DE60224131T2 (de) Leiterrahmen-Packung in Chipgrösse
DE3022840A1 (de) Gekapselte schaltungsanordnung und verfahren zu ihrer herstellung
DE102009008738A1 (de) Halbleiteranordnung und Verfahren zum Herstellen einer Halbleiteranordnung
DE102014106158B4 (de) Verfahren zum Testen von elektronischen Bauteilen und Halbleiterstreifenanordnung
DE102014112174B4 (de) Anschlussrahmenstreifen mit elektrischer Isolierung von Chipträgern und Verfahren zum Bearbeiten desselben
WO2007020132A1 (de) Sensoranordnung mit einem substrat und mit einem gehäuse und verfahren zur herstellung einer sensoranordnung
DE19808193A1 (de) Leadframevorrichtung und entsprechendes Herstellungsverfahren
DE10144467B4 (de) Elektronisches Sensorbauteil und Verfahren zu seiner Herstellung
DE69624284T2 (de) Verfahren zur Herstellung von Viel-Chip-Packungen
EP0637081B1 (de) Mikrosensor mit Steckeranschluss
DE102006045900A1 (de) Halbleitermodul und Verfahren zu dessen Herstellung
DE19820319A1 (de) Halbleiterbaustein und Verfahren zu seiner Herstellung
DE19834160A1 (de) Halbleiterkomponente und entsprechendes Herstellungsverfahren
EP2052409A2 (de) Moldgehäuse in einpresstechnik
DE3486056T2 (de) Infrarotstrahlen-detektor.
EP0032726B1 (de) Magnetschranke
DE3885624T2 (de) UV-Lichtdurchlässiges Gehäuse für integrierte Schaltungen.

Legal Events

Date Code Title Description
8128 New person/name/address of the agent

Representative=s name: SCHUMACHER & WILLSAU, PATENTANWALTSSOZIETAET, 8033

8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: H01L 2350 20060101

8127 New person/name/address of the applicant

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8131 Rejection