DE19517424A1 - Flexibles Verfahren zum Erstellen eines Layouts für eine integrierte Schaltung - Google Patents
Flexibles Verfahren zum Erstellen eines Layouts für eine integrierte SchaltungInfo
- Publication number
- DE19517424A1 DE19517424A1 DE19517424A DE19517424A DE19517424A1 DE 19517424 A1 DE19517424 A1 DE 19517424A1 DE 19517424 A DE19517424 A DE 19517424A DE 19517424 A DE19517424 A DE 19517424A DE 19517424 A1 DE19517424 A1 DE 19517424A1
- Authority
- DE
- Germany
- Prior art keywords
- logic gates
- gates
- input
- polysilicon
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims description 22
- 238000002513 implantation Methods 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 39
- 229920005591 polysilicon Polymers 0.000 claims description 39
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000010420 art technique Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW083107523A TW250580B (en) | 1994-08-16 | 1994-08-16 | Layout method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE19517424A1 true DE19517424A1 (de) | 1996-02-22 |
Family
ID=21624664
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19517424A Withdrawn DE19517424A1 (de) | 1994-08-16 | 1995-05-12 | Flexibles Verfahren zum Erstellen eines Layouts für eine integrierte Schaltung |
Country Status (2)
| Country | Link |
|---|---|
| DE (1) | DE19517424A1 (zh) |
| TW (1) | TW250580B (zh) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0095418A1 (fr) * | 1982-05-25 | 1983-11-30 | Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux - E.F.C.I.S. | Circuit intégré logique conçu de manière à simplifier son implantation sur un substrat |
| EP0087472B1 (en) * | 1981-09-14 | 1987-09-02 | Ncr Corporation | Process for making electrical contact to semiconductor substrate regions |
-
1994
- 1994-08-16 TW TW083107523A patent/TW250580B/zh active
-
1995
- 1995-05-12 DE DE19517424A patent/DE19517424A1/de not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0087472B1 (en) * | 1981-09-14 | 1987-09-02 | Ncr Corporation | Process for making electrical contact to semiconductor substrate regions |
| EP0095418A1 (fr) * | 1982-05-25 | 1983-11-30 | Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux - E.F.C.I.S. | Circuit intégré logique conçu de manière à simplifier son implantation sur un substrat |
Also Published As
| Publication number | Publication date |
|---|---|
| TW250580B (en) | 1995-07-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OP8 | Request for examination as to paragraph 44 patent law | ||
| 8127 | New person/name/address of the applicant |
Owner name: HOLTEK SEMICONDUCTOR INC., HSINCHU, TW |
|
| 8139 | Disposal/non-payment of the annual fee |