TW250580B - Layout method - Google Patents
Layout methodInfo
- Publication number
- TW250580B TW250580B TW083107523A TW83107523A TW250580B TW 250580 B TW250580 B TW 250580B TW 083107523 A TW083107523 A TW 083107523A TW 83107523 A TW83107523 A TW 83107523A TW 250580 B TW250580 B TW 250580B
- Authority
- TW
- Taiwan
- Prior art keywords
- directional
- gate structure
- logic gate
- layout method
- input end
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
- 238000002513 implantation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW083107523A TW250580B (en) | 1994-08-16 | 1994-08-16 | Layout method |
DE19517424A DE19517424A1 (de) | 1994-08-16 | 1995-05-12 | Flexibles Verfahren zum Erstellen eines Layouts für eine integrierte Schaltung |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW083107523A TW250580B (en) | 1994-08-16 | 1994-08-16 | Layout method |
Publications (1)
Publication Number | Publication Date |
---|---|
TW250580B true TW250580B (en) | 1995-07-01 |
Family
ID=21624664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW083107523A TW250580B (en) | 1994-08-16 | 1994-08-16 | Layout method |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE19517424A1 (zh) |
TW (1) | TW250580B (zh) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4397076A (en) * | 1981-09-14 | 1983-08-09 | Ncr Corporation | Method for making low leakage polycrystalline silicon-to-substrate contacts |
FR2527868A1 (fr) * | 1982-05-25 | 1983-12-02 | Efcis | Circuit integre logique concu de maniere a simplifier son implantation sur un substrat |
-
1994
- 1994-08-16 TW TW083107523A patent/TW250580B/zh active
-
1995
- 1995-05-12 DE DE19517424A patent/DE19517424A1/de not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
DE19517424A1 (de) | 1996-02-22 |
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