DE1801073B2 - Verfahren zum herstellen von halbleiterbauteilen - Google Patents

Verfahren zum herstellen von halbleiterbauteilen

Info

Publication number
DE1801073B2
DE1801073B2 DE19681801073 DE1801073A DE1801073B2 DE 1801073 B2 DE1801073 B2 DE 1801073B2 DE 19681801073 DE19681801073 DE 19681801073 DE 1801073 A DE1801073 A DE 1801073A DE 1801073 B2 DE1801073 B2 DE 1801073B2
Authority
DE
Germany
Prior art keywords
strip
connection
terminal
plastic
punched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19681801073
Other languages
German (de)
English (en)
Other versions
DE1801073A1 (de
Inventor
Robert Elwood Metzger Robert William jun Rittmann Albert Deitz Sayers Eugene Hill Kokomo I-d Buck (V St A )
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motors Liquidation Co
Original Assignee
General Motors Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Motors Corp filed Critical General Motors Corp
Publication of DE1801073A1 publication Critical patent/DE1801073A1/de
Publication of DE1801073B2 publication Critical patent/DE1801073B2/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/461—Leadframes specially adapted for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49826—Assembling or joining
    • Y10T29/49828—Progressively advancing of work assembly station or assembled portion of work
    • Y10T29/49829—Advancing work to successive stations [i.e., assembly line]

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Thyristors (AREA)
DE19681801073 1967-11-29 1968-10-01 Verfahren zum herstellen von halbleiterbauteilen Pending DE1801073B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US68658967A 1967-11-29 1967-11-29

Publications (2)

Publication Number Publication Date
DE1801073A1 DE1801073A1 (de) 1970-03-26
DE1801073B2 true DE1801073B2 (de) 1973-04-19

Family

ID=24756931

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19681801073 Pending DE1801073B2 (de) 1967-11-29 1968-10-01 Verfahren zum herstellen von halbleiterbauteilen

Country Status (5)

Country Link
US (1) US3581387A (enExample)
DE (1) DE1801073B2 (enExample)
FR (1) FR1592313A (enExample)
GB (1) GB1181336A (enExample)
NL (1) NL6817115A (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1157498B (de) * 1959-09-29 1963-11-14 Stig Martin Lindblad Loesbare Befestigungseinrichtung fuer Kraftfahrzeug-Sicherheitsgurte u. dgl.
US3763403A (en) * 1972-03-01 1973-10-02 Gen Electric Isolated heat-sink semiconductor device
US4012765A (en) * 1975-09-24 1977-03-15 Motorola, Inc. Lead frame for plastic encapsulated semiconductor assemblies
DE2608250C3 (de) * 1976-02-28 1985-06-05 Telefunken electronic GmbH, 7100 Heilbronn Verfahren zum Thermokompressions-Verbinden von auf Halbleiterkörpern befindlichen Metall-Anschlußkontakten mit zugeordneten Gehäuseanschlußteilen und Vorrichtung zur Durchführung des Verfahrens
DE2714145C2 (de) * 1976-03-31 1985-01-10 Mitsubishi Denki K.K., Tokio/Tokyo Gestanzte Metallträgerplatte für die Herstellung von kunststoffummantelten Halbleiterbauelementen
JPS58209147A (ja) * 1982-05-31 1983-12-06 Toshiba Corp 樹脂封止型半導体装置
IT1213139B (it) * 1984-02-17 1989-12-14 Ates Componenti Elettron Componente elettronico integrato di tipo "single-in-line" eprocedimento per la sua fabbricazione.
US6159770A (en) * 1995-11-08 2000-12-12 Fujitsu Limited Method and apparatus for fabricating semiconductor device
US7446383B2 (en) * 2003-09-16 2008-11-04 Koninklijke Philips Electronics N.V. Electronic device mountable onto a substrate using surface mount techniques, and method
US7602054B2 (en) * 2005-10-05 2009-10-13 Semiconductor Components Industries, L.L.C. Method of forming a molded array package device having an exposed tab and structure

Also Published As

Publication number Publication date
FR1592313A (enExample) 1970-05-11
GB1181336A (en) 1970-02-11
US3581387A (en) 1971-06-01
DE1801073A1 (de) 1970-03-26
NL6817115A (enExample) 1969-06-02

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