DE1774338A1 - Rechenanlage - Google Patents

Rechenanlage

Info

Publication number
DE1774338A1
DE1774338A1 DE19681774338 DE1774338A DE1774338A1 DE 1774338 A1 DE1774338 A1 DE 1774338A1 DE 19681774338 DE19681774338 DE 19681774338 DE 1774338 A DE1774338 A DE 1774338A DE 1774338 A1 DE1774338 A1 DE 1774338A1
Authority
DE
Germany
Prior art keywords
memory
information
field
peripheral device
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19681774338
Other languages
German (de)
English (en)
Inventor
White Emery Albert
Harmon Sherril Allan
Hovey Ronald Sheldon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of DE1774338A1 publication Critical patent/DE1774338A1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Communication Control (AREA)
  • Bus Control (AREA)
DE19681774338 1967-05-29 1968-05-28 Rechenanlage Pending DE1774338A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US64205667A 1967-05-29 1967-05-29
US64783367A 1967-06-21 1967-06-21

Publications (1)

Publication Number Publication Date
DE1774338A1 true DE1774338A1 (de) 1971-12-30

Family

ID=27093924

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19681774338 Pending DE1774338A1 (de) 1967-05-29 1968-05-28 Rechenanlage

Country Status (7)

Country Link
JP (1) JPS5631612B1 (fr)
BE (1) BE715773A (fr)
DE (1) DE1774338A1 (fr)
FR (1) FR1566127A (fr)
GB (1) GB1220144A (fr)
NL (1) NL6807612A (fr)
SE (1) SE344375B (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL182178C (nl) * 1970-04-01 1988-01-18 Digital Equipment Corp Dataeenheid met een adresseerbaar opslagorgaan.
JPS58114812U (ja) * 1982-01-29 1983-08-05 カルソニックカンセイ株式会社 ストレ−ト・フロ−式消音器

Also Published As

Publication number Publication date
FR1566127A (fr) 1969-05-02
NL6807612A (fr) 1968-12-02
BE715773A (fr) 1968-10-16
SE344375B (fr) 1972-04-10
GB1220144A (en) 1971-01-20
JPS5631612B1 (fr) 1981-07-22

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Legal Events

Date Code Title Description
OHJ Non-payment of the annual fee