DE1303416B - - Google Patents

Abstract

1,061,361. Editing data. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 11, 1965 [April 6, 1964], No. 5906/65. Heading G4A. In an electronic data processing system, data characters to be edited are transferred selectively and successively under partial control of a bi-stable device from a first (" source ") storage field to a second (" pattern ") storage field initially containing control and data characters (e.g. decimal point), whereby at the conclusion of an editing operation the second field contains selected characters from the first field selectively interspersed with data characters of the second field. Bytes each have 8 bits and comprise two binary-coded decimal digits or one such and a sign (" packed " format), or one such digit plus 4 zone bits (" unpacked " format). Provision is made for interchanging the two halves of a byte in a register to simplify test on a half, testing being done generally by subtracting a constant from the number and seeing if the result is zero. The bi-stable device referred to above is a " significance trigger " which is 0 if the next " source " character is presumed non-significant and 1 if significant. The trigger is set to 1 if the " source " character is non-zero, or when a " significance start " control character is detected in the " pattern " field, and set to 0 when a " field separation " control character is detected. The characters of the " pattern " field are accessed from memory in turn. Those not control characters are retained in the " pattern " field if the "significance trigger " is at 1 but replaced by fill characters if at .0. " Field separation " control characters are replaced by fill characters. Detection of a " significance start " control character or a " digit select " control character results in the accessing of the. corresponding " source " character. If this is non-zero or if the "significance trigger " is at 1, it replaces the control character in the "pattern " field after being " unpacked " by insertion of zone bits 1111. Otherwise the control character is replaced by a fill character. The editing operation is initiated by an instruction word containing an OP code specifying either normal, editing as above or the latter plus the additional feature of storing the address in the "pattern " field of the highest significant character in the "source" field when this is detected through switching of the " significance trigger ". This facilitates later insertion of e.g. a currency symbol. The editing instruction word also specifies the number of bytes in the " pattern " field and the addresses of the highest order bytes of the " source " and " pattern " fields. These addresses are each specified by specifying a number and a register, the contents of the register being added to the number to get the address. Detection of a sign character in the " source " field sets to 1 a trigger to indicate that a sign is present, and if the sign is negative sets a further trigger to 1 to indicate this. This will cause the " significance trigger " to be set to 1. The second sign trigger and another trigger set to 1 in the presence of a non-zero " source " digit can be used to control subsequent (unspecified) operations. Reference has been directed by the Comptroller to Specification 954,801.

Description

1 \ 2

iosind

In data processing systems, memories - the third operandTind are always in an even-un-

Plütze or register marked by addresses, even contain storage space, and thus the

For the sake of simplicity, the instructions become an address of the third operand without difficulty

Program sequence obtained from the address of the second operand in the order in which it is obtained

Execution in memories of consecutive addresses 5

saved. In this way, it is possible to obtain the address for the after-index greater than the one in the main purpose of the instruction "branch if the instruction address is incremented" is to increment and test a first instruction. For this purpose, a Be is an index value. In the "branch, if index large-error counter is provided, which with the execution of each ßer" operation, the second operand (in /? - 1) is advanced to the instruction by one. The new inio is added to the first operand (in R 1) and the sum of the incremented address is the address of the next algebraically compared with the third operand. Command. If the sum is greater than the third operand, it is also known to change an address on a special basis to the branch address as the next instruction identifier. One of these method addresses is used. If the sum is lower than the indexing, which is triggered by a character in the third operand or equal to the third operand, and causes the address contained in the instruction, the program is continued with the instruction, by one in an index register whose address is in the command counter. The amount just included is increased or decreased. The instructions described are similar to the instructions “Purpose of the invention is to create a branch if index is lower” and “Branch, proceed to address modification. The invention relates to a method for a stored if the sum is less than or equal to the third operand programmed in the memory.

system with a device for decoding The "branch if index is greater" instruction a branch instruction, which is a branch on the basis of one in FIG. 2 execution address shown and a first and second address for a microprogram-controlled data pool, for example first and second operands defined. The processing plant. of which only the one to carry out The invention is characterized in that the following parts necessary for this command are shown, he method steps take place: to be purified. In the connections between the \ ..... Jt-J / -. j circuit blocks shown are optional

a) Add.t, on of the beii-n operand values. _{30 Finding} connections between the blocks

b) Comparison of the sum of the two operands with one according to the program steps AND circuits third operand to think of switched by a third. To the F i g. 2 clearer Address is specified, where you make the address of the, these AND circuits are omitted, third operand from the binary address of the data processing system of the present pickling range Operands according to an OR example are based on processing byte by byte. Each link with the binary value "1" in the byte comprises eight bits.

desired position is obtained, V, VTDGS R, M and W are registers that

c) Calling the next instruction at the branch j ^{e have eight} bit positions. Mommy of the register address. if the comparison has a previous ^ninth bit position in which a Pantatsbencs result delivers, or a previous ⁴ ° ^blt is called up. Since this bit is only a check address if the comparison is used for another purpose, it should be. the following description of the result does not need to be mentioned any more.

A and B are registers that the inputs to

Expanses. Represent features, advantageous configurations of an arithmetic-logic unit ALE,

around! Further developments of a system for implementation 45 The arithmetic-logic unit ALE is designed in this way

of the procedure, the interclaims are to be developed that they all in a data processing

to take. arithmetic operations arising from the system.

The following should be based on the execution of the haulage. In addition, she also performs logical

failed ■ · Branch if the index is greater than «operations such as the AND function, ά, ύ, are explained

the. such as the correct address modification * - 50 ODF.R function or the exclusive OR radio

Vorrichumg works. tion. This means that every single bit has one

I i g. I shows the format of the. \ branches ns. if In- information supplied via register A with the

dex largervr instruction, when the corresponding bit of a command is executed via register D

Address modification takes place; information is compared. The ALE is

F i g. 2 represents a block diagram of the parts of 55 but also able to match the four lower bits with the

Data processing system to swap the four higher bits of a byte when executing,

tion of the in f i g. I can be used. The in F i g. 2 also includes the circuit

When executing the »Branch, if In- the main memory HS, its output with

dcx greater « instruction (Fig. 1) , the content of a register R is connected. As an address register for

General register, the address of which is controlled by Bl Oa the Hauptspekhere HS , the two registers M

is drawn. to the D 2 field added to the effective and N. In a decoder DBC the addresses

Form branch address that is decoded in branch »- before being fed to memory. The main-

fold the next command determined. The field R 1 also contains memory in addition to the memory locations

indicates the storage location of the first operand. sixteen registers, so-called general registers,

the field R i the storage location of the second operand 85 e.g. Rl, Rl, Ri with 32 bit positions each,

the. The storage location of a third operand. The following description of the control

is sleeping! to the memory of the second operand tion for the command "branch if Index

an and is always odd, ie. the second and greater ” assumed a state in which

3 4

the instruction is read out of the memory and decoded / - brought to registers. In the next micro sequence, the bytes of the command are stored in the command register, the address RI from the '/' register in the address (not shown). Register M and / V are also brought, and the content of the 'f-R is assumed that at this point in time the register / -gisters = in its four high bit positions the address R 1 of the 5 by one reduced,

The fourth byte (bits 24 to 31) of the general bit positions of the /. Register the address of the all-register R 1 is now placed in the / i-register contain the general register /? 3 . It is also indicated and in the arithmetic-logic unit that the content of the general register is the content of the JL register, which is the fourth byte of the address / 32 to the relative address D 2 io formation in /? 3 -Register contains, added. The sum was added and the total, which is the effective result, is returned to the Λ register and represents the branch address, to which the address register U was saved in the next step, to which and V was brought back. General register R 1.

It is assumed that the last one in the following steps will be the third bytes

Step of reading the command following micro 15 (bits 16 to 23) from the general registers R 1

step the registers L and T so that the and R add 3 and in the third byte position of the

four bits that characterize the address of the register R 1 - general register R 1. In the next

draw, the second bytes (bits 8 to

gisters to be brought. In addition, in this 15) the registers /? 3 and Rl are combined

Command »Branch, if index is greater«, the bi- ao addict and in byte position 2 of the register R 1

nary number 0011 is stored in the four lower bit positions of the. The same thing then happens with the harvest

T registers brought. The address i * n T register byte position.

later selects the general with its high places. The

Register (address Rl) , while the binary (M) Il four high bits of the K register with the binary value

determines the bit positions within the register. 35 0001 subjected to an OR function and the

The following list shows the addresses of the ν rschiegconis brought into the K register. Purpose of this op-

those bytes. ration is the address of the general register

Byte address bit positions ^{Λ3 to be} increased by one if /? 3 is an even number,

_ and leave this address unchanged if Ki

^{4 Bvte} ° ⁰¹ '- ^{24 to 31} 30 is odd. As mentioned regretfully, the

3rd byte 0010 = 16 to 23 address of the register /? 3 by the four high bits

2nd byte 0001 = 8 to 15 marked in the K-Registcr. If the address of the

1st byte 0000 - 0 to 7 of register R 3 is increased by one, you get the

Address of the general register R 2. because the purely this microstep will have the bistable toggle switch contained in part of the 35 gister /? 3 and /? 2 adjoining addresses operation codes; Except the address /? 3 is odd, in lines G 4, G 5 and G 6, which forms the 011- assigned to the command »Which case as result again the address /? 3 branch, if index is greater?«. The address of the third open state is thus checked, and it is included in a series of microsteps with the start of a series of microsteps in the address of the second operand, which is identified by the R 3 field. gone who are performing the machine operation. So the programmer has it by choosing the In this step it is also checked whether the four addresses of /? 3 in hand, whether the result of the high bits of the T register are not equal to zero. Operation of the content of R 1 plus the content of R 3 with In the next step, the content of the K-Re- the value in the register /? 2 is compared, which is the lower-digit part of the effective 45 and thus a comparison branching address is brought into the D register. or whether the result of the operation content of R 1 The contents of the K-register must be shifted compared plus content of R3 with the contents of R3 because it is kept for the following operations and therefore then always only one branch of must and the K register is otherwise required comparison branch is continued,
will. 50 For the determination of the next to be executed In a further step, the fourth low instruction is transferred at this point in time to the content of the bits of the / register which identify the address of the general address register U and K in the address register M register R 3 brought the ß-register in and N. As already explained above, the arithmetic-logic unit in the four high marks draws the address in the registers U and K now places and there added to 0000 0011, so 55 the register /? 2, which gives the third operand, this address the Identifies byte 4 of register R 3. Because the low digits (bits 7 and 8) of the draws. The result will be in register K, K registers are 00, the byte containing the bits will include 0 to 7 - the s'nd the highest digits. In the next step, the in the address bits of the general register /? 2 - read out from the registers (J and V addresses in the addresses · 60 memories.

register M and N brought, and the value of K-Re- The content of the Λ register is checked whether

gisters is decreased by one. the operand R 2 is zero. For this Aitsfüh-

In the next 'cycle, the information that is assumed in rungsbeiaptel is that RlΦ0 . In

The address given by the i.spisterM and / V for this step will also contain the content of the highest

R 3 of the main memory is contained in the R-real bits of the A1 register in the register !, ge ·

register brought. The memory is regenerated and brought.

The content of the ^ register is now via the arith- The content of the /? register is now

metic-logical unit in the previously deleted halt of the L register subtracted, and if the sum

νοα content Rl and content R $ is greater than content Rl, the comparison is made to a sequence of Mtkrosehfitteti. In the event of equality, the content of the register is recognized, whereupon the comparison process is carried out with the lowest byte. The last of the micro-steps triggered in the event of an inequality brings the content of the Ü-fteghiter into the / 'register. It should be mentioned again here that the D register now contains the lowest part of the branch address that was initially contained in the V register. In the next step, the contents of the i / register are brought into the / register so that the next macro instruction can now be taken from this effective address, which resulted from the "branch if index is greater" instruction. In the next step, the /. Register is emptied.

Claims (4)

Patent claims: 1. Method for a stored-program electronic data processing system with a Means for decoding a branch instruction containing a branch address and defines a first and second address for a first and second operand, characterized in that that the following procedural steps take place: a) addition of the two operand values, 10 b) Comparison of the sum of the two operands with a third operand, which is replaced by a third address is specified, the address of the third operand from the Binary address of the second operand according to an ODBR link with the binary value »l« is obtained in the desired location, c) Call the next instruction at the branch address if the comparison is a predefined result yeast, or retrieval of a predefined address. if the comparison gives a different result. 2. Memory-programmed electronic data processing system for carrying out the method according to claim 1, characterized in that a device for deriving the third address from the second address is provided. 3. System according to claim 2, characterized in that said device is a OR gate is the second address and the binary value "!" To form the third address combined. 4.! Ipe reprogrammed electronic data processing system for carrying out the method according to claim 1, characterized in that said predetermined address is from an instruction counter is generated. 1 sheet of drawings