DE1499200A1 - Data processing system with priority-controlled program interruption - Google Patents

Abstract

1,061,361. Editing data. INTERNATIONAL BUSINESS MACHINES CORPORATION. Feb. 11, 1965 [April 6, 1964], No. 5906/65. Heading G4A. In an electronic data processing system, data characters to be edited are transferred selectively and successively under partial control of a bi-stable device from a first (" source ") storage field to a second (" pattern ") storage field initially containing control and data characters (e.g. decimal point), whereby at the conclusion of an editing operation the second field contains selected characters from the first field selectively interspersed with data characters of the second field. Bytes each have 8 bits and comprise two binary-coded decimal digits or one such and a sign (" packed " format), or one such digit plus 4 zone bits (" unpacked " format). Provision is made for interchanging the two halves of a byte in a register to simplify test on a half, testing being done generally by subtracting a constant from the number and seeing if the result is zero. The bi-stable device referred to above is a " significance trigger " which is 0 if the next " source " character is presumed non-significant and 1 if significant. The trigger is set to 1 if the " source " character is non-zero, or when a " significance start " control character is detected in the " pattern " field, and set to 0 when a " field separation " control character is detected. The characters of the " pattern " field are accessed from memory in turn. Those not control characters are retained in the " pattern " field if the "significance trigger " is at 1 but replaced by fill characters if at .0. " Field separation " control characters are replaced by fill characters. Detection of a " significance start " control character or a " digit select " control character results in the accessing of the. corresponding " source " character. If this is non-zero or if the "significance trigger " is at 1, it replaces the control character in the "pattern " field after being " unpacked " by insertion of zone bits 1111. Otherwise the control character is replaced by a fill character. The editing operation is initiated by an instruction word containing an OP code specifying either normal, editing as above or the latter plus the additional feature of storing the address in the "pattern " field of the highest significant character in the "source" field when this is detected through switching of the " significance trigger ". This facilitates later insertion of e.g. a currency symbol. The editing instruction word also specifies the number of bytes in the " pattern " field and the addresses of the highest order bytes of the " source " and " pattern " fields. These addresses are each specified by specifying a number and a register, the contents of the register being added to the number to get the address. Detection of a sign character in the " source " field sets to 1 a trigger to indicate that a sign is present, and if the sign is negative sets a further trigger to 1 to indicate this. This will cause the " significance trigger " to be set to 1. The second sign trigger and another trigger set to 1 in the presence of a non-zero " source " digit can be used to control subsequent (unspecified) operations. Reference has been directed by the Comptroller to Specification 954,801.

Description

H99200

IBM Germany Internationale Büro-Matchinen Geseihthaft mbH

Boeblingen, April 23, 69 yoy-kr

Applicant:

International Business Machines Corporation, Armonk, N.Y. 10 50 · ^

Official file number:

Applicant's file number:

Docket 6580 WB

Data processing system with priority-controlled program interruption

The invention relates to a data processing system with priority-controlled Program interruption in which a running program or subroutine is described by a program status word assigned to this program will.

During the execution of the various operations that are carried out in programmatic Data processing systems are running, certain conditions can occur that an interruption of the normal running Require problem program. Such conditions can occur in different parts of the plant; they can through input and output units be caused, e.g. B. when an input or output operation is to be started or ended; they can also be used in so-called external Units occur, so in the console, in a timer used in the system, or in other units connected to the system that use Requests require immediate consideration; also detected errors the machine or the program may need an interruption do. Usually it is when an interrupt condition occurs

009810/1389

'»11.1111

sufficient to interrupt the currently running problem program Run the interrupt subroutine, and then run the problem program to continue.

It is known that each channel has its own control word in multi-channel transmissions to be assigned, which specifies the properties and the status of this channel for information transmission.

It is also known to have a bistable memory element for each input and output device to be assigned, which is set in the event of an interrupt request for this device; these feature elements are cyclic according to their existence queried an interrupt request. Priority between the requests is not taken into account.

In the present invention, the selection of the one becomes a matter of urgency equipped interrupting program using program status words done in a very adaptable way. If there are several requirements of different urgency, starting in the case of the request of the lowest urgency, continuously checked whether there is still a request of higher urgency; only if this is not the case more is the case, the request for time becomes the highest priority done and then one after the other in reverse order processing of the remaining requirements.

The invention accordingly relates to a data processing system with priority-controlled program interruption, with an active program status word register (PSW register) for receiving the data describing the current program (program status word) and with a control circuit to control the program flow and to receive interrupt requests; it is characterized by several inactive ones PSW register for the inclusion of data available for description Sub-programs or interrupted programs; by the tax

Docket 6580 WB OOfSi 0/1389

Circuit for initiating a subroutine of different polarities excitable control devices, each assigned to a subroutine and which, when energized, supplement the active program status word, store them in the inactive PSW register assigned to the relevant subroutine and transfer the program status word associated with this subroutine to the active PSW register; and through between the control circuit and logic circuits inserted into the control devices after every such exchange of program status words check for further interrupt requests present »and possibly a further control device of higher priority for the renewed exchange of the program status words irritate.

If there is a pair of registers for recording for each available subroutine is provided by program status words, one of which is empty and receives the program status word of the program to be interrupted and the other of which is the program status word of the interrupting program contains, an exchange of the program status words and the transition from a running program to a subroutine can be made »If the following * check shows that a If there is a request for an interruption of higher urgency, this is done Program status word just entered in the active PSV / register now is the empty register of the register pair for the interrupting program higher urgency. ' This process can be repeated *

Sin an exemplary embodiment of the data processing system according to the invention is explained on the basis of the drawings »They show:

Fig. 1: a simplified block diagram of a data processor

processing system in which the interruption system according to the invention Can be used;

009810/1389

ORiQfNAL

Fig. 2: a schematic representation of a program station

tuswortes; "'■" ■■■.

Fig. 3: a diagram indicating when the various

Types of interruption conditions related to the problem program can occur, and too what times the interrupt subroutines are started;

Fig. 4: a diagram that for the case of several at the same time

tig occurring interruption conditions indicates the order in which the problem program and completes program status words associated with the various interrupt subroutines and stored;

Fig. 5: a block diagram of the circuit with the help of which

it is determined whether a requested interrupt according to the currently used program status word may or may not take place, and

Figure 6 is a block diagram of the circuitry used for the

The system determines the priority order of the various interruptions.

Fig. 1 shows a block diagram of a machine in which the interrupt system according to the invention can be used. In this diagram, block 1 represents a core memory which has a main memory Z for storing macro instructions, other control words and data, all of which can be of different lengths, and a working memory 3 which takes on the function of registers for the arithmetic operations to be carried out 8-bit storage locations are addressed by address register 5; the stored 8 bits each form a byte and are read out into the data register 19 in parallel. The writing of data takes place under the control of the blocking circuit 4 assigned to the memory in over-

Docket 6580 WB 00981J / 1389 -> ^?

agreement with the · Inhalt.de s register 19; Block 6 represents one. Read-only memory in which macro instructions are stored. The microinstructions are read out from memory locations in sense amplifier locking circuits 8 which are determined by the address register 7. Once decoded, they are used to control the operations of the computer system. The control circuits are represented by block 9, among other things they comprise the circuits 10 and 11, which are used to control the interruptions. The latter circuits and their mode of operation are explained in detail in connection with FIGS. The blocks 12 provide the parts of the system from which an interrupt request can originate. Arithmetic and logical operations are carried out in the arithmetic “Werk'lS. The two operands with which the arithmetic and logical operations are to be carried out, ¹ are transferred to the buffer registers A (13) and B (14) via the lines A (13) and B (14) (17) and passed on from there to the arithmetic unit. The signals representing the results were put on the line Z, (15) - from where they are transferred to one or more of the registers 19 to 25. These "Registers serve different purposes: Register 19 is how. already explained, used as main memory data register: Register 20 serves as an instruction counter, the values stored in it 21 are transferred to address register .5; Register 21 is used as an intermediate address register, the values stored in it are used via the address register 5 to call up the memories of the main memory 1. or via the address register 7 for addressing the · read-only memory =, 6., The ^: remaining registers 22 to 25 'are used for the temporary storage of the operation code, the condition code, the length code and status bits, "partial addresses or other information" In connection with the program executed in each case, the meaning is * The number of registers is of course not limited to the number of the "" * specified in the drawing. The iri deri registers stored values can, as shown in the diagram, the * different lines.

und.Ädressenregisters who are supplied; so. z » ⁵ © ^ can be read out from the main- '· 2 in-4ä.s data register.f L9 © Datefa. . übfer: the "ijeitun'g ^13; ''

the buffer register 16, and the arithmetic unit 10 passed to every other register will.

In the system shown in Fig. 1, the execution of problem programs controlled by a sequence of macro instructions; any of these macro instructions specifies an operation to be carried out which is carried out under the direct control of a sequence of macro instructions. Of the Operation code of each macro instruction determines this operation, the

However, bits of the macro instructions are not used directly to control the circuitry of the system; on the other hand, the operation code stored in one of the registers, in cooperation with the control circuits 9, reads out a first microinstruction from the fixed value memory 6. The address of the next microinstruction is at least partially contained in the preceding microinstruction, the bits required to complete the address depend on the conditions prevailing in the system at the time and on the operation code of the macro instruction. "^'-. · ^■■': ■■ '■ ■ ·' - ■ '- ■■ - ■ / ■ ■■■■ - · · ..-....." ■ · "*. \ u / iVi-.yr [s

After executing the sequence of microinstructions corresponding to a macroinstruction the next macro instruction is read from the memory location of the main memory, which is determined by the instruction counter 20 and the problem program will continue.

In the computer system described, the execution of all programs is carried out by a superordinate program, which is referred to below as the monitor program; if _f . supervised,. "If.several programs, each of which consists of a sequence of.Makrqin_struktip.nenf., are to be carried out, this Mpnitoipr.ograrniri determines the order in which they are carried out; it also controls the subroutines that are included in the Occurrence of interruption conditions in the system become necessary - . _R .... _ ...

During the execution of _: Problem programs, d works under the control of one provided by the monitor program. Control word, which is referred to as the program status word .. (PSW}.

Docket 6580 WB 003810/1389 _gAD

different interruption subroutines are also supported by Art the subroutines use certain PSWs. The one contained in the PSW 's Information shows the current status of the programs as well as the existing relationships and conditions in the system Purpose, it is constantly being corrected and completed. Among other information it contains, for example, the address of the next macro instruction. For direct control of a program that is currently running, this is currently used or active PSW in a memory section provided for this purpose the main memory 3 included; certain parts of the PSW in addition, in registers, interlocking circuits, or the like Temporary storage facilities are given. Inactive PSW's, the programs that are not currently being executed are in Fixed locations of the main memory 2 provided for this purpose. As a program is interrupted, the PSW assigned to it is saved as a "old" PSW entered in the main memory and a "new" PSW, which is to * Control of subsequent operations is applied, transferred to the working memory. These PSWs contain the one for an interruption at all times and later resumption of a program.

The following is a more detailed description of the function of the PSW's and the functioning of the interruption system.

In Fig. 2, the PSW 26 used in the system is shown schematically consists of the bit positions 0 - 63, which are grouped in fields 26A to 26K are. Below is an explanation of what is stored in these fields Information and the control functions performed by them are given. "

Field 26A - Bits 0 through 7 - SYSTEM MASK

When a request for an input / output or a The bits of the system mask are used for "external" interruptions

Docket 6580 WB 009810/138

'-β- _t , U99200

determine whether such an interruption can currently take place, i.e. is allowed or not. The bit positions 0 to 6 correspond to seven different channels via which the input / output units are connected to the computer system; Bit position 7 is assigned to the units that require an external interrupt program can do. A "0" bit in one of these bit positions causes the execution of the corresponding subroutine to be postponed will; a "1" bit indicates that the subroutine can be executed. The purpose of these interruptions and what they cause conditional operations will be explained in more detail later.

j The system mask of the active PSW is in the main memory and above

. ·

also stored in interlock circuits.

Field 26B - Bits 8 through 11 - MEMORY PROTECTION CODE This 4-bit code defines the areas of the main memory that are accessible for the instructions of the program currently running. If the memory protection code does not match the memory code contained in a memory code used / address used to address the main memory, an interruption of the program is necessary.

The memory protection code of the active PSW is in the working memory and contained in a register of the computer system

■■■ - '■ - ■ "I'

Field 26C - Bit 12 - Not used. \

Docket 6580 WB

009810/1389

OBlOiNALtNSPECTED

Field 26D - Bit 13 - MACHINE TEST MASK '

This bit is used to determine whether there is a machine check interrupt .can take place or not. Such an interruption is requested if an error is found in the operation of the computer system became. If this bit is a "1", the interruption is initiated; however, if this bit is a "0", the currently running bit becomes Program continued.

Field 26E - Bit 14 - RUN / WAIT

If this bit is a "0", the computer executes instructions she runs". If, however, this bit becomes "1", the execution of Instructions interrupted and the system waits until the program is interrupted.

Field 26F - Bit 15 - MONITOR / PROBLEM

If this bit is a "1", then the computer system is in the problem program status, the programs reach normal to ₅ A base columns. If this bit becomes "0", the computer system is in the monitor status, in which only special functions can be carried out; all other functions lead to an error display.

Bits 13, 14 and 15 of the active PSW are in memory are stored, bits 13 and 14 are also included in interlock circuits.

65βο WB 009810/1389

Field 26G - Bits 16 to 31 - UXTER.BRECHUNGSCODE -, ·, ...

This 16-bit code is used to indicate the reason that a
Caused interruption; For the various types of interruption, it determines both the unit that requested an interruption program and the reason or condition that caused the interruption
made necessary. . ·

The interrupt code is not included in the active PSW; these
Information is only fed to the PSW when it is ...
Interruption is transferred to main memory as old PS \ * /.

Field 26H - Bits 32 and 33 - IX \ STRUKTIOXSL · AEXGEXC ODE ''"'"'''"' ^Λ "'"'^;

Mixkr.oinsiruktiönen of different lengths are used in the appendix, j "The 8-ii It-ByLe _- S;,. From which an instruction. Is composed, slr.d · · ■ ': ■ - ■" ■■ in successive Store : r place ή ". The instruction!. '1 .. ^ tI ₁ ^
code is used by the monitor program in the case of a machine check number. "InterruptjOdei", the .Prograrum check interruption is used, xxm the address of the "first byte of the instruction which produced the interruption;

called to determine. Bits 32 and 33 are used to determine the length of the_.
Instruction currently being executed or just being completed: Sie- «- <- i: c? F; ·. *. "» -, - of every macro instruction whose bit positions 0 and 1 correspond to the length of the
Mark instruction inserted into the PSY / so that the memory address

of the first byte of the instruction can be identified. '

Field 261.- Bits 34 and 35v - "'- BEa) iN6Ü ^ GSCOOE V ^' * '"' - '·. ·''''"'"'"-' = ^; ^ ^V ''■" ■

This code identifies ^ -conditions, die-beitd'e ^? «·»> · ■■ 13Cl

Execution previous ^ Rgei ·? ·. tr, computer system

are. In the active PSV / this code is in decoded form in the working memory contain:

Bits 34 and 35 4-bit code of the active PSV / 'a.

00 1000

01 0100

10 0010

11 0001

When executing an instruction in the course of which a code is written into the Condition register of the system is brought, the in PSW contained 4-bit code changed to reflect the result of the executed To mark operations. Dor code stays that long unchanged until another instruction changes the condition register.

Field? .6J - Bits 36 to 39 - PROGRAM-PRUeFMASKC '

These bits were used to determine whether a .ut / .t was requested Program exam interruption may or may not occur; such An interruption is required after an error has been detected in the program.

Each of the 4 bits corresponds to one of four interruption conditions, which can occur in the computer system. When a soK occurs.

Condition is considered d * corresponding: VIt, it is an 'M ", s> j If a program check interruption is initiated, if it is "0", however, the current program is continued.

The program check mask is part of the active PSW and therefore in the RAM included.

Field 26K- Bits 40 through 63 - INSTRUCTION ADDRESS

These bits define the address of the next macro instruction is to be carried out during the running program.

Docket 6580 WB

009810/1389

H99200

After executing a macro instruction, the address is the next Instruction of the current program both in the instruction counter of the System as well as in bit positions 40 to 63 of the active PSW. During the execution of each instruction, this address is stored in Consistent with the instruction length code included in each instruction is included, increased; the address is replaced when the normal instruction sequence is interrupted by a branch instruction will.

The interrupt system used in the data processing system described allows the interruption of running programs and the execution of interrupt subroutines which are required by conditions which occur in external units of the system, in I / O units or in the computer system itself. An interruption consists in storing the active PSW ¹ S as the "old" PSW and providing a "new" PSW ¹ S. Then the execution of the program determined by the new PSW begins under the conditions and at the point specified by the new one PSW can be defined.

There can be five different types of interruption conditions in the system appear: .

1. MACHINE TESTING

A machine test interruption is initiated as soon as an error occurs detected by the machine

0Ö9Ö10 / 1389

SAD

Docket 6580 WB " . - ■ -, ^ \ 4 *: v ^l

■ 2. PROGRAM- PRUEF-UXC- ..- ■ · ■::. · - "/, \. -

A program check interruption is initiated as soon as a Error was found in the program, e.g. an invalid operation code, an incorrect memory address or an overflow condition.

3. INPUT / OUTPUT '"■'

An input / output interruption is initiated as soon as an input / Output unit a point during the operations it performs reached, at which the monitor program must be used to determine the further work process of the system.

4. EXTERNAL '.

An external interruption is initiated as soon as the computer system from external units whose operations cannot be postponed, must be used.

5. MONITOR CALL . .... · .-.,; /.;., .. _: A monitor call interruption is triggered by a special. Monitor call. _: Instruction initiated. The main purpose of this interruption: is to switch the research system from the problem status to the monitor status ...; this is required if a PSW is replaced or changed /; shall be. . ...., -....- .. .. ::,. ,, _; "., '-'. ·> - ■ -

As already mentioned, machine testing, program testing. Input / output and external interrupt subroutines are only initiated if the corresponding mask bits of the active ¹¹ PS W s represent a "1"; if, on the other hand, the corresponding bit is a "0", an interruption cannot take place until the bit changes to "1". A monitor call sub-- —— ■

Docket 6580 WB 0 0 9 810/1389 '

refraction becomes «.k: re !; e,;:; e IA .:. 'iu; iscru. <iion introduced and i-Fiordri; t. ~. _v? * _{% v} »therefore no mask bit in PSV /.

The diagram shown in FIG. 3 indicates ₍ at what time, with B.-to-, lui the problem program,. The requirements for the various types. Of. Interruptions occur and at what time the interruptions can be made. As already mentioned, the operations defined by the macroinstructions are carried out under the direct control of a sequence of microinstructions 1 to i: which is determined by the respective macroinstruction (columns 3-OA and 30B).

Arrows in the column "Interruption requested ^1. " (30C) indicate for each type of interruption at what time, with reference to the microinstruction sequence, an .interrupt can be requested. / .... _T .-.: "

Requirements for machine testa (MASCH PRUEF) -, program ~ Exam. (PROG PRUEF) -, input / output ^. (I / O) -, and external (ZXT; interruptions can be done at any time as indicated by the pie above:] and the large brackets. The monitor call (MON RUF) breakdown is initiated by a macro instruction provided by the programmer and can therefore only be used after a sequence of micro instructions has elapsed are carried out as indicated by the arrow marked MON RUF.

Arrows; column. A ¹ break x ^ follows ¹ * (.30D) give for each 'tintcr-JM'-;break;unigJs-a'r.ttian, _i -35Uswel ^> cher time, with reference to the moral instruc- tion ■><-: ■ -'.- the execution of the interruption program begin! v ~ ir <:,

Docket 6580 "WB

0 09810/1389 8A6

when requested and when by the appropriate. Mabkenbits it has been determined that the interruption can take place.

As shown, MASCTI PRUEF and PROG PRUEF breaks initiated immediately. The sequence of microinstructions is interrupted because a Continuing the program could lead to erroneous results.

I / O and EXT interrupts are cleared after the sequence of microinstructions has expired initiated. The last macro instruction of such a sequence is used always to determine whether during the execution of the microinstruction sequence Requests for I / O or EXT interrupts have occurred.

As already mentioned, a MON RUF interruption occurs after expiry the 'sequence of microinstructions initiated.

By using the PSWs it is possible to have several at the same time to process any interruption requests that occur, to execute the most urgent interruption program first, and to process the information that are necessary for the interruption programs of lower urgency. Enter the interrupt system described several ^ conditions requiring an interruption at the same time, so the old problem program PSW are saved one after the other in the main memory, that of a first interruption (lowest urgency) corresponding new PSW transferred into the main memory, this first new PSW, after it has been changed and completed in accordance with the interruption conditions, is again stored in the main memory, the next new PSW corresponding to the one in the priority order.

Docket 6580 WB

00981071389

is assigned to the next interrupt program in the working memory transferred, etc. The execution of instructions is resumed under the control of the PSW, the last one from main memory was transferred to the main memory, i.e. the interrupt program corresponds to the highest urgency; the order of execution of the Interrupt programs are opposite to that in which the PSWs were convicted »

• In the main memory there are 10 memories each with 64 bits for the different PSWs permanently assigned. The PSWs for which these locations are intended are designated as follows:

I. Old EXT PSW

II. New EXT PSW

III. Old I / O PSW

IV. New I / O PSW '

V. Old MASCH PRUEF PSW

VI. New MASCH PRUEF PSW

VII. Old PROG PRUEF PSW

VIII. New PROG PRUEF PSW

IX. Old MON RUF PSW

X. New MON RUF PSW.

When an interruption is initiated, the active problem program PSW, after it has been modified and completed according to the interruption conditions, is stored as the old PSW in the appropriate main memory location. For a PROG PRUEF interruption, the old PSW is entered, for example, in memory location VII "old PROG PRUEF PSW ^11. Most of the bits of the PSW are

Docket 6580 WB

009810/1389

'" ^{? M} "' ~ ORWUNAL

unchanged, i.e. as it was contained in the main memory, transferred to main memory; however, as already explained, the condition code must be decoded beforehand.

When an old PSW is stored, the interrupt code is contained in bit positions 16 through 31, respectively. This code defines the reasons for the interruption as follows:

1. For an EXT interrupt, the code defines which one is external

Unit causing the interruption.

Z. For a MON RUF interruption, the code forms the information,

which, decoded by the MON PROG, is the reason for the MON RUF instruction certainly. '

3. For a PROG PRUEF interruption, the code defines the through A condition that has arisen from a faulty program requires an interruption.

4. The code is always "0" for a MASCH PRUEF interruption.

5. For an I / O interruption, the code defines the channel and the Unit that requested the interruption. '

After the old PSW is completely in the state determined by the type = of the interruption. Memory location of the main memory has been entered, the new PSW is transferred to the memory provided for the respectively active 'PSW' of the main memory. For example, if '. an old PSW in the ^Speieher-: imagine IV "old PROG PRUEF PSW" has been stored, the new PSW ■ serving PRUEF interrupt program to control the PROG,

Docket 6580 WB - /; - ^fV? ί If 1 S ■ ' ^:

009810/1389

"New PROG PRUEF PSW" was taken from memory location VIII. For the new PSW, the interrupt code is not required and will be d.i. not transferred to the main memory; the 2-bit condition codc · is decoded into the 4-bit form as already explained. Now that contains new PSW the start address and the start conditions for the monitor program, under the control of which the interrupt program runs', and the computer system starts executing instructions to the interrupt routine has ended. At this time, the PSW under whose control the interrupt program was executed will be returned to the memory assigned to it in the main memory. Then the old PSW, which is used to control the interrupted Problem program was used, entered into the memory and the Computer continues the problem program from the point at which it was interrupted.

The diagram in Fig. 4 shows the use of the PSW's for the case that two interruptions, EXT and I / O, are requested at the same time. . It is assumed that both interrupts were determined to be "allowed" at the time of the request by the corresponding mask bits, the corresponding subroutines in the order of their urgency are to be carried out.

Those indicated in column 40A. Numbers correspond to the different on Operations steps that are required for the assumed example. Columns 4OB and 40C show which program or subroutine during the individual steps "is carried out in each case u :: d

Docket 6580 WB '' BAOOBiGINAL

003810/1389. ·

■ .-. - ¹⁹ - H99200

ι ·

which PSW is contained in the main memory as the active PSW. The different programs; The problem program, EXT interruption, and I / O interruption are represented by different hatching in accordance with the explanations given for blocks 41, 42 and 43. The double columns 4OD to 4OH represent the pairs of the memory locations of the main memory permanently assigned to the different types of interruptions, which are used to store the inactive PSWs. Such a pair of storage locations I to X is provided for the old and new PSWs of one type of interruption, such as I and II for EXT interruptions, III and IV for I / O interruptions, etc. The storage of a PSW in the "old""Storage location of a pair is followed automatically by the readout of the associated" new "storage location. A detailed description of the operation steps 1 to 12 follows.

Step 1:

Execution of a problem program under the control of a problem program PSW ¹ s contained in the working memory. The "old" PSW storage locations in main memory (odd numbers I, III, etc.) are empty, while the "new" PSAV storage locations (even numbers II, IV, etc.) contain the PSWs corresponding to the various interrupt subroutines.

Step 2: ·

During the execution of the problem program, two Permitted interruptions of different urgency requested:

Docket 6580 WB,

009810/13 89

an EXT interrupt (lower priority) and an I / O interrupt (higher urgency). The problem program PSW is transferred to storage location I as an old PSW; this is the location the "lower urgency interruption of the two requested Corresponds to interruptions.

Step 3: .' :.

The new EXT interruption PSW is taken from storage location II and transferred to the working memory. There is another interruption (higher urgency) waiting for execution will not deal with the Execution of the EXT interrupt routine started.

Step 4:

The EXT interruption PSW is stored as the old PSW in storage location III convicted; this is the memory location, the higher that the interruption

, i

Urgency.

Step 5;

The new I / O PSW is read out from the storage location IV and into the Working memory saved. As no further interruptions requested execution of the I / O interrupt routine begins.

Step 6:.

Execution of the I / O interrupt routine under the control of "des I / O PSWs contained in the main memory.

Docket 6580 WB::

009810/1389

After completion of the I / O interrupt routine, the I / O becomes PSW returned to the memory location IV assigned to it.

Step 8: ·.

Dag EXT-PSW is automatically read out from memory location III and stored in the main memory. Beginning of the EXT interruption

program.
Step 9:

Execution of the EXT interrupt program under the control of the EXT-PSW ¹ S.

Step 10:.

After the EXT interruption program has been completed, the EXT-PSW is transferred to the. memory assigned to it, II is returned.

. f

Step 11:

The problem program PSW is read from memory location l and stored in the working memory. The execution of the problem program resumes from the point where it was interrupted by step 2.

Step 12:

Execution of the problem program under the control of the in the working memory included problem program FSW;

The mode of operation of the various PSWs was designed for the case of two simultaneously occurring interruption messages are described Erocket & S8Ö WB

Cases in which only a single interruption is required, or in which an interrupt program is already running interrupt are treated accordingly and therefore not here further explained. The same applies to other types of interruptions than those selected in the example.

FIG. 5 shows a block diagram of the circuit, designated 11 in FIG. 1, which is used for the mask operation which is used to determine whether or not a requested interrupt can take place at the present time, ie is permitted. The circuit shown is limited to handling I / O and EXT interrupts requested by the I / O units on channels -123-126 and by the external units on channel 127.

As noted, the system mask bits of the active PSW's 26 are used to determine whether a requested I / O or EXT interrupt is allowed. If the bit corresponding to the channel requesting the interruption (bit 0 for channel 120, bit 1 for channel 121, etc.) is' ¹ I ", it means that the interruption is allowed; a" 0 "would indicate that the Interruption must be reset at least temporarily- '■' * ■ ". . ^v - ".. '" ^w: "" -

The active PSW 26 is completely stored in the main memory 3. The bits of the system mask are also contained in the associated interlocking circuits SOO Ms 507, these circuits being in the on state if the corresponding mask

Docket 65 & ÜWB-

'008 * 10/1309'

- ²³ - H99200

Is "1", they are in the off state when the bit is "O". One of the AND circuits 530 to 537 is provided for each mask bit or for ioden of the interruption channels 120 to 127. The inputs of these AND circuits are connected via lines 510 to 517.mil dun corresponding interlocking circuits and via lines 520 to 527 to the corresponding interruption channels. An interlocking circuit in the on state applies a potential to one input line of the associated AND circuit, which prepares the AND circuit in such a way that a signal coming from the corresponding interrupt channel via the other input line passes the AND circuit. These signals appearing on the output lines 540 to 547 of the AND circuits are used to display permitted interrupt requests. The circuit shown in FIG. 5 also supplies "interruption requested" (UNT ANGEF) and "external interruption requested" (EXT ANGEF) signals on output lines 57 and 58, which are fed to the circuit shown in FIG. B and are used for display purposes that there is an interrupt request of some kind or a request for an external interruption. The signal UNT ANGEF appears at the output of the OR circuit 56, the input lines of which are connected to lines 540 to 547.

Since a plurality of I / O channels 120-126 are connected, several I / O interrupt requests can therefore occur at the same time, a priority order of these channels must be determined, if not all channels with only one exception by the mask bits 0 to 6 of the active one

Docket 6580 WB

009810/1389 ' _mD original

PSWs are defined as unauthorized. The one for this priority determination required circuit is no longer described because it is not constitutes an essential part of the present invention.

Fig. 6 shows a block diagram of the in Fig. 1 designated by 10 · Control circuit that is used to control the various. At the same time PSW operations required when multiple interrupt requests occur. This circuit determines the structure of the System predefined order of priority in which the various types of interruption programs are executed.

Block 60 represents the circuits that are under direct control a sequence of microinstructions that. Execution of the macro instructions the programs to be processed. These operations are either carried out by one at the beginning of a problem program 61 initiated signal, or by a signal on line 62; the latter appears after a macro instruction has been fully executed if there is no interrupt request, or at the beginning of an interrupt program. Those controlled by circuit 60 Operations also include ongoing changes and additions to the active PSW. .

If by signals on lines 63 or 64 the request for Permitted MASCH PRUEF or PROG PRUEF interruptions are displayed the circuit 60 causes the current execution to be terminated immediately Sequence of microinstructions and supplies signals on the output lines 65 or 66. These signals become the ones indicated by blocks 8.0D

Docket 6580 WB 0 0 9 810 * 1389

'-25-. 1A9920G

And 8OE circuits shown routed the corresponding Initiate interruptions. Used by a programmer Instruction initiated a MON RUF interrupt, sp a signal appears on the output line 67, which, for Circuit 8OC conducted, causing the required interruption.

The last instruction of a sequence of microinstructions is generated a signal on the output line 68, which is used to determine whether a. requirement has been set for an I / O or EXT interrupt.

The blocks 70 "Interrupt? ¹¹ and .72" External? "Represent simple logic circuits which, after the input of a signal on the lines 6f> or 71, perform the following function: when a UNT BEGIN or an EXT ANGEF signal is applied the input lines 57 and 58, a signal is given on the YES output line 71 or 73; if there is no request signal, a signal is generated on the NO output line 62 or 74.

With 80A' to 8OE, circuits are identified which control the following operations for the various interrupt types EXT, I / O, MON ^- RUF, PROG PRUEF and MASCH PRUEF under the control of macro instructions: Completion of the active PSW with information that the requesting unit and define the reason for the interruption; Transfer of the active PSW from the main memory to one of the "old" PSW storage locations, this storage location being due to the type of sub «

Docket. 6580 WB

■ Q0981 0/1389

refraction is determined: Spc> icherstelle "old EXT PSW * for circuit 3OA, "old I / O PSw" for 8OB, "old MON RUF * PSw" for 80C, "altc-s PROG PRUEF PSW "for 8OD and" nd "old MASCH PRUEF PSW * for 8OE; reading out the new one PSVvfe from the memory location of the main memory that is placed by the old PSVV has been stored, is assigned, and transfer of the new PSW into the working memory. After completing these operations an output signal appears on that corresponding to circuit 80 Line 68A, B, C, D or E.

The operation of the circuit arrangements shown in FIG explained below using three examples:

1. No interrupt requested;

2. A single interrupt request;

3. Several simultaneous interrupt requests.

example 1

Assume that during an Alakro instruction under the Control of the corresponding microinstruction sequence was carried out, no interruption conditions occurred in the system, and thus none Interrupt request was made.

Since no MASCH PRUEF or PROG PRUEF interrupt requests which result in an immediate termination of the macro instruction the last macro instruction in the sequence becomes the determination used whether a request for an I / O or EXT interrupt is present. The interrogation signal appearing on line 68 is passed to circuit 70. This circuit simply performs the one already mentioned «?

Docke. 6580 WB _v . _009B . _{) 0/1389}

logic function to produce one of the output signals YES or NO on lines 71 and 62, respectively. Since it was assumed that there is no interrupt request, there is no signal on the input line UNT ANGEF 57 and the sound 70 is a signal on the NO output line 62. This signal becomes Control circuit 60 conducts and here causes the execution of the next Macro instruction of the current program.

Example 2

Assume that during the execution of a problem program associated macro instruction an I / O interruption has been requested from channel 121 (see FIG. 5) and that bit 1 of the The system mask of the active PSWs that corresponds to this channel is a 1 and thus defines the interruption as permitted.

Since no MASCH PRUEF or PROG PRUEF interrupt requests that would have caused the sequence of microinstructions to terminate immediately, the last macroinstruction in the sequence is determined used whether a request for an I / O or EXT interrupt is present. The interrogation signal on line 68 is passed to circuit 70.

Since it was assumed that there was a request for an allowable interruption has been set and this is indicated by a signal on the line 57, the circuit 70 generates on the YES output line 71 a pulse applied to circuit 72. This circuit generates a signal when a request for an EXT interrupt occurs on the line 58, exercises the aforementioned function that of the circuit

Docket 6580 WB

009810/13 89 ^

70 and provides a YES or NO output signal to the Lines 73 and 74, respectively. Since it was assumed that there was only one I / O interrupt was requested, there is no signal on the line 58 and an output signal appears on the NO line 74. This signal means that an I / O interruption has been requested; this becomes clear from the following consideration: a signal on line 57 indicates that a request for an interrupt of some kind has been made, and since in the present, in the arrangement shown in Fig. 6 only two different types of interrupt requests and the absence of a signal on line 58 indicates that the request is present

does not refer to an EXT break, it must necessarily be be a request for an I / O interruption.

The query of the different types of interrupt requests is in the order of increasing urgency of the interruptions executed. In the arrangement shown in Fig. 6, only two different Urgency levels considered, but without changing the principle of the procedure, a further subdivided urgency «- scheme to be used; for example, the various I / O channels different priorities can be assigned to which by additional Query circuits (corresponding to circuits 70 and 72) can be taken into account. , '

Returning to the assumed example: the NO signal on the Line 74 is passed to circuit 8OB which does the completion

Docket 6580V ¹ IfB

009810/1389

SAO

. ■ * ■■ -

. -The active PSW. controls and the transfer of the interrupted

Program assigned old PSW from the main memory to the main. "Old I / O PSW" storage location. Since the query for EXT and I / O interrupt requests at the end of a macro instruction takes place, the active PSW at this time contains all the information that are required to resume the interrupted program after the interruption program has ended. In addition to the storage of the active PSW as old PSW in the main memory are no further data transfer or storage operations necessary. The new PSW required for the I / O subroutine is then still controlled by the circuit 8OB read out from the main memory location "new I / O PSW" and into the RAM transferred.

After these PSW transmissions have been carried out, the output signal becomes on line 68B to circuit 70 and discussed above. Inquiry operation repeated. Since it is assumed that no further interrupt requests have been made, a signal generated on NO output line 62 and passed to circuit 60, which in turn initiates the execution of the I / O interrupt routine. ·

After completion of this subroutine, "if no further Interrupt was requested, the active PSW which the dem PSW associated with the I / O interrupt routine is in the main memory location "New I / O PSW" is stored, and the 3PSW that is used for the

Docket 6580 WB. _; BAD ORIGlNAU

H99200 le

. Resumption of the interrupted problem program contains the necessary information, the memory location "old I / O PSW" read out and transferred to the main memory. The Execution of the problem program continued.

Example 3

Assume that while executing one to one The macro instruction belonging to the problem program has two requests for interruptions of different urgency, namely for one I / O and for an EXT interrupt, occurred and considered allowed were determined.

Since no requests for MASCH PRUEF or PROG PRUEF interrupts have occurred that would have caused the sequence of microinstructions to terminate immediately, the last microinstruction in the sequence is used to determine whether there is a request for an I / O or an EXT interrupt. The interrogation signal on line 68 is passed to circuit 70 which, as explained in Example 2, develops a YES output on line 71. Signals are present on the two input lines 58 and 71 of ¹ · circuit 72, so that this circuit also gives a YES output signal on line 73, which is forwarded to circuit 80A. This circuit causes the storage of the active PSW in the main memory place "old EXT PSW" and the subsequent transfer of the new PSW ^ S; required for the execution of the EXT program, from the main memory location "new EXT PSW" to the working memory. After these transmissions have been completed, the · ._.

Docket 658b WES

ÖÖS8iÖ / if89

The signal developed on line 68A is applied to circuit 70 and the polling operation repeated. Since there is a second interrupt request, a signal is present on line 57 and circuit 70 provides a YES output on line 71. Since the request; has already been taken into account for the EXT interruption by transferring the corresponding PSW ¹ s to the main memory, there is no longer a signal on line 58 and circuit 72 develops a NO output signal on line 74. This indicates, as already explained, that there is a request for an I / O interruption, and the circuit 8OB controls the storage of the old PSW in the main memory location "old I / O PSW". It is pointed out to Eb that this old PSW is the control word assigned to the EXT interrupt program which has not yet been executed. This PSW contains all the information that is required to initiate the execution of the EXT maintenance program as soon as it is transferred back to the working memory. As will be explained below, this occurs after the I / O interrupt routine has been completed, which is of greater urgency than the EXT interrupt. .

After the old (EXT) PSW has been saved, the new one is used for the I / O interruption program required PSW is read from the main memory location "new I / O PSW" and transferred to the main memory.

That which appears on line 68B after these operations are complete Signal is given to circuit 70 and the polling operation is performed repeated again. Since it was assumed that no further sub-

Docket 6580 WB

BATH ORIGINAL 009810/1389

Break requests have been made, a signal will appear on the NO output line 62 which, fed to circuit 60, executes of the I / O interrupt routine.

After completing the I / O interrupt routine and assuming that no further interrupt requests have occurred the active (I / O) PSW is stored in the main memory location * "new I / O PSW" and the PSW for the EXT interrupt program read out from the memory location "old I / O PSW" and fed to the main memory. The second interrupt program is then executed.

After completing this program as well and again assuming that If no further interrupt requests have occurred, the now active (EXT) PSW is stored in the main memory location "new EXTPSW" and the PSW, which contains the information required to resume the interrupted problem program, taken from the memory location "old EXT PSW" and entered into the working memory. The interrupted problem program is then executed continued.

In the method described, if several at the same time Interrupt requests occur, the corresponding PSW * s in the Order of increasing urgency of the subroutines stored, the lowest priority PSW is considered first; however, takes place the execution of the subroutines in the opposite order, i.e. the highest priority subroutine is executed first.

Docket 6580 WB

00981071389

With the help of the specified procedure, it is also possible to meet interruption requests to be taken into account that occur during the execution of an interruption program of a different type. If the requested The system enables the second interruption to be permitted the interruption of the running first interruption program.

From the foregoing it can be seen that as soon as the monitor program has initiated and started the execution of an interruption program, this subroutine must not be interrupted by a subroutine of the same type. If this were allowed, all information about the interrupted, originally running problem program would be lost, since the PSW assigned to the first interruption program would be entered in the "old" PSW memory location which already contains the PSW of the original problem program. This situation can be prevented by suitable use of the PSW s' mask bits: if, for example, the successive interrupt requests are I / O interruptions, the system mask of the new I / O PSW that corresponds to the first interrupt program must include all of the other I / O interruptions. Define interruptions requested by A channels as not allowed. In this way, no more I / Ar may be initiated before interruption not _there's currently running I / O subroutine is brought to an end ".

MASCH PRUEF and PROG PRUEF interruptions are immediate initiated after the occurrence of the conditions requiring the interruptions. This also becomes the control of what is to be interrupted

Docket 6580 WB BAD ORIGINAL

Program serving old PSV / "in. Doi: main memory transferred and that new, necessary for the execution of the interrupt program PSV / entered into memory. The same applies to the MOX RLT interruptions, which differ only in that sit · through macro instructions provided by the programmer are initiated.

The order of priority given by the structure of the system shown in FIG PSWs uses the given possibilities. Should z. B-. an interrupt program which, according to the circuit, has a lower priority than a second, simultaneously requested one Interrupt program before this second interruption program higher priority, you can use the mask bits of the PSW corresponding to the subroutine, lower priority, which is the first to be transferred to the main memory, so select that the mask bit corresponding to the channel requesting the higher priority interrupt is made "0", thereby causing this interrupt is defined as not allowed. This results in a very versatile and easily variable interruption method, the interruptions Different urgency in one of the programmer or the Program itself allowed to execute in a specific order.

Docket 6580 for 009810/1389

Claims (2)

- 35 PATENTAN S P R Ü C H E 1. Data processing system with priority-controlled program interruption, with an active program status word register (PSW register) for receiving the data describing the current program (program status word) and with a control circuit for controlling the program flow and for the receipt of interruption requests, characterized by several inactive PSW registers for the acceptance of data for the description of ready subroutines or interrupted programs; through from the control circuit (60) excitable control devices (80) to initiate a sub-program of different polarities, each of which has a sub-program are assigned and which, when energized, add the active program status word to the one assigned to the relevant subroutine Save inactive PSW registers and this subroutine Transfer the assigned program status word to the active PSW register; and through between the control circuit (6o) and the control devices (80) inserted logic circuits (70, 72) after each such Exchange of program status words check whether further interrupt requests are present, and which, if necessary, excite a further control device (for example, «80 A) with higher priority for the renewed exchange of the program status words. 2. Data processing system according to claim 1, characterized in that each available subroutine is assigned a pair of registers (40 D to 40H), one of which (z. B. 40 DI) is provided for receiving the program status word associated with the program to be interrupted and that others (e.g. 40 DII) contains the program status word belonging to the interrupting subroutine and to be transferred to the active PSW register; that if there is a further interrupt request at the same time, higher priority docket 6580 WB 00 9810/1389 ^: '"' ^{: ?} '- BAD ORfQINAL did the program status word of the subroutine initially considered taken from the active PSW register and into one register (e.g. 40 E III) of the register pair assigned to the second subroutine (e.g. 40 E) and from the other register (e.g. 4OE IV) of the second register pair, the program status word belonging to the second subroutine is transferred to the active PSW register and that further simultaneous interrupt requests are dealt with in the same way and the reduction of the request amounts in the reverse order is made. 009 810/1389 Docket 6580 WB 31- blank page