DE1084497B - Logistic electronic computing device - Google Patents

Description

GERMAN

The invention relates to a logistic electronic computing device.

In a logistic electronic computing device, the arithmetic operations are generally performed as a series of logical connections. It can be shown that everyone arithmetic process both on a single basic term of arithmetic (for example the Addition) and can be traced back to logical operations. With only two specified in binary code Input signals, the number of logical operations to be carried out can be very considerable be. Therefore, if a flexible computing device is required, this device must be constructed in such a way that that it can perform a great many, if not all, of the logical connections.

Previously it was common for any logical link to provide a separate logic switching element. It is obvious that with a proportionate flexible computing device a considerable number of logic switching elements must be present and that, in addition, gates and selection circles are necessary through which the information to be processed is introduced into the correct logic switching element.

With the present invention, a computing unit is proposed in which an extraordinarily high flexibility can be obtained using only a single logic switching element. the Invention is based on the application of the well-known theorem that all logical judgments about binary or boolean variables can be expressed in terms of the incompatibility judgment, such as this for example on p. 14 of the book by Weyl, "The Philosophy of Mathematics and Natural Science", is shown.

The logistic processing unit according to the invention contains a logic switching element that the incompatibility can express among a larger number of binary code signals. The invention characterizes the fact that the input signals and the signals originating from the logic switching element in one larger number of memories for binary signals and stored via gated conduction paths be channeled selectively from the memories through the logic switching element, with a selection circuit intended for successive opening and closing of selected combinations of these paths so that various logic operations are carried out with the input signals can.

Further details and advantages of the invention are given below with reference to the drawings explained. In the drawings shows:

Logistic
electronic computing device

Applicant:

Electric & Musical Industries Limited,
Hayes, Middlesex (Great Britain)

Representative: Dr. K.-R. Eikenberg, patent attorney,
Hanover, Am Klagesmarkt 10-11

Robert Justin Froggatt, Norwood Green,

Southall, Middlesex (UK),

has been named as the inventor

Fig. 1 two logic circuit elements that express incompatibility,

2 shows a subroutine unit which is used in the exemplary embodiment of the invention,
3 shows an example of an arithmetic unit according to the present invention.

As already mentioned, all logical links in the arithmetic unit can be controlled by a suitable one Represent selection of operations of a single logic switching element if this switching element expresses the incompatibility. These operations are controlled by a suitable subroutine, that regulates the input and acceptance of values from a series of digit memories that are connected to the inputs and the output of the switching element are connected.

For example, the logic switching element can be configured with an »OR lock« with negated inputs, as shown in Fig. 1 a, are formed. The way this lock works can be expressed in logical symbols generally express as:

~ sv ~ &, ie not α or not b.

To operate this lock, an input c is applied to two gates in parallel. This input c can be suppressed by inputs at α or at b , so that an output d results from the block from the threshold value "1" if there is no input at a or no input at b or no input at α and b . Only in the case that inputs at α and b are present at the same time, no output d is supplied.

The above symbolism is written as alb by Weyl. Weyl then states that ala, al (b / b), (a / b) / (alb) and (ala) I (bib) negation (~), implication (- »-), conjunction (&) or Alternation (v)

009 548/219

represent. The relationship between these notations can be seen from the following overview:

a / a = ~ α ν ~ α = ~ α. ν; ·

α / (& / δ) = α / (~ &) = ~ α ν ~ (~ &) = ~ a ν b = a- + b. ■ "" · (alb) I (alb) = ^ - (alb) = ~ (~ αν ~ &) = α &&. ""
(ala) l \ blb) = - (~ α) / (~ 6) = ~ (~ α) ν (~ fe) -α ν 6.

Optionally, an "AND lock" with a negated output, shown in Fig. 1b, can also be used to express all that ~ sv ~ & = ~ (a & b) . It can be seen that the output d follows the same law described above, that is, the output d is suppressed only when inputs are applied to α and b.

FIG. 2 shows in detail a subroutine unit used to control the operations of the arithmetic unit shown in FIG. The unit contains a function programmer 1 with two inputs. The input 2 is intended for the function required by the unit according to FIG. 3, the further input 3 comes from a shift register 4 which works as a clock generator. Connecting lines extend from the programmer 1, only one of which (reference number 5) is shown. These connecting lines are drawn through various combinations of solenoid cores 6 to earth. The cores form a pattern memory and are arranged in a number of vertical columns, each of which comprises eighteen groups of five cores each. Output lines 7 from a shift register 4 are also drawn one after the other through the columns of the coil cores 6 to earth. Further lines Ta are drawn from earth through the rows of coil cores 6 (which are horizontal in the drawing) and are connected to amplifiers 8. The output lines 8 a from the amplifiers 8 are in turn passed through a respective coil core 9 to ground. The cores 9 are also arranged in eighteen groups of five cores each, but there are only five columns and each column contains only one core from each group. The core provided with the relevant line 8 α lies in the series to which the amplifier 8 is assigned. Output lines 10 from an evaluation unit 11 are also pulled through the coil cores 9 to earth in such a way that the first of these lines 10 through the first of the five coil cores 9 in each individual group, the next line through the next of the coil cores in of each group and the last line is pulled through the last coil core. The five columns thus result from the coil cores 9. One of the lines 12 extending from earth is also drawn individually through each of the coil cores 9. The lines 12 are then brought together in the corresponding groups of five lines each and are each connected to an amplifier 13, from which they lead to eighteen output lines CGI to CG 18.

The cores 6 and 9 are operated in such a way that a set in the working state Coil core is reset by a reading pulse and thereby in an induction loop that the Output line forms through the coil core, generates a pulse. On the other hand, a reading pulse acts does not insert a coil core that has remained in the idle state; it just becomes an extremely small pulse output which is easily generated by a suitable biased diode limiter in the output line can be suppressed.

The unit in 'Fig. 3 is operated by two inputs a and b which originate from other parts of the computing device (not shown) and to digit memories 16 and 17 via gates G16 and G17, respectively

■ 5 created: are. There are three more digit memories 18, 19 and 20 available. The outputs from the digit memories 16 to 20 are applied in parallel to the gates G 6 to G10 and G11 to G15 in the manner shown. The outputs from the gate groups G6 to GIO and GIl to G15 are each connected to a collecting line. The two bus lines lead ■ to the two »suppression inputs« α and b of a logic switching unit LU. This logic switching unit here has the structure shown in FIG. 1b. The output from the unit Lt / is fed in parallel to the memories 16 to 20 via one of the gates G1 to G 5. .

Each of the gates G1 to G18 has the threshold value "2" and, in addition to the above-mentioned inputs, receives a further input from one of the groups of five magnetic coil cores each in FIG. 2. Each of the gates G1 to G18 is connected to that group which has the same reference numerals, the outputs of these groups being combined to form eighteen individual lines CG 1 to CG 18 in the above-mentioned manner.

It can be shown to be sixteen in all different logical links of two binary or Boolean variables can be carried out.

This combination contains all the links that are possible. Furthermore, it can be shown that each of these logical links can be carried out with the device described by a series of operations of the one logical switching unit LU .

It can therefore be any logical link as a series of patterns or combinations of operating states the gates G1 to G18 can be determined. the Combinations of the respective operating states of the gates that indicate a specific operation are intended hereinafter referred to as "gate combinations" for short. The series of gate combinations are unambiguous with regard to every logical connection, although the series, of course, have a particular connection determine, can include identical combinations.

For the operation of the apparatus shown in FIGS. 2 and 3, each series of the gate combinations is in Groups of five gate combinations each divided. This division is only used to simplify the Operation of the solenoid cores, as explained below. For any link you want is a special connecting line 5 from the program unit 1 from the one formed by the coil cores 6 Pattern memory provided. If there is an instruction for a special link in the Line 2 appears, which here can take the form of a series of binary signals, becomes the appropriate connection line 5 fed by the program unit 1. The program unit 1 can be of any suitable construction have, for example, in the case of a binary input, it can consist of a decryption branch.

When one of the connecting lines 5 is fed

and at the same time the first output from the register 4 runs into the first column of the coil cores 6 , a pulse appears in those row lines 7a through whose cores 6 arranged in the first column the line 5 is pulled, which via the amplifier 8 in question into the Line 8 α arrives and there sets the associated coil core 9 in the working state. In this way, according to the

Claims (2)

special required link, which is determined by the routing of the relevant line 5 ', from the first column of cores 6 fed by the first stage of register 4 a combination of states of the coil cores 9, which in the first column of cores 9 of the first of the above-mentioned gate combinations in the required: series that brings the logical switching unit LU to execute the required link. The combination of the states of the cores 9 in the next column corresponds to the next - gate combination and in the last column; the fifth combination of gates in the series. After the five columns of the coil cores 9 have been set in this way in the working state corresponding to the five first gate combinations of a series of gate combinations, the first output from the register 4 is applied to the evaluation unit. This unit 11 can contain a pulse shaper 14 in series with four individual delay units 15, which are arranged so that an evaluation pulse is first applied to all coil cores 9 in the first column and then in sequence to all coil cores 9 in the next column. As soon as an evaluation pulse is applied to the first column through which the first line from the unit 11 has passed, output pulses appear via the amplifiers 13 exclusively in the output lines of those groups whose coil cores 9 in the first column are in the working state. As a result, the gates G1 to G18 are selectively set to the working state for performing the first operation of the logic switching unit LU. In a similar way, the gates G1 to G18 are set to the state of the second gate combination as soon as an evaluation pulse appears in the second column through which a line has been drawn from the unit 11. As soon as the operations corresponding to the first five gate combinations have been completely carried out, the next five combinations are transmitted in an analogous manner from the second column of the coil cores 6 to the coil cores 9 through an output from the second stage of the register 4. They are then processed in sequence by the unit 11 in accordance with the second output of the register 4 in the manner described above. The next step is then carried out in the same way until the required link has finally been carried out. The final answer is given through gate G18. In one embodiment of the device, the digit rate for the signals fed into the memories 16 and 17 can be of the order of 100 kHz. The operating speed of the programmer 1 can be about 5 MHz, while the release speed of the gate combinations can be about 1 MHz. Since the groups of five coil cores 9 are used in sequence and switched on in common output lines, the gates G1 to G18 and, accordingly, the logic switching unit LU can operate at about 5 MHz. Compared to the digit feed rate of 100 kHz, this means that a maximum of fifty operations can be carried out by the logic switching unit for each required link in the device. The ratio of 5: 1 between the working speed of the programmer and the release speed of the sink cores of groups CGX to CG 18 allows a relatively low working speed of the coil cores. These numerical ratios are of course mainly given for better clarity and can be changed and adapted to special cases. The first operation of the logic switching unit is related to the original inputs α and b in the memories 16 and 17 and can be one of the following operations: (i) G6, GIl open; G7, G12 closed; Entry in LU: a, a; Output from LU: ~ ev ~ d = ~ a - not α. (ii) G7, G12 open; G6, GIl closed; Entry in LU: b, b; Exit from LU: ~ & v ~ & = ~ ö = not b. (iii) G6, G12 open; G7, GIl closed or G7, GIl open; G6, G12 closed; Entry in LU: a, b or b, a; Exit from LU: ~ av ~ 5 or ~ & v ~ ö. Both expressions are identical to: ~ (a & b) = not (a and b). In each of these operations, all gates are closed except for the one that is in the input line to the memory in which the output from the logical unit LU is to be retained. The memories are designed in such a way that they retain the information introduced into them until a further input value is introduced. A memory can thus be used more than once for any function if the information stored in it is not required again in a further work step of the function in question. The number of memories is not limited to five, it is only limited by the maximum number of operations necessary for any desired link. In the following operations the obtained values a, b, ~ <z, ~ £ and ~ (α & ί>) can be combined with one another in such a way that every possible link can be made. The intermediate results are stored and, as soon as they are required, are reintroduced into an operational stage by the function programmer using suitable gate combinations. Optionally, the sub-program unit consisting of a magnetic core matrix can also be replaced by a magnetic tape or magnetic drum memory or a point light scanning device with perforated cards and photocells. The main advantage of a computing unit in accordance with the present invention is that it provides the greatest degree of flexibility and adaptability. PATKNTaNSPKOOHE: 1. Logistic processing unit with a logical switching element that eliminates the incompatibility between expresses a larger number of binary code signals, characterized in that the input signals and those from the logic switching element originating signals are stored in a larger number of binary signal memories and via with Gated conduction paths are selectively channeled from the memories through the logic switching element are selected, with a selection circuit for sequential opening and closing Combinations of these routes are provided so that different logical operations are carried out with the input signals can. 2. Computing unit according to claim 1, characterized in that the selection circuit groups of magnetic cores, each of which is associated with one of the gates and which are selectively in one predefined patterns are set in the working state, and that those within the group in the Working state set cores selectively by clock devices to open the assigned Gatters are operated. Considered publications:
"Automatic Digital Computers", Methuen & Co., London, 1956, particularly pp. 210 to 256; "Electronic Rundschau", vol. 9, no. 10, p. 349 to 353. 1 sheet of drawings