DE1184125B - Two-stage arithmetic unit - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY

GERMAN

PATENT OFFICE

EDITORIAL

Boarding school KL: G 06 f

German class: 42 m -14

Number: 1184125

File number: T21135lXc / 42m

Filing date: November 17, 1961

Opening day: December 23, 1964

The invention relates to an arithmetic and logic unit in which two or more binary-coded input variables using one of a plurality of functions available through control lines selected switching function, a binary-coded result variable is formed in two switching stages will.

It is known that the effort required to implement a sound function is often reduced if you increase the number of stages connected in series. For example there is Parallel adders that separate sum and carry for each binary digit in a first stage determine and then reduce the carryover in further stages. The transfer in particular is conditional in one single-stage adder a complicated and expensive logical network, since it consists of all binary digits depends on both summands.

The multistage addition, on the other hand, has the major disadvantage of the longer duration of the operation. if two cycle times are necessary to determine the result of the link, then in known Arithmetic units two operations follow each other only at a distance of two cycle times.

Such known adding units form auxiliary quantities from only a few adjacent ones in the first stage Binary digits of the operands, especially conjunction and disjunction from only one binary digit each each operand. The auxiliary variables are usually chosen in such a way that the desired addition works through only results in a suitable combination of these auxiliary variables. The system of auxiliary quantities then provides a complete Generating system for addition. In general, there is a different one for each addition code Generating system with minimal overall effort ".

This is where the invention comes in. It faces a double task without much greater effort to expand the adding unit to an arithmetic unit with several selectable functions and at the same time to improve the unfavorable time balance of known multi-stage adding units.

The invention proposes an arithmetic and logic unit in which the linking result after one with the help of control lines in two stages selectable arithmetic logic unit function is formed, its time balance, however, essentially the characteristics a single-stage arithmetic unit. This is achieved by connecting the control lines only to the Influence the function of the second switching stage, while in the first switching stage stereotypical auxiliary variables are generated, from which all available functions of the second switching stage can be derived.

Two-stage arithmetic unit

Applicant: * · '

Telefunken patent collecting company

m. b. H., Ulm / Danube, Elisabethenstr. 3

Named as inventor:

Dipl.-Math. Dr. rer. nat. Günter Hotz,
Saarbrücken

The auxiliary quantities must therefore describe an algebra.

ben, which includes all selectable functions.

According to a further invention, the auxiliary variables are each dependent on a subgroup of binary parts Each input variable is formed, with a subgroup preferably consisting of one or two binary digits consists. Such an arithmetic unit structure allows operand groups to be mutually exclusive with only one cycle time Follow a distance, since there is the possibility of program control at every cycle time. Only in the further processing of Yorf interim results

hat is actually the cycle lasting two bars to bring through the arithmetic unit.

The most common case of further processing of interim results is the carryover in the series addition. To the disadvantage of the two To avoid long cycle times - also in this case, is proposed according to a further invention, the second switching stage so "to train that the Carryover is only taken into account in this Sctialtsruf needs to be. '.'. '"'

In the following, the invention is based on the

F i g. 1 to 5 explained in more detail, of which. ".

Fig. 1 and ^: 2 show an example of an egg housing

Arithmetic unit show, ": '' ■ ⁵ "" ^{: r} ;

3 and 4 show an explanatory function table this embodiment

Fig. 5 indicates a further AusfrÄrungsbeispiel. The first embodiment relates to a decimal Serial calculator, whereby the individual binary characters that are used to represent the decimal digits are necessary (tetrad), fed in parallel to your arithmetic unit will. The multitude of possible operations have become two to illustrate the invention Operations selected, which are only to be regarded as an example: The binary addition and the addition two decimal numbers in the so-called 3-excess code. '

In 'Fig. 1, two asset registers are through

symbolic representation ^ ffig = ypn four flip-flops each

409 759/314

given. A first operand register X consists of the register elements AJr ₁ , Rx ₂ , Rx ₃ , Rx _f ; the second operand register Y consists of the register elements Ry ₁ , Ry ₂ , Ry ₃ , Ry ₄ . Index 1 always refers to the most significant binary digit. The flip-flops each have a normal and a Kömplernent output, which are designated with x _h y, - and X ₁ , y _t . According to the invention, these outputs are linked to one another via a logical, passive network in a first switching stage, in which no control line is yet involved. According to a further invention, this link is divided into two networks 1 and 2, of which the network 1 only links the two higher-order digits of both operand registers, while the second network 2 links the other two digits of the operand registers.

Among the numerous possibilities for the formation of the auxiliary variables, preference is given to those which result in an overall switching mechanism that is as simple as possible. In any case, the auxiliary variables must describe an algebra from which the desired result functions can be formed. It will be explained later on the basis of further figures that the selected auxiliary functions have these properties. Suffice it to say here that six auxiliary functions A ₁ '... A ₈ ' or g / ... g ₆ ' after an in _; F i g. 1 function represented in algebraic notation. These auxiliary variables are then temporarily stored in 12Re $ sterelemerrten, which are marked with Rg ₁ . ..Rg _a and Rh ₁ - ^ Rh _{6 are} designated; their outputs act on a logic network 3 of the second switching stage, which is shown in FIG. In this network, the mentioned auxiliary variables are linked to one another as a function of control lines b and Έ, the carryover from a previous addition via lines r and T being also taken into account, as already mentioned. In this network, the result variable, whose individual binary digits /, Z ₂ , z /, Z _{4 are} named, and in a result register consisting of the register elements Rz ₁ . *. ₄ discontinued. The logical network 3 also generates a carry, which is stored in the register element Rz _{T for} a cycle time and then offered to the network again.

All mentioned register elements are synchronized by a mandatory clock, the puts the elements in such a binary position that corresponds to the potential of the input line.

To justify the in Figs. 1 and 2 in the logic networks 1, 2 and 3 selected switching functions must go into circuit theory the basics of which can be found, for example, in P h i s t e r, »Logical Design of Digital Computers«, London, 1958.

F i g. 3 shows a function table which consists of sixteen rows and sixteen columns corresponding to the sixteen possible combinations of four binary digits. These possible combinations are shown in the order of a binary counter on the left and top edge. On the right and lower edge two assignments used in the embodiment are entered in desimal notation: The numbers 0 to 15 are provided in accordance with a binary adder and the numbers 0 to 9 in accordance with a decimal adder in 3-excess code. Four rows and four columns each of the thus spanned quadrai ^ eirid? U _: an eirfbait summarized by thicker lines, which have the same description by the first two binary digits of the operands. ι When choosing auxiliary variables * strtäit pian vor & l hkft ^; #ne AT ^ dbra zu teschreibef ^ jiie. ; includes only the desired output functions. For example, an algebra that is invariant to interchanging the operands is sufficient for the requirements of an adder. Another property of additions is that a whole line is occupied in each case parallel to the diagonal from bottom left to top right in the drawn square, since it is irrelevant for the output quantity whether, for example, the number 9 from 4 + 5, 3 + 6, 2 + 7 or 1 + 8 was created. For the first binary digit of the register, the squares that are to receive a ONE in the binary addition are crossed in FIG. 3. The cross field is limited by the additional conditions that the carry provides. If, for example, the combination of the binary coded 8 with the binary coded 7, i.e. the binary coded 15 · is the last number in which there should still be a ONE in the first position, this combination may only lead to a ONE if there is no additional carry pending (r). On the other hand, a ONE is already used in the first digit of the result if the binary number 4 is added to the number 3 and there is also a carry (r).

From this function table you can see at a glance that the auxiliary functions also advantageously describe fields that are limited parallel to the diagonal. According to the division of the first switching stage, two networks are provided which link the places of higher or lower significance. Correspondingly, there are subdivisions of the 16 × 16 fields into sixteen large fields, which like-; which, as described, are divided into sixteen individual fields. The large fields are described by the A-Fu actions, the individual fields within the large fields by the g-functions. The function A _1, for example, comprises the upper left large field, the function A ₂ the three upper left corner fields, -die

Function h _a six upper left corner squares, the function A _4, the six lower right corner squares, - the Fuaktion A _s the three lower-right corner squares · uad the function A _8, the lower right corner square. The same distribution applies to the functions S ₁ . >. g _e and die

Description of the sixteen fields within the large fields. This distribution is indicated in FIG. 4. To describe a »diagonal line- the auxiliary functions are combined accordingly. Within a large field, for example, the main diagonal is clearly identified _{by J 3} -J _4. The diagonal from the second uppermost square to the uppermost field of the second column within & aes large field is correspondingly described by g ₂ -J ₁ . With the help of two g-functions, each group of fields parallel to the diagonal can be selected. The same applies to the selection of a large field group in the overall function table in FIG. 3 and the Α functions. The functions for the description of these obliquely delimited surfaces are explicitly given in FIG. 1. They form auxiliary functions according to the invention, but not the only possible number which are most favorable in all cases. For codes or operations that are subject to any other law

Γ 184

<r

speed than the described symmetry is subject it makes sense to choose other auxiliary functions that take this law into account and so on lead to even simpler circuits. One such further system of auxiliary functions will be added later. Hand of fig. 5 will be explained.

The function entered in the function table (FIG. 3) for the first digit Z _{1 of} the binary ■ - (&===; 1) addition results will now be considered in more detail. The table shows the switching function of the second switching stage (first binary digit, b = 1) in disjunctive normal form. The main diagonal, which should be part of the function under condition 7 , is described by g ₃ · g ₄ · Έ ₃ · Tz ₄ , since these fields within a large field are outside the areas g ₃ and g ₄ and the large fields concerned are outside the areas h ₃ and / i ₄ . The condition f ₃ can be omitted, since the fields recorded in this way have x-signs and belong to the function anyway. In Fig. 2 the corresponding term would have to be called bTg _i 7i ₃ 7i _i ; However, since the same diagonal is also used in the function table for the first binary digit for non-binary addition (b - 0), condition b does not apply. So one finds £ ₄ 7ζ ₃ 7ϊ ₄ 7 ·. Now the fields that are subject to the condition r (carry) follow: They are again on a large field diagonal, this time the x-fields on the lower side, so that the condition f ₄ does not apply. Since only two large fields at the top left (without the corner field) and the three corner fields at the bottom left can be combined individually _{, the term for the r fields is Tg 3} Tz ₁ Tz _{2 + rg 3} / z ₅ . The description of the x-fields is found in the same way:

r u

One proceeds similarly with the non-binary addition and with the other binary digits: One carries the desired function in a function table and describes it using the auxiliary functions. For the The function table can also be used to select suitable auxiliary functions, since the latter is the Shows symmetry properties of the function and the group behavior of field combinations. Auxiliary functions which themselves describe or remove such field combinations are advantageous from which such field combinations can easily be derived. Next one chooses auxiliary functions that can be easily defined using the input variables; preferably they are made up of one or two binary digits of the input variables are formed.

Finally, another exemplary system of auxiliary variables is presented, which is also possesses the properties mentioned and could take the place of the system explained. It used only the known functions of conjunction (= intersection) and disjunction. The auxiliary functions are therefore:

άζ = x ₂ + y ₂ ;

dl = * ₄ + y ₄ .

60

65 These auxiliary functions "are also symmetrical, ie inväriätfü 'against ¹ Vferta ^ ctiuiig ■ the' input variables, but they have ^one ..nur füridie'iHaupitdiagonale (within the Großfddes like., In, delta. Total. Blackboard) a einheitlicheJ ^ eid ^ e ^ jceJbunS · Ia * Fig. 5 the fields of a size are plotted, in which the description by the auxiliary functions g ₃ , k ₃ , g ₄ , ^ is written. The upper left corner field, for example, is uniquely determined _{by 3 3} * 3 _4. The same applies, of course, to the distinction between the large fields and to the auxiliary functions ^ ₁ , k _v £ ₂ and k ₂ .

With this system, in addition to the additions mentioned, logical operations such as mixing or intersection can also be carried out in an extremely simple manner, in that the second switching stage, for example, switches through the k or ^ variables.

On the basis of this detailed description of the mathematical-logical relationship, a Method for determining favorable auxiliary functions for a given combination of operations. The technical implementation of the auxiliary functions as well as the functions of the second switching stage happens in a known manner by diode logic or magnetic core logic.

In addition to the examples shown, the invention therefore also includes arithmetic units in others Circuit technology and with functions other than the additions modulo 10 and modulo 16, in particular with all legal operations (e.g. Intersection).

Claims (4)

Patent claims: 1.Two-stage arithmetic unit, in which a binary-coded result variable is formed from two or more binary-coded input variables in two successive switching stages, and in which control lines are present through which one of several available arithmetic unit functions is selected in each case, characterized in that the control lines ( b, Έ) only affect the functions of the second switching stage (Fig. 2), while stereotypical auxiliary variables (g _b hi) are generated in the first switching stage, from which all available functions of the second switching stage can be derived. 2. Arithmetic unit according to claim 1, characterized in that each auxiliary variable is only dependent is formed by a subgroup of binary digits of each input variable, with a subgroup preferably consists of one or two binary digits. 3. arithmetic unit according to claim 2, characterized in that that to generate switching functions with certain symmetry properties (e.g. invariance of the result variable against interchanging the input variables) also the switching functions the first switching stage have these symmetry properties (e.g. conjunction in places, Disjunction, equivalence or the like). 4. Arithmetic unit according to claim 3, which, inter alia, the addition of two binary coded input digits able to perform, characterized in that a carry over from a previous Addition only becomes effective in the second switching stage.