FR1338794A - Two-stage computing unit - Google Patents
Two-stage computing unitInfo
- Publication number
- FR1338794A FR1338794A FR914867A FR914867A FR1338794A FR 1338794 A FR1338794 A FR 1338794A FR 914867 A FR914867 A FR 914867A FR 914867 A FR914867 A FR 914867A FR 1338794 A FR1338794 A FR 1338794A
- Authority
- FR
- France
- Prior art keywords
- computing unit
- stage computing
- stage
- unit
- computing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
- G06F7/495—Adding; Subtracting in digit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/491—Indexing scheme relating to groups G06F7/491 - G06F7/4917
- G06F2207/4919—Using excess-3 code, i.e. natural BCD + offset of 3, rendering the code symmetrical within the series of 16 possible 4 bit values
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR914867A FR1338794A (en) | 1961-11-17 | 1962-11-09 | Two-stage computing unit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DET21135A DE1184125B (en) | 1961-11-17 | 1961-11-17 | Two-stage arithmetic unit |
FR914867A FR1338794A (en) | 1961-11-17 | 1962-11-09 | Two-stage computing unit |
Publications (1)
Publication Number | Publication Date |
---|---|
FR1338794A true FR1338794A (en) | 1963-09-27 |
Family
ID=25999558
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR914867A Expired FR1338794A (en) | 1961-11-17 | 1962-11-09 | Two-stage computing unit |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR1338794A (en) |
-
1962
- 1962-11-09 FR FR914867A patent/FR1338794A/en not_active Expired
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