DE1499233C3 - Combination calculator - Google Patents

Description

The invention relates to a combination computer system comprising a universal computer and a digital one Differential analyzer (DDA), whereby the universal computer has a multiple memory, an arithmetic unit with several registers and a control unit and the differential analyzer a y-register, an λ-register, an overflow memory and an initial condition memory.

A general purpose computer is capable of performing most arithmetic functions. A universal computer however, it takes an excessive amount of time for many operations because it increases the Adaptability is built up from basic functional units. For example, an integration provides a slow process on a general-purpose computer.

Please refer to the article "A Digital Computer for 'Scientific Applications" by CF. West in the Proc. IRE, December 1948, pp. 1452-1460.

On the other hand, integration with the low cost of a digital differential analyzer, i. H. a computer specially designed for integration purposes, carried out relatively quickly. A However, DDA is relatively limited in terms of the functions it allows it to perform.

Please refer to the German Auslegeschriften 1 038 797, 1 120 781, 1 119 013 and 1 119 014.

U.S. Patent 3,039,688 shows that it is useful to use digital differential analyzers (DDA) to work with variable word length to short processing times and a To achieve savings in storage space.

It therefore seems advantageous to combine a general purpose computer and a DDA into a single combination computer system summarize in which both complement each other. The advantages of such Plant have long been known. The universal computer takes on general problems and takes care of overall control, while DDA processes integration problems quickly. It is so far however failed to develop combination plants that work satisfactorily, mainly as a result their size, complexity, slow working speed and lack of communication between and within the units (see also "Electronic Computing System, 5" (1963), No. 6, Pp. 262 to 269, especially page 269 "Future tendencies").

In particular, the large number of individual parts led to both increased space requirements and increased susceptibility to failure. The coordination of the two types of systems is also problematic, and it was So far it has not been possible to optimally utilize the advantages of both types of device.

Particular problems arose from the fact that general purpose computers and digital differential analyzers were developed independently of each other and only later on their mutual assignment took place. This made it particularly difficult to exchange information quickly and effectively between Universal computer and DDA, in particular, every single step of the DDA usually had to go through the Universal computer can be controlled. This results in a relatively slow working speed, the is very disadvantageous, for example, in navigation systems, since these allow rapid control based on input Request data.

It is therefore the object of the invention to provide a combination computing system to create, in which the exchange of information between general purpose computer and differential analyzer takes place in such a way that which the universal computer and the differential

3 4

analyzer own advantages, namely high adaptability can be fully exploited if the communication

ability or high integration speed, cation with the Z-tracks at the appropriate time without

takes place with the compilation of the combination delay,

computer system are retained as far as possible. A particularly favorable collaboration between

According to the invention, the object is achieved in that the universal computer and DDA result from the fact that a sequence control register is provided which determines the operating mode of the differential analyzer in another embodiment of the invention and which serves as an input channel for the y register (FIG. 3) a read flip-flop (FDFOl) is provided during the operation of the differential, via which the tialanalysators non-erasable program memory the universal computer can correct 7 numbers without disturbing the differential analyzer as well as the universal 10 DDA operation,
The system has a universal computer with a memory of the differential analyzer which can be triggered control storage unit, a control unit and arithmetic commands for carrying out the integration processes. The control unit allows the normal arithmetic functions of a universal computer in the differential analyzer of the universal computer and supplies errors for the transmission of the content of an initial 15 in addition a pre-control of the DDA. The condition memory of the differential analyzer in the DDA has a program unit and a control unit 7 registers and the deletion of memories and for related components, for example a register of the differential analyzer can be triggered and a track for initial conditions, a 7 register, a register that can be used with memory commands from the general-purpose computer to the Λ-register and two Z-lines, all of which are used for data transfer from and to arithmetic registers also 20 Implementation of a programmed integration of memories and registers of the differential analyzer,
are addressable. The universal computer part is designed so that two

The processing speed can thereby be independent communication methods with the DDA be increased that, according to a development, are given to the interaction of the units Invention of the differential analyzer with variable 25 to further increase. A number of by the university word length works that the universal computer and the universal computer controlled test and correction radio differential analyzer A common storage area was developed in order to permanently store the dual arrangement drum and to make better use of the differential. For example, you can use integer analyzer has an adder, which of these corrections by individual integrators of the DDA Commands can be controlled in such a way that 30 are carried out during a. Also the correction or the Drum rotation performed numerous additions initial setting of 7 numbers for each other in can be. Related integrators of the DDA at a

This has the advantage that no word length com-simple iteration is possible.

promises have to be made and therefore every

Device can work with optimal efficiency. 35 sponsors of the DDA are of particular importance,

By stringing together the words with, because they not only connect the digital integration system in this way,

for example only a single gap will allow turning due to restrictions

Saving storage space, i.e. reducing the size of the system, practically no bit is wasted in the device,

and the computation speed is increased because there are waiting but also word length compromises between the

Exclude times due to large gaps 40 universal computers and the DDA. the

be avoided. The common storage drum can store location and the length of each integrator can

it also simplifies mutual cooperation and is fully determined by the programmer who runs the

increases the communication speed. Able to start and stop integrators,

Since all operations of the DDA on the memory increments select as desired as well as numerous drum are permanently stored, there are no facilities 45 can perform other functions. The program required to write commands on the drum can provide as many bit characters as for practice, which makes the system easier and its use requires an operation, with between the for example in aircraft. Integrators do not leave any useless space free.

By the fact that during a Trcmmelumlauf in this way each integrator can to the respective

Numerous additions are carried out; n can initiate 50 neighbors without practically any between

full circuits are avoided for each addition, leaving useless space free. Any integrator

and the iteration speed of the DDA can still be the length desired by the programmer,

increased. So that such a compact arrangement is used

In order to increase the accuracy and can become smaller, is within the digital integration increments To get on with iteration, 55 anlage will be a very adaptable system of the Z-level Another inexpensive further training course of training is required. At the before of the differential analyzer all data and lying integration system is one for the Z-lines Commands ternary encrypted. Two short drum loops are provided. There are four reading tracks necessary: one for storing the amount stations available, which are at a distance above the (1 or 0), the others are arranged to store the pre-60 Z-wire trace of the drum. A sign (+ or -). Temporary storage flip-flop is also provided,

According to a further embodiment of the invention to enable selective Z-line storage assign the Z tracks to the magnetic drum, thereby enhancing the communication skills of the (Result traces) several reading heads and are arranged to be increased. It is also through two decrease flip-flops as intermediate storage before- 65 suitable application of the memory flip-flops, the seen. This is particularly beneficial with a DDA circular loop and multiple reading positions with integrators of variable length, because the latter is possible, a Z-line storage on each visible Time saving and use of memory space only pre-set the desired bit storage location of the Z-lines.

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to take. A choice can also be made at each bit as well as a control unit. The control unit works in

Location to be executed. As a result, reliance on the commands can be linked

every integrator practical the calculation registers and certain other system parts with every other integrator

table without restrictions. such that the data is in a prescribed manner

The DDA can be processed into 5 due to the possibility of it.

program and, as a result, integrators with A digital differential analyzer is suitable for

variable length to be used, as well as due to the integration, for example according to a process,

flexible communication scheme up to 90% of that described in US Pat. No. 3,035,768

register space available for integration is off. This essentially becomes a T-number in one

to use. For a device working with a fixed length, io y register changed by delta F increments, one

only 60% of the integrator space can be used on average. Λ-number in a / ^ register around the F-number in a

The advantages of this optimization are readily changed in the Delta-Z growth rate and in the Ä register

. On the hand. . . Overflow increment (Delta-Z increments) the result

An extremely large track length of the registers of the nis Z of integration is formed. Each special Inte DDA makes it possible that that is variable length 15 integrator, usually virtually assigns other integrators been working integrators as desired to edit large integration problems can be programmed and Wortlängenein- The integration capability of a DDA particularly beautiful ^r änkungen be avoided . Semi-permanent useful when a navigation system ^Spe: cheranordnungen is assigned within the general-purpose computer, for example, reduce an inertial and the DDA the weight of the plant and 20 navigation system with guide platform Berechführen to a · reduction of their size and voltage of distances, speeds and Posi-Kom ^ licity. The improved internal communi- cations.

cation, which is caused by increased storage and consumption. 1 the DDA 30 works

properties is made possible, the Er- supports the control of the universal computer 10. The

increase in machine speed. Overall control carried out by the UR 10 in particular

Its use is a storage facility between enables the DDA 30 to work correctly.

the DDA and the universal computer, which yaw with both, to improve and supplement, creating a

Devices can work together. The storage is suitable «considerably more powerful facility created

is particularly useful as a buffer for the DDA when it is used in a normal digital integration

and enables short-term changes to be made easily 3 °. For example, the UR 10

and run without delay. Two initial conditions according to the present arrangement

Provide logical transmission command units in universal settings for the DDA 30, discrete variables

calculators allow automatic operations for calculating and for correcting the DDA 30

use such a combination system particularly well and others with navigation or others

are. 35 associated operations

The invention in the following description will address problems such as fire control, etc.

on the basis of exemplary embodiments in connection with the universal computer. 10 also ensures the overall

explained with the drawings. It shows control of the plant. It essentially consists of

F i g. 1 is a block diagram of the system, a storage unit 11, an arithmetic unit 12, a

F i g. 2 shows a block diagram to explain the 40 control unit 13 and an input-output unit 14. Operations in carrying out an integration The storage unit 11 is in a permanent storage means a digital integration system, part and a buffer part divided. Of the

F i g. 3 a functional diagram of the digital Inte- permanent memory part can expediently for

grating system of the combination computer system, recording of constants that are used in the intended

F i g. 4a and 4b juxtaposed, partially in 45 illustrated operations of the universal computer 10 ge block diagram, partly in schematic need, during the modifiable storage position, the combination computing system, part of the storage of program instructions, the

Fig. 5 is a diagram of the sequence of commands for storage of various input variables, the

rend of typical DDA operations, storage of partial solutions and implementation

F i g. 6 a functional diagram of the universal ^ 5 ° further buffer functions serve ^ ann.

computer part of the system, the combination computer system uses a single

F i g. 7 is a diagram of the word structure of the unique magnetic drum and associated Ic ische and

universal computer part according to the invention, gate circuits for forming the memory of

F i g. Figure 8 is a diagram of the timing lanes of both the wraparound register and timing lanes

Universal computer part, 55 for the UR 10 as well as for the DDA 30. The

F i g. 9 a diagram showing connections when the machine works in series operation with binary numbers,

Works of the accumulator of the general-purpose computer part although a ternary representation for part of the

and internal communication of the DDA 30 is used.

FIG. 10 is a diagram which shows how one arithmetic unit 12 has three circulating arithmetic registers

of the logical equations can be mechanized. 60 A, M and B on the magnetic drum. Register A

The system according to FIG. 1 has a universal is an accumulator with left and right shift calculator 10 and a digital differential analyzer exercise, the register M an auxiliary register with left-30. A general purpose computer (UR) solves mathematical and right shift and register B and logical problems of a general nature, while an auxiliary register, which only allows circular storage. Differential analyzer specially designed for performing ⁶ 5 The control unit 13 comprises a number of flip integrations. Flop control registers, timing tracks on the drum

A UR has a number of arithmetic registers, a mel and a logic control matrix for implementation

Storage unit for storing data and commands of the various functions represented by the equation

genes and commands are determined by means of which the UR10 is operated. The input and output communications between the UR10 and various External facilities are carried out via the input-output plant 14. The general control and information transfer of input and output signals within the system between the UR 10 and the digital integration system 30 takes place immediately and via a special storage unit 24, as described in detail in the specific description which follows is explained.

The UR10 can do essentially the normal Functions of a UR and also perform a number of functions that are particularly useful for the Control of the DDA 30 are suitable. For example, the UR10 is equipped with control circuits for the initial setting, the deletion, the data circulation and the action on various registers of the DDA 30 as well as equipped to start and stop the DDA. It also has special logical functions, soft the Do not directly affect DDA 30, but are useful as its operations are expanded should.

The DDA 30 has a program memory 31 with five program memory tracks on the magnetic drum, an arithmetic unit 32 with an F register, a / {register and two Z-line memory tracks Control unit 33, an input-output unit 34 and an initial conditions track 35 for storage of y-numbers for the initial setting of the integrators of the F-register.

The overall control of the DDA 30 takes place by means of the program memory 31, which is dependent on the program of the five tracks works. These tracks contain the entire control program for starting and stopping the integrators to select the incremental signals and to work in servo mode. ■ The overall control takes place by means of these tracks and by means of the universal computer 10. Both influence the control unit 33 to control the logical operations. The program unit 31 controls also the inclusion of incremental information via the input-output work 34 from locations outside the plant. The control unit 33 comprises circuits for executing the logical equations (the matrix) and a variety of flip-flop registers for control operations.

Controlled by the UR 10, the DDA 30 can operate in three operating modes. At the integration company the DDA 30 uses the arithmetic registers in the arithmetic unit 32 to carry out certain integrations, controlled by the program control unit 31 and the control unit 33. Be in servo mode Ternary information generated during the integration operation controlled by the program track control converted to the usual binary form for use outside the system. In circulation operation will information processed during an integration cycle circulated and without further Maintain processing so that the general purpose computer 10 can perform functions without that the information of the DDA 30 is destroyed, which may still be applicable.

An exception to the use of binary notation occurs within the system in the calculator 32 of the DDA 30, which uses a ternary representation for internal communication purposes.

The operations of the general purpose computer and the DDA 30 that are linked and each other can best be supported after a discussion of the peculiarities of the individual system components to understand. As a result, further discussion of the mapping made possible by the present invention is made possible Capabilities of the system are postponed until each of the two individual computing systems is explained in more detail.

The universal computer 10 supplies the digital differential analyzer 30 with integer values, and it can receive integer numbers linked to one another from the DDA 30 for computational purposes Groups of initial conditions for F-register integrators of the DDA 30, check and correct the values in the DDA 30 or, where necessary, update these values. the Internal communication within the DDA 30 also favors the ability of the two computer parts to to work with each other as well as independently of each other without the system parts having to block each other.

Structure of the universal computer part

The universal computer 10 of the system is shown schematically in FIG. 6 shown. The UR 10 includes a number of memory tracks (32 tracks in the described embodiment), which are individually one Read-only memory, a memory with changeable information content, circulating registers and input-output functions assigned. Certain tracks on the same storage drum are different Functions of the DDA are assigned, as described in detail below. As a clue for the performance of the general-purpose computer 10 it should be mentioned that in the special embodiment with 32 tracks on the single drum space in each track is for 128 words of which each comprises 25 binary bits. The word structure will be used in the following when discussing the operation of the Universal computer 10 explained.

The general purpose computer 10 functionally comprises four circulation registers. These registers are formed under the influence of the matrix circuit which links the various components. Of these registers, the ^ register, the M register and the 2? Register are used in the main arithmetic operations, while the F register is used in addressing. The ^ register is the accumulator, the main arithmetic register, in which essentially all arithmetic operations are carried out. This register works with left and right shift. The M register is an auxiliary arithmetic register which stores the multiplier during a multiplication instruction and a quotient during a division instruction. This register can be shifted to the right, and a shift to the left can also be carried out by time-division multiplexing of a logic flip-flop. The 5 register is an auxiliary arithmetic register which stores the multiple during the multiplication operation and the divisor during the division operation. This register cannot be shifted left or right. The V or sector address register is not an arithmetic register. It is not under program control, but receives every command read from the memory and lets it circulate. The V register stores the instruction for a bit-by-bit comparison of the sector address with the output of a sector address track which specifically designates the respective word sector of the track. the

509 634/13

The position designation supplied by the sector address track is accompanied by the command or the operant address compared, which is present in the F-register. If the two match, the corresponding one becomes Word position of the drum selected automatically. The K register can also be mechanical Operation can be changed to count intervals for functions that have a particular number of word times require, for example, right shift, multiplication, and division.

The sector address Γ track works in conjunction with a word interval track to provide base time and sequence control. As stated, the sector address track supplies information which designates the sector of the memory which is in each case under the read heads for word addressing. The sector address track also contains a constant in each word position which is used to indicate the number of word times required to perform the aforementioned counting operation during multiply or divide instructions. The constant is read into the sector address V register and incrementally decremented during the multiply or divide instructions.

On the other hand, the interval track provides basic information for the sequence of the various operations of the universal computer 10. The interval track delivers Signals for dividing each word sector into a number of intervals such that the meaning can be distinguished from certain bits of each word. The intervals are in the control the various logical operations used.

During each particular operation, general purpose computer 10 goes through four basic phases, controlled by two sequence control flip-flops FGUOL and FGU02, collectively referred to as sequence control (t /) registers. The phases for each operation are (1) search for the next instruction, (2) read the next instruction, (3) search for the operand specified in the instruction word, and (4) read the operand and perform the arithmetic operation.

The operations carried out by the general-purpose computer 10 are summarized in Table I below can if the logic circuit is constructed in the manner described.

Table I.

command

Place

Add up

Subtract

Delete - Add

Delete - Subtract

Add - replace

Subtract - replace

Multiply

Divide

Move A right

Move A left

Save Accumulator Contents] ⁱⁿ . ^the
Save Af register content [ ^a ? ^T f- Save, -Register contents J save

GibinsA / -Registerein] ^d " ^nInha ' ^tdes
Enter in, -ReU ß

binary code

54321
00001
00101
01001
01101
01011
01111
10001
10101
10,000
10100
00011
00110
00111

Hill
11101

Continuation of table 1

command

Swap the content of the Λ register and
, Register

Swap the contents of the ^ register and
M register

Sign test transmission

Compare transfer

Logical »and« transmission 1

Logical »and« transmission 2

Unconditional transfer

idle

input

output

Control of the DDA

Give initial values to the DDA.

Enter initial values and delete
the DDA

Delete R and Z

Start the DDA

y register for initial condition track

Circulate DDA

binary code

11001

11011
10011
10111
10110
10010
11110
OHIO
11010
01010
01000

Track address register
steering

55 The execution of each special command is under the control of the Command (I) register. The command register has five flip-flops that can store 32 individual commands in binary form. After every Instruction is given in Table I for the specific binary signal required to carry out a to initiate a certain command. It is important that with the commands »Save Accumulator Contents«, »Save Af register content«, »Save .B register content« as well as "Enter into the, register" also memory of the DDA, such as the initial condition track and y-register, can be addressed.

It should be noted that the delete-add and delete-subtract operations are mutually exclusive particularly suitable for numbers from the y-register of the digital integration system 30 for comparison and others Retrieve purposes that are directly related to correction and data renewal.

Controlling the digital differential analyzer

As can be seen even better from the following description of the DDA 30, the UR10 Trigger certain operations of the DDA 30 with a general command "Control the DDA". the the particular operation desired is indicated by the state of the track address (D) register of the UR.

Control the DDA
Enter the initial conditions into the DDA

When this command is executed, the contents of the initial condition track of the DDA 30 are written to the y-register read. The Λ register and the Z lines of the DDA 30 circulate. Execution this command is delayed until an original pulse is received. The operation lasts one revolution of the drum and is terminated when the following original pulse occurs. The Λ register, the, register and the M register of the UR 10 remain unchanged. After executing this command, the normal operation of the DDA resumed. The state of the D register for the instruction is in Table IX below.

Control the DDA
Enter initial conditions - clear the DDA

The execution of this command by the UR 10 causes the contents of the initial condition trace can be read into the 7 register of the DDA 30 and the i? register and the Z lines of the DDA 30 cleared to zero. This command requires one drum revolution and begins and ends at an original pulse. After executing this command, the normal Operation of DDA 30 resumed. The contents of the registers of the UR 10 remain unchanged. The status of the D register for the instruction is shown in Table IX below.

Control the DDA / delete R and Z.

The contents of the i? Register and the Z lines of the DDA 30 are cleared to zero. The Y register circulates and retains its information. The command requires one drum revolution and begins and ender with an original mark. The ^! Register, the JJ register and the M register of the UR 10 remain unchanged. The command results from the D register according to Table IX.

Steer the DDA / rotate the DDA

This command has the consequence that the DDA 30 works from an original pulse on in circulation mode. Information in the Z-lines loops in the 50-bit long loop so that most of the information is retained. Information in the Y and Λ registers and the initial condition track is circulated. The status of the D register is shown in Table IX. The command is normally used for test purposes.

Control the DDA / Start the DDA

Execution of this command causes signals which bring the DDA 30 out of circulation mode. Table IX gives the state of the D register for this instruction.

General description of the DDA 30

In order to understand the manner in which the DDA 30 is practically implemented it seems useful explain the methodological principles on which the application of a DDA is based.

Delta-Z output signals are generated by an integrator in accordance with the equation dZ = KYdX by using a so-called .R-number, which is assigned to the 7-number. Delta Y increments are selectively added to or subtracted from the 7 number, so that the F number changes in the amount of Delta Y. For each received delta signal, the Y number is correspondingly added to or subtracted from the λ number. In this way, the Y number is added to the i? Number in the measure delta X.

If necessary, the i? Number overflows (i.e. it exceeds the predetermined limit values; the extent to which such an overflow occurs is used as the initial measure Delta Z. the Operation is schematic in Fig. 2 shown.

The mathematical basis of the integration is z. B. in the essay "The Decimal Differential

Analyzer ”by Mendelssohn, Aero Engineering Review, February 1954.

In order to solve a problem with the digital integration system, its integrator sections must be among each other are connected and initial values must be determined for each of the sections. After this the mutual connections and the initial values are determined, the programming takes place and can the problem solving take place.

ίο It goes without saying that with a digital integration system a single integrator does not need to be present as a separate separate unit, but instead a stored Y "number, an associated stored λ number and a device can be provided, which brings the two variables together in order to facilitate the integration to execute. The apparatus may comprise means for converting selected delta-Z signals as delta-λ "- and Delta 7 inputs to use, means to the

ao y-number corresponding to each delta Γ input decrease or increase, means to the i? number corresponding to the y number and the delta X input increase or decrease, and means to generate delta-Z output signals according to the

generating overflows of the i? -number. Thus, a plurality of integrators can be provided by means for storing a plurality of pairs of Y and Λ numbers and by means for processing each of these pairs in turn, the apparatus for performing these operations being time division multiplexed to process each pair of Y and Ä numbers in turn. For this purpose, one or more magnetic tracks can be used, which store all Y and numbers, expediently a single track for all Y numbers and a further single track for all numbers.

The interconnections between the integrator sections are established through initial programming of the DDA in such a way that results (Delta-Z signals) from different integrator sections as Delta-A "and Delta-F signals for further integrator sections can be selected. The initial values of the various F-numbers will be entered by placing the digits representing these numbers in the spaces on the y-register track be introduced, which is selected for the various integrator sections. That special program for full integration (selected taking into account the explanations above) is incorporated into the DDA's program memory tracks. The program is chosen so that the mutual connections of the integrators and all necessary to carry out the operation Commands are received. A particularly detailed description of an integrator structure and the basis for this, including interconnection, can be found in the U.S. Patent 3,035,768.

F i g. 3 shows a functional block diagram of a particular embodiment.

The DDA 30 has a number of magnetic drum storage tracks, a plurality of flip-flop circuits, various amplifiers and magnetic heads and a logic switching matrix for performing the from special functions provided by the programmer. He is with an initial condition trace, one F register track, one Ä register track, two

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Size and sign Z line traces and five more functions of the relatively complicated DDA

Provided program tracks, which are all magnetic as sufficient.

storage tracks on a rotating drum The program tracks supply signals to the logical can. In the illustrated embodiment, switching matrix for exercising control over a become the program tracks of a »semi-permanent« 5 multitude of circuit arrangements. The program memory tracks Formed on the magnetic drum, control the generation of signals by the tracks while the other tracks are modifiable memory matrix to allow the DDA 30 to operate in integrated mode and in Include tracks from the drum. Let it work under a half-servo mode. It is remembered permanent track is primarily intended to mean a track that is the main control of these operations the logical arrangements through the program tracks for which no precautions have been taken Change the memory content during operation. he follows.

The five program tracks are arranged synchronously.The logic switching matrix of the DDA 30 accepts and can be operated, in series operation, so clock signals from the clock pulse generator, which also supplies 5 bits to the clock signals for the general-purpose computer 10, binary program information is available at each specific machine time . Up to 32 program instructions are available on 15 The Initial Condition Track in this way. Discussed embodiment comprises a circular These commands include commands for starting and mige magnetic track with 3200 bit positions, which corresponds to the number of stopping individual integrators, for starting and the bit positions for the Y and Λ tracks ending a servo - Operation designated Opera- are provided. In contrast to these tracks, tion, for selecting (decoding) information 20, is filled with information only half of the initial conditions in Z line positions, such as delta-JV and delta track, because the track only has 7-input signals for Reversal of sign, for entering the initial condition of the 7-register selection of external increment input signals and for supplying what only takes half of the track around other functions, all of which are further down on the drum. The beginning are explained. 25 condition track is a write head amplifier WDPOL

The program took up half the length and assigned a read head amplifier to RDP06

of the tracks and is provided twice in order to facilitate reading and writing with the aid of heads

To get the repetition speed, the double effect, the 1600 bits or half a track length effect.

th drum speed. Everyone lying to each other. The read head amplifier RDP06 delivers

A reading head is assigned to the gram track, which signals synchronously 3 ° one after the other while the drum is rotating

with the read heads of the other program tracks to a read head flip-flop FDP06. The transcription

is operated to an output signal for read amplifier WDPQl supplies signals to a flip-flop FDPQT,

stronger for the actuation of program track reading by means of the control matrix with the 7-register track

Get flip flops. The read and write heads can be connected to the initial conditions

of the system are to be entered taking into account the known 35 of the DDA 30.

Criteria selected and assigned to the tracks to be The selected initial conditions

according to the input supplied to these heads - originally controlled by an external circuit

Signals incremental ranges of the tracks from past through the universal computer 10, via the write head

Obtain correct magnetization and to under-amplifier WDPQl and the write flip-flop FDPOl

divorce. 4 ° introduced into the initial condition track. this

To enter a program in the program tracks, use the command »Save«, if you add a known device, the initial condition track can be addressed. When those become which each of the program track read heads provides initial conditions of the DDA 30 according to the write signals. For example, commands of the program control tracks can be introduced, signals for writing a so-called "Ferranti 45" which are supplied by external devices in certain positions of the initial pattern. Condition track stored initial 7-digits The use of external devices to write the program read out in series operation via the flip-flop FDP06 gives cause to be introduced by and into the 7-register track. The actual semi-permanent memory to speak of. The start control is carried out by means of the universal computer 10. Drive a program in the program tracks over 50. That is, the universal computer 10 commands a device to be introduced that is not a component of the "delete-enter initial conditions" command that the system itself represents, is particularly useful from i? -register track and the Z-line tracks to zero, if the system is to be transportable and deleted and that the contents of the initial total weight or total size, for example conditional track, are written in the 7-register track for Flight facilities, are to be reduced. 55 to be.

It should be emphasized that all operations when the command is present, the beginning of the DDA are programmed, both for the conditions of the y-register during a single start and stop of the integrators as well as for drum rotation.
Decryption functions. This feature enables both the Y and the Λ register of the DDA light, supported by the extreme track length, which 60 _s j _n dj _{n is structured as} follows. Each register in order to form space-saving integrators with variable takes up its own magnetic track using a length. single pair of read and write heads that

As explained above, a binary number system yields 1600 binary bits apart. In general

of the present device 32 possible individual known circulating registers read and write

Program instructions when five program tracks (five 65 heads on, their spacing for the bits only a few

Bit positions) can be queried synchronously and at the same time. fewer integrators is sufficient. Such an arrangement

In practice it has been shown that the number of openings with fixed programs form more fixed registers

available command encryptions for the radio length, which must be large enough to accommodate the largest

15 16

used F and /? numbers. If Z-lines are decrypted and shorter numbers are processed on the shift register, the unused flip-flops FDY ( S1 to FDY06 are transferred, lost together

The large head spacing enables the pro-y number in the F register of a following integrator programmer to start integrators as required and to hold them at 5. The ease with which one can shut down integrators with variable length in front of a single one and see these integrators between the integrator heads in the event of an overflow of the F register track, whereby only a negligible one can be added, avoids individual ones Circulation space loss occurs (in a special execution process for each addition and increases the iteration form a single distance bit). While at the known speed of the DDA 30 considerably,
th, fixed-length integrators As stated above, the sum of the F-number is

the unused in a certain register and the delta Γ increments are necessarily lost during the integration space, when operating with the number in the i? 'Signals can be connected to a specific speed with a wider integrator of 26 bits, 15 speed added. The register is left out by a single space to distinguish between the two register storage tracks, a sense amplifier integrator. RDAOl assigned read head, a read flip-flop On average it can be estimated that the present FDROi, a write head and a write system with integrators of variable length the flip-flop FDRQ7 assigned amplifier WDROl use well over 90% of the available register 20 formed. As in the case of the F-register, the space is permitted, compared to approximately 60% control of the signals to and from the flip-flops in integrators with a fixed word length. FDROi and FDR07 through the logic switching matrix.

Another advantage arises from the dense A schematic representation of the Λ register takes place Arrangement of the individual registers. Since it is lost in Fig. 3.

Space is practically avoided, the time 25 is saved. The addition of the F number and the jR number is saved, the logical full adder circuit normally required for this overflow with the aid of a carry flip-flop FDRQ6 and a space in machines with a fixed word length within the matrix. It is high, so that the operations are approximately two flip-flops FDRO1 and FDR03 which run one and a half times as fast as when storing the sign and the size of the comparable machine with a fixed word length. Furthermore, 3 ° A 'increments, which is the addition or subtraction, do not control the register size by statistically calculated. These flip-flops are also restricted in terms of the limit values. If used once larger generation of overflow signals.
As a result, words are desired, they can be used within the DDA 30 without As stated above

any changes to the machine will be used and transmitted using ternary encrypted numbers. 35 So have Delta-X, Delta- Y, and Delta-Z bits

Each of the Y and Α registers (with a specific possible value of -1, 0 or +1. The ternary embodiment) is a circulating register with a numbering system used to determine the track length between the heads of 1600 binary bits formation of small increments possible increased formation. Each of the tracks has space for 3200 bits for accuracy. The use of the ternary so that an itoration is only half a drum system, however, requires that both the landmark require rotation. as well as the size of the overflow of the / ^ register

The in Fig. 3, the F register shown schematically is recorded by the Z lines. For this purpose, FDY09 is formed by a write flip-flop, two Z-line traces are provided, and controls the signals that are sent via the write head amplifier one for the sign and one for the amount WDY09 and a write head to the magnetic track 45 of the overflow information .

skate. The overflow is generated by the

a read head, which is connected to a read head amplifier program control tracks in accordance with the following .RDYOl, is controlled via the signals to a read control. Is the as i? Number plus the sum of the flip-flop FD YOl to be transmitted. By switching the new F-number times Delta-Ä "equal to or greater than the arrangements in the logic switching matrix, a 5 ° 1/2, a unit amount bit and a zero cycle away between the flip-flops FDY09 and Sign bits generated to produce a delta-Z increment FDFO1 to indicate the arithmetic operation of +1 If the sum of these numbers functions of the F register, combined is less than 1/2, but equal or

The DDA logic switch matrix has one greater than -1/2, a zero magnitude bit is generated, full adder which is used to identify the sum of the 55 by a delta Z increment of zero. Delta-F-Increments with the F-Numbers in the F-Register If the sum is less than -1/2, units are to be added or subtracted from these. The amount bit and a zero sign bit generated by full adders have a carry flip-flop FDF08. indicate a Delta Z increment of -1. The information relating to the summation of delta generated increment overflow signals come from the F values is entered and removed from the adder from a shift register 60 Å register to an overflow, the a plurality of flip-flops FDF02 coding circuit, the two overflow memory and to FDF06 and associated circuits within decrease flip-flops FDZOO and FDZ10, the matrix has to a plurality (with a These flip-flops store the sign and the special embodiment up to 7) Delta-F-Incre- amount of each Overflow signals. To add up from the ments. The adder also receives 65 decrease flip-flops, the signals based on F-number information from the F-register. On from commands of the program to the Z-lines this way can be transferred under the influence of the program,
channels several Delta-F-Increment-Signals from the The amount-Z-line has a write-flip-flop

FDZ02, a write amplifier WDZOl, a write head, the magnetic track and a plurality of read heads which can be connected from the logic switching matrix to read head amplifiers RDZQl and RDZ02 . In a corresponding manner, the sign Z line comprises a write flip-flop FDZ 12, a write amplifier WDZIl, a write head, the magnetic track and read heads which can be connected to read amplifiers RDZXl and RDZ12 .

Normal storage, both in the amount and in the sign Z line, is carried out by means of short-loop circulating registers. In the case of the amount line, the memory is circulated by means of a loop that connects the write flip-flop FD Z 02, the amplifier WDZOl, 50 bit spaces on the track that separate the write head from the first read head, the amplifier RDZ02 and a path back the write flip-flop FDZ02 controlled by the matrix. The circular loop of the Z-sign line comprises the write flip-flop FDZ12, the write amplifier WDZIl, 50 bits of the track which separate the write and the first read head, the amplifier RDZ12 and feedback to the flip-flop FDZ12 controlled by the matrix. Once an incremental signal has been introduced into the two lines, it circulates in the 50-bit path until it is overwritten by a subsequent signal. Since it is rewritten every 50 bits, it runs along the track to the further reading positions and is repeated at 50-bit intervals. In this way, each incremental signal can be selected by each read head at an interval of 50 bits. Since the heads are 260 bits apart, the occurrence interval is even less than 50 bits.

. The flip-flops FDZOO and FDZ10 provide intermediate storage so that delta-Z overflow signals can be selectively written into the Z lines in positions which are determined by a decrease command. In this way, information can be temporarily stored in the pick-up flip-flops and written into the Z-lines in almost every position in order to facilitate communication with certain integrators and to make better use of the integrator space. The contents of the two acceptance flip-flops can also be transmitted directly to the integrator sections as delta-y or delta-y input signals, which further increases the application possibilities of the system.

The circular paths also ensure storage during the under the control of the general purpose computer 10 circulating operation in progress. During this operation, information becomes in each of the Z-line traces rotated between the write head and the first read head while each further information is destroyed.

By using the acceptance flip-flops and the plurality of reading heads that are in appropriate Intervals are arranged along the traces of the Z-lines, a rapid and easy communication of the system. This is particularly useful in a digital integration system, in which the integrators are of variable length because of the variable length feature with regard to the time saving and the utilization of the storage space can only be fully utilized can, if the communication with the Z-lines is designed so that increment input signals to appropriate time can appear without delay.

The DDA 30 has an additional register. This sequence control register comprises 4 flip-flops FDKOl to FDKOA. It stores signals which characterize the operating mode being executed (e.g. integration) and takes over overall control of the operation. When performing its functions, this register responds both to signals from the program tracks and to signals from the universal computer 10.

General description of how the DDA works

As mentioned, the digital integration system 30, controlled by the universal computer, can operate in circulation work or, controlled by the program tracks, in integration and servo mode. Under the Influence of the program tracks, it can also be used for certain input-output functions will.

The commands given in Table II below can be used to program the operating mode of the DDA 30 can be used in integration mode and in servo mode.

Table II

command

Program track number

Complement dz ₀

Decipher dz ₀ + as dx

Decrypt Uz ₁ as dx

Decipher dz ₂ as dx

Decrypt dz ₃ as dx

Decipher dz ₄ as dx

Decipher dz ₀ as dy

Decipher dzj as dy

Decipher dz _z as dy

Decipher dz ₃ as dy

Decipher dz ₄ as dy

Decrypt dz ₁ as dz ₀

Decrypt dz ₂ as dz ₀

Decrypt dz ₃ as dz ₀

Decrypt dz ₄ as dz ₀

Overflow after dz ₀

Overflow to dz ₀ and takeover of

dz ₀ to dx

Decrease dz ₀ positive

Decrease dz ₀ negative

Start servo operation

Start integration operation

Do nothing

Entrance 1

Entrance 2

Entrance 3

Entrance 4

Exit 1

Exit 2

Exit 3

Read the input-output trace

Write in the input-output track

Key to the trail

54321 11000 11010 00100 00101 00110 00111 01000 00000 00001 00010 00011 10000 10001 10010 10011 OHIO

01010 01001 01011 01101 01100 01111 11100 11101 11110 Hill

10100

10101 10110 11011 11001

The operations effected by each of the above commands result from the following Description.

19 20

The integration operation of the DDA ^ registers minus 1/2 < R <1/2. Negative forms

are printed in two's complement form. As

The number of integrators available and the one mentioned gives the highest bit position in the .R register

Length of each integrator are under the influence of the sign of the number in the ^ register. To this

Program variable. Referring to FIG. 5, 5 way, two bit times are required to get the

which is a diagram of some of the instructions that generate delta Z overflow, namely a bit time,

given during certain bit times, which indicates the highest bit position, and

it results that an integrator is started, another bit time which is the sign bit position

if indicates on the program tracks during 4 bit times,

a command "Start the integrator" occurs. As below io servo operation
explained, the start period can in certain cases

be less than 4 bit times; However, 4-bit times are sufficient. In many cases, the specified mechanical times are sufficient for all cases. This command sets the control or electronic arrangements to which the flip-flop FDKO1 is assigned to the integration interval to DDA, do not process signals that determine, so that further program commands have a value of zero for 15. As a result, the integration must be able to be carried out. Before the delta-Z signals with the value zero, the special command "Start the integrator" shown in the course of an integration of DDA 30 to achieve external, the DDA runs through other operations, and the most precision is generated, often for outputting incremental input signals for the special interest - be converted to another form outwardly, sizing integrators are deciphered. During 20 the DDA 30 does this by converting this interval code from ternary form to binary form under program control. The different increments of the Z-line sputtering are made in servo mode.
The servo operation takes place under the control of the type, which is controlled by flip-flops FDR02 and FDR03 program tracks. Essentially the same and the Delta 7 summing register will be formed. 25 components as used for the integration, with the exception that the register function is not used by the program tracks, the delta 7-in remains after receipt of the command »start the integrator«. In the DDA 30, the servo operation is generally selected and initiated in the delta by the fact that a command "Start servo 7 summing register (the flip-flops FD 702 to FD 706) was operating" during four successive bits were combined in which appears from the matrix 30 times on the program tracks. While formed full adder circuit shifted. The first of the command "Start servo operation" is the sum of the 4-bit times for this shift function - delta 7-increments that are used for servo operation. Then the integration begins automatically, the Z lines are decrypted from the operation, and the sum of the delta Y values is shifted to the summation register in the 7-register full adder by means of the full adder with the 7-number in the 7-register 35.

added while the new 7-number in the .R register with During servo operation, which automatically after

the R-number is added. During this period the four consecutive commands »Start servo

can according to FIG. 2 the different start-up «begins, a certain number becomes ternary

increment input signals for the next integrator notation converted into binary notation,

can be decrypted (the delta A 'input signal only, 40 so that it can be used for external communication purposes

after the 7-number can be given according to one. The operation is done by the

if there is a delta A 'input signal added to the delta F increments with the 7 number and that

J? Register is transferred). External sign of the 7-number and the value of Delta-Z

Increment input signals can also be used to generate the Delta-Z overflow

and overflow output signals after 45. To make sure Delta-Z- never

be transmitted externally. If it becomes zero, a positive clock pulse becomes the Delta-Z

The end of each integrator is being overused.

run command specified, which occurs during two consecutive An overflow command terminates servo operation

The following bit times on the program channels generate and generate the corresponding output signals. Of the

appears. After this command has been received, servo operation and integration can be

.R register overflow for a specific integrator using different lengths of the 7 memory track,

generated according to the rules given above and the output signals can be used for later use

to the decrease flip-flops FDZ00 and FDZlO stored in the Z lines or immediately for

convicted. The overflow bits can then be used for external communication purposes.

Z-line trace saved or according to Pro- 55

program commands can be used in a different way. Circulation operation

It should be particularly emphasized that an integrator The recirculation mode represents the third basic operation

both started and displayed by program commands that can be executed by the DDA 30. the

is stopped. This facility allows the wraparound operation to occur when the general purpose computer

Formation of integrators of variable length, whereby 60 10 executes the command »Let the DDA circulate«,

the machine operation is significantly accelerated. Execution will start after the command has been issued

The overflow command determines the sign bit delayed, so that the circulation only after completion

Position of the integrator word. The sign of one of an iteration cycle begins

positive number is represented by a binary zero in the. During circulation, the contents of the

Sign bit position shown, the sign 65 Y and Λ registers around and are represented by the in the

a negative number by a binary 1 in the pre-program channels (which are not taken into account)

character bit position. Not modified in the case of a special execution form. The contents of the

Form of the invention is the maximum area of the 50-bit long recirculation paths the Z-lines run

also, while the information not contained in these circulation routes is destroyed. Of the DDA 30 rotates until the digital computer 10 issues the command "Start the digital integration system". This command is also only executed after the DDA 30 has received an origin point of the Drum track reached although the command can be given at any bit time.

The overall control of the mode of operation of the DDA 30 takes place by means of commands which originate from the universal computer 10 and the program channels and which act on the sequence control (. K) register. The sequence control (A> register has four flip-flops FDAOl to FDK04 . Basically, the flip-flop FDKOl controls the integration mode, the flip-flop FDK02 controls the servo mode, and the flip-flops FDK03 and FDK04 take care of the program control of the DDA £ On the basis of integer input-output possibilities, whereby they also participate in the control of special operating modes under the command of the universal computer 10.

The integration cycle begins with the setting of FDKOl. The flip-flop FDKOl is cleared either after the first bit time of the overflow operation or after the initiation of the circulation operation.

The servo operation is initiated when the flip-flop FDK02 is set. The servo operation is terminated either with the last bit time of the overflow or the receipt of a rotation command.

The general purpose computer 10 controls the operation of the DDA 30 in performing a variety of functions by monitoring the status of the sequence control (AT) register. These functions are entering the initial conditions of the DDA, clearing and entering the initial conditions of the DDA, clearing the R and Z registers, the

ίο Circulating the digital integration system, starting the DDA and transferring the contents of the F register to the initial condition track. The actual control is effected by means of a general universal computer command “Control the DDA” in conjunction with a specific encryption of a track address (D) register of the universal computer 10. The output signal generated by an inverting amplifier / G / 67 of the general- purpose computer 10 causes the amplifier IDIO1 to generate a signal that means "control the DDA". The code appearing in the track address (D) register of the general-purpose computer 10 specifies the specific of the six control functions to be carried out for the DDA. The conditions of the flip-flops FGDO1 to FGD05 of the track address register D for controlling the special operations of the DDA 30 under the influence of the general-purpose computer are summarized in Table III below.

Table III

Function of the DDA

States of the D-register flip-flops FGD 03 FGD 02 FGD 05 FGD 04 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0

FGDOl

Entering the initial conditions of the DDA ...
Enter the initial conditions and delete

of the DDA

Clearing the R and Z registers

Start the DDA

Circulating operation of the DDA

Transfer of the contents of the y-register to the

Initial condition trace

0
1
0
0

As stated above, general purpose computer 10 can have another very useful operation with respect to FIG Execute din DDA 30. Because one of the Storage, acceptance or other universal computer commands has a memory address, words from the general purpose computer 10 can be put directly into the y-register of the DDA. The y-register is simply addressed as a further memory position. This option allows single word corrections to be carried out and offers other advantages.

As mentioned above, the conditions of the flip-flops FDKOl to FDÄO4 of the sequence control. Register K is controlled not only by the universal computer 10, but also by the program tracks of the DDA 30. The program tracks each supply signals via read head amplifiers RDPOL to RDP05 for setting and deleting the program track read flip-flops FDPOL to FDPOS. The five program tracks can store 32 individual commands.

Initial condition trace

The main function of the initial condition trace of the DDA 30 is to record information, by means of whose starting F-numbers are placed in positions that correspond to the various integrators of the Y register are selected. Basically, the initial condition track serves as a modifiable storage track, by means of their suitably calculated initial F-numbers with the aid of the universal computer 10 into the y-registers can be introduced. You may initially address a problem or then used when updating a problem, where the y-numbers are a series are linked by integrators and require mutual renewal.

The initial condition track basically comprises the part of the magnetic track between the read and

Write heads that are connected to the amplifiers RDP06 and WDPOl, these amplifiers, the write flip-flop FDPOl and the read flip-flop FDP06. In order to write information from the A, B and M registers of the general-purpose computer 10 into the initial condition track, the general-purpose computer 10 performs the commands "Save A", "Save B", "Save M", "Add — Replace" and "Subtract — Replace" was created.

The initial condition trace can also be used to transfer information from the 7 register to the general purpose computer 10. The initial condition write flip-flop responds to the information contained in the 7 register as the initial stage of the transfer. The initial condition trace is queried by means of the assigned read flip-flop FDP06, which also supplies output signals for the circulation and for entering the initial conditions of the 7-register.

The 7 register

The 7 register includes the magnetic drum track between the read and write heads, which are connected to the amplifiers RDYOl and WDYOl , the read flip-flop FDYOl, the write flip-flop FD 709, the delta 7 summing register with a Adding input flip-flop FDY02, three delta-7 summation flip-flops FD 703 to FD 705 and a sign flip-flop FD 705, and finally a logical full adder circuit at the input to the carry flip-flop FD 708. The summing register is discussed in the following section.

The read flip-flop FD YOl is used as an input channel for the 7 register. The universal computer 10 can write into the 7 register under program control via the flip-flop FD 701. The operation is performed as if the 7 register were part of the modifiable memory of general purpose computer 10 while general purpose computer control prevents normal operation of the 7 register. This function allows the general-purpose computer 10 to correct, replace or otherwise renew individual 7-numbers without disrupting the operation of the digital integrator or loss of iteration. The general-purpose computer 10 simply writes the new word into the read flip-flop FDYO1 in place of the circulating word.

The DDA 30, controlled by the program, can also use the read amplifier AD 701 of the 7-register (the normal input) or the output of an input-output buffer stage (a magnetic track) as the input of the read flip-flop FD 701.

The input-output track designation retrieves or routes signals from a magnetic storage track there, with the magnetic storage track as a modifiable intermediate storage between the DDA and the Universal computer 10 is used. It can serve either or both and is particularly useful as a Buffer for intermediate conditions and results of the DDA.

Delta 7 summing register

The delta-7 increment signals selected by the Z lines for summation with a specific 7 number are algebraically added in the five-stage flip-flop register FD 702 to FD 706. The stages with the flip-flops FD 703 to FD 705 are designed as the forward-backward two's complement parallel adders. Such an adder can work with the ternary input signals from the Z lines and, depending on their signs, either add or subtract certain increments. These stages are supported by the FD 706 sign memory flip-flop.

The decrypted values of the Z-lines are transferred to the summing register, added there and together with the corresponding sign held back until an integration start or servo start signal Will be received. Then the signals characterizing the summation are transmitted via the flip-flop FD 702 shifted into the logical full adder in order to match that stored in the relevant position of the 7 register 7-number to be added. The first four bit times of a servo or integration operation will be exploited for this shift operation. After the absolute number is shifted, the sign becomes

ίο held in the flip-flop FD702 for the remainder of the integration or servo interval to the relevant To control summation.

The shift interval can be shortened if the number of delta 7 increments added is less than 4. For example, only two bit times are required to shift a single delta 7 increment, since only the lowest bit and the shift flip-flop FD 702 have to be passed through. Similarly, only three bit times are required to shift three or fewer delta-7 increments.

The i? Register

The Ä register comprises the portion of the rotating magnetic recording track of the drum between the write amplifier WDR 07 and the sense amplifier RDA 01 associated magnetic heads, ^d: ese heads and amplifier, a write-type flip-flop FD.R07 and a read flip-flop FD.ROl. The i? Register also has within the logic matrix of the DDA a circuit comprising a carry flip-flop FDR06 for performing a full adder function and for utilizing the delta-X control flip-flops FDR02 and FDR 03 as well as one associated with overflow generation Flip-flop FDJTOO on.

As explained above, the read and write heads of the circumferential track of the λ register are located 1600 bit positions corresponding to half a track length from one another. The read amplifier RDAOl is directly connected to the read flip-flop FDROl . From the read flip-flop FDi? 01, the signals of the matrix of the digital integration system circulate to the write flip-flop FDRO1.
On the other hand, the addition of the R number and the 7 number is effected in accordance with the delta X input signal by means of the full adder of the λ register.

Besides the information from the full adder also runs

information contained in the i? register about the write flip-flop FDROl when Delta-Γ is equal to zero. Information can also circulate when the DDA 30 is operating in circulation, whereby signals can be provided in order to clear the Y? Register to zero under the control of the general-purpose computer or external write signals can be supplied.

Overflow facility

Since the Ä register stores information with positive and negative values (between -1/2 and 1/2), two bits (sign and amount) are required to represent an overflow increment. The highest Bit position indicates the sign of the number, the next its amount. When the total value of the i? number and the 7 number is greater than or equal to 1/2, a positive Delta-Z increment is generated. Lies the total value between the two limits, only zeros are generated. If it is less than -1/2, it becomes a negative Delta-Z-increment generated.

509634/13

25 26

The flip-flops FDROl, FDR03 and FDXQO are destroyed while new information is received from the

Input signals from logic circuits to the acceptance flip-flops FDZOO and FDZ10 are input

Generate overflow signals that will be used for the purpose. The flip-flops FDZ02 and FDZYL allow

corresponding Delta-Z generation are characteristic. the input of external incremental input information

In servo mode, there is an output signal in the form of 5 tion. For increment output signals, the in of a binary zero is never permitted in the overflow. To formation of the first read head RDZ02 the amount for this purpose it is provided that the read during the line and RDZIl of the sign line. Delta-Z overflow increment generated by servo operation. The output is then sent to an external circuit, equal to the sign of the Y number and the amount, for example, buffer stages not illustrated, from Delta-Zist. In order to separate zero output bits ίο transferred, depending on the purpose in question, a single-valued delta A 'is always generated. In which is provided.

The last bit time of the overflow is always a delta. With different references to the Z lines

'Increment of size +1 generated, if not one, the reading positions are designated with Z ₀ , Z ₁ , Z ₂ , Z ₃ , Z ₄

Delta-X decryption command (signal FDP03 +) net. Z ₀ refers to the acceptance flip-flop,

will give. This necessarily leads to the fact that 15 Z ₁ on the first pair of reading heads etc. is the delta Z increment for the next number

Has a value of 1. How the DDA works

The Z-Lines The filling operation

In the case of the digital integration system, two Z lines are provided, as in the case of the universal computer 10 of the system, in order to represent the ternary values of the filling operation of the DDA 30 with the help of conventional, +1, 0 and -1, the possible values of unillustrated devices, the one with the Delta-Z overflow. Each line has an identical read / write head arrangement only during the filling operation. Each line includes is connected. The device is used to write, in addition to a magnetic track, a write flip-flop, a write amplifier over the read heads for the purpose of filling the program write head for recording, and a write amplifier. If a problem arises with the information in question from a write flip-flop, initial delta ^ T and takes a number of delta y increments at predetermined intervals also by means of the external read heads and two read amplifiers. direction can be written into the Z-lines. For example, the amount Z line has a write 30 Essentially, this method is used for the weight flip-flop FDZ 02, a write head amplifier to facilitate the device, so that it is better WDZOl, a first read head HDZSO, one for weight reduction the device so that it read head HDZSO connected first read head is better for ventilation applications and other amplifiers RDZOl, a second read head HDZSl, cases where a minimum weight is a third read head HDZSl and a last 35 main criterion. It goes without saying that it would also be possible without the HDZ 83 read head. The three last-mentioned read heads would also be able to physically assign filling devices to the system via a logic circuit. You can receive various additional arrangements connected to a second read head amplifier RDZOl , such as punched strips, holes. card and magnetic tape input devices in connection

The particular read head selected is determined from among the 40 with various known forms of buffer control of the five program tracks. The save. Since these devices do not form part of the read head amplifier Ai) ZOl supplies Delta-Z information of the present invention, they are not dealt with in more detail for reasons under the influence of the program on the Delta-X and for the sake of clarity. Delta-y decryption stations. ". ,,. . ... . __.

The read head amplifier RDZOl is in a return 45 ^{Emgabe of the} initial conditions in the DDA leading to the input of the amount Z line for integration and servo operation must

running slice of 50 bits, so that information about the initial conditions can often be introduced into the initial condition flip-flop FDZ 02 for the amount Z line and read into the y register. before the operation begins. The first

A decrease sign function is carried out in a similar manner by arranging the contents of the A, B or flip-flop FDZ 10, the overflow sign A / register into the information via the write flip-flop FDPOTI Write flip-flop FDZ10 for the initial condition track are read. Pre-sign Z-line gives. The sign Z line is to be raised so that during operation the beginning also has a 50-bit long circular loop , conditional track such as a modifiable memory that addresses a read head amplifier RDZIl and a flip position of the general-purpose computer 10. The flop FDZIl, as well as read heads HDZ90, HDZ91, second function is carried out either by the command HDZ92 and HDZ93 . The last three "Universal computer - enter initial conditions - heads are selected by means of a logical link Delete" or the command "initial conditions to enter the output amplifier RDZIl ". It should be remembered that these two sign lines feed. The outputs of the 60 commands of the general universal computer command "Control read amplifier .RDZOl and RDZIl are assigned to the DDA" before they are assigned. The command "Enter clock-wise input into a flip-flop immediately for the initial conditions - clear" is given, logical gate control is used so that the If the DDA was used for any previous address for the read head and the decryption operations and its registers old command can be the same logical expression. 65 contain information that must be deleted

The information circulates in the 50 bits long before the new problem can be dealt with. Of the Z-line loop is given by an acceptance command. The command »Enter initial conditions« is given, interrupted, which causes the old information to be removed if the registers have already been cleared, or if a

27 28

Set of corrected 7 digits that depend on each other to produce ternary overflow output that is a

should be entered during a problem. Has a sign bit and an amount bit.

Both commands require the universal computer command. The signal »Start integration operation«, which is displayed in

"Control the DDA". In any case, what appears in the program tracks will cause the

Initial condition track contained initial conditions 5 sequential control registers FDKOl to FDKQA the in-

operations one after the other from the track via which angration operation is initiated. The state of integration

Catch condition read flip-flopFDPOe and the F-Re- the sequence control - (. K) register causes the

Register write flip-flop FD Y09 in the corresponding write flip-flop FD Y09 of the 7 register the addition

Positions of the 7-register track transferred. of signals from the addition of the delta Y register

Both operations will start io and information in the Y register track for each

conditions from the initial condition track into the special integrator programmed in the Y register

Read in Y register. As mentioned, this is the initial recording. These sizes are added together,

As explained above, the integration operation

Drum filled because initial conditions only triggered for a single integrator by that

Part of the F-register memory track 15 in the memory tracks the command »Start the integration

between the read and write heads, integration operation «for four successive integration

d. H. along half the drum circumference. valle appears.

As mentioned above, 7-numbers can also be transferred from the operation of the command "Start the integration Y-tracks taken from the initial condition track" in the program channels for the correct and to the universal computer 10. This period causes the amplifier NDYOO to be activated by the general-purpose computer command, which generates the signal that either the command »Start the transfer between these tracks is provided. Integration mode "or the command" Start the The information can be identified after it is once in the servo mode ". The occurrence of the initial condition track signal is stored, to which the university "Start the integration operation" leads into the program computer 10 through direct addressing 25 tracks the addition of the sum of the delta-Y increments as a memory position is transferred. and the Y number stored in the Y register. -,. . , ". , _ As explained above, the sum of the delta operations with the input-output track is y increments via the summing register in the full

The function of the input-output track as an adder circuit shifted, which is the Y-register small memory, which is assigned to both the general purpose computer 10 30. In the equations for the transmission which is also assigned to the DDA 30, flip-flop FD Y08 provides the signal FD YOiI in each case mentioned in the above. The use of the track is triggered by the first expression of the sum of the delta Y increments DDA 30 via the read or write command, which are to be added to the Y number during this. In the case of a read command, the information in signal FDYOl is the Y number. It should be noted that the track from there in the read flip-flop FDYOl of 35 that the sign of the sum of the Y increments 7 registers let. in the flip-flop FDY02 of the summing register during

In the case of the write command, the information from the operation of the full adder is retained

Γ register written to the input-output track. the operation in question

Both commands take over as well as control the commands.

"Start integrator mode" and "Start servo mode" the 4 ° after the 7 number and the delta-T increments

Controlling the DDA 30 and continuing until an over- combined can be a number of operations

run command is received. occur. For example, new Delta Y-In-

The provision of the track opens up special possibilities for the Z-lines or the acceptance

opportunities for the entire system by decrypting an intermediate flip-flop and adding it to the summing register

memory for the DDA 30 is created. It can be saved 45 times in the next integrator

also in connection with the universal computer 10 the. A

used, but is usually there to be decrypted for Delta X increments, even though the

Storage purposes not required. Your primary old Delta-X cannot be replaced before the

Use in conjunction with the universal computer 10 R and Y operation is complete. During the

would be for transportation purposes. 50 addition also becomes the new 7-number with the-number

in the register of the integrator according to the

- The integration operation Delta-A "increment adds that in the Delta-.T-Ent-

encryption flip-fiops is stored.

The integration operation for an individual The operation by means of whose increments the integrator is decrypted by the occurrence of command 55 Z-line and stored in the delta-Y-summing "start integrator mode" on the five program registers follows. The decryption track command during four successive bit times is triggered by the encryption of the program. The four bit times sufficient to the tracks in a particular Tatkintervall obtained, the sum of the delta Y increments number representative of the particular instruction causes the over the Summierregister with the flip-flops FDY02 60 different read head positions of the Z -Line verbis FDY06 in the full adder of the Y register to move the logic circuit bound in the respective. As mentioned above, the position interval can provide stored increments. The signals that are shortened when very few Delta-Y-In-Y-increments are represented are processed by the increments. The integration cycle sense amplifiers RDZOi, RDZOl, RDZW and RDZ12 begins automatically after the command has been completed and 65 transferred to the flip-flops of the summing register, continues until an overflow signal from the five program channels in addition to the usual addition of the program channels during two bit times can receive sum of delta y increments to the y number . The two bit times are sufficient to replace the Y number with a corrected Y number

which is supplied by the general-purpose computer 10, and can this number with the incremental sum can be added. This operation takes place on the basis of one of the commands of the general-purpose computer 10 (for example "Store"), which uses the Y register as an addressable memory location (see description above of the universal computer 10). Any part of the information in the Y-track can be replaced in this way to correct it or to renew it in some other way. It should be emphasized that the new Y number is added with the delta Y increments without losing an iteration, since the input from the universal computer 10 is on the read flip-flop of the Y-track, so that the machine speed is increased.

The addition of the Y number and the Ä number in the jR register takes place in accordance with the value of the delta Z increment stored in the flip-flops FDR 02 and FDR 03. The decryption of a Delta-X increment is carried out in the same way as the decryption of the Delta-Y increment. The logic circuit connected to the sense amplifiers of the Z line causes the delta A 'increment to be transmitted to the delta X memory flip-flops FDR02 and FDR03. As mentioned above, the acceptance flip-flops can also be used as a decryption station instead. By using the decrease flip-flops, the delta X increment for a subsequent integrator can already be deciphered before the Y and A numbers are added under the influence of the old delta A 'increment. This is done using the commands »Overflow to AZ ₀ and take dZ ₀ to dA '« and »Decrypt dZ as dZ ₀ «. The last-mentioned command decrypts an increment on a certain Z-line reading head and transfers it to the acceptance flip-flops FDZOQ and FDZ10 _{(called dZ 0} in command language) for storage, while the first-mentioned command causes the increment to be saved once is stored in the acceptance flip-flops, is automatically transferred to the delta-Z memory flip-flops FDR 02 and FDR03 when an overflow occurs.

The addition of the Y number and the R number is done by the full addition matrix of the i? Register. All expressions of the full adder matrix are addressed to the write flip-flop FDRO1 of the λ register.

The amplifiers supplying the true and false inputs are activated as a function of the register carry signal, of the Delta JV increment and the Y number energized. One of the inputs of the full adder of the .R register represents the output of the full adder of the Y register. Using the full adder output of the Y register as an expression in the Full adders of the ft register can perform the combination operations the Y and Λ registers can be carried out at the same time. This precludes the Y-number at a first iteration and the-number at a second iteration of the magnetic drum is processed and improves the accuracy of the means of the DDA 30 calculations made.

The Y-number is added to the Ä-number by adding bits one after the other. After the addition is complete, the integration cycle can be completed by the fact that the command "Overflow" (Table II) appears on the program tracks for two successive bit intervals. The overflow command energizes the flip-flop FDR02. During the second bit time of the overflow period, the overflow signals are generated in the decrease flip-flops FDZ 00 and FDZ10 . As mentioned above, the

Overflow have three different values, namely a positive 1, a 0 or a negative 1.

The overflow information can then be decrypted by the pick -up flip-flops for immediate use as a Ddta.-X or Delta-Y increment or stored in the appropriate positions on the Z lines for later use.

As mentioned above, the overflow command can go through

ίο the command »overflow to dZ ₀ > .nd take dZ ₀ to dX« should be replaced. The latter command causes the same overflow to occur, but additionally shifts the stored delta Z increment from the decrease flip-flops to the delta A 'memory flip-flops FDR02 and FDR03.

The storage in the Z-lines is designed so that in particular communication with all Integrators is favored. So the overflow information can be kept in the decrease flip-flops until the flip-flops are needed to save the overflow from the next integrator. These The possibility provides a considerable selection period which can be used to improve the distribution of information on the Z-lines. Further

The short circulation loops of the Z-line can take advantage of each of the starting positions to increase the availability of the output signals and improve communication. The above-mentioned command "Decrypt to the acceptance flip-flops" serves to further facilitate communication, while the command "Complement dZ ₀ " is available to facilitate the operation and increase the machine speed.
This extreme option of storage along the considerable number of decryption positions which are available via the multiplicity of reading heads improves the internal communication of the digital integration system 30 considerably. In particular, it makes the arrangement of integrators of any length possible and usable in practice.

The storage and selection of the Z-lines has already been discussed as far as the integration operation is concerned. It was, however, at the end of the Discussion of this operation highlighted that the incremental inputs (e.g., accelerometer inputs) entered using the four program input commands of the digital integration system which are given in Table II.

The increment input signals are received on write flip-flops FDZOl and FDZU , which represent the inputs to the amplifiers / DZ24 and IDZ26 . The inputs can be introduced during the respective integration operation (as well as Z-line increments can be deciphered). As a result, there is no delay required to intercept external incremental input signals.

The servo operation

As mentioned above, the servo operation is specially designed for communication and ternary signals used for mathematical calculation within the digital integrating system 30 To convert the transmission to the outside world into binary notation. Servo operation is initiated by that the command "start servo operation" occurs for four or fewer consecutive intervals

31 32

appears on the program tracks. The program Ä registers circulate without change. So they have

states for the special command are in the above delta Y and delta A 'increments which are in the

Table II given. the relevant registers assigned to flip-flops

After the command »Start servo operation« has been saved, no influence during the cycle,

is received, the in the delta F-summing 5 During the circulation operation also runs in the

register contained sum of the delta y increments short, 50-bit long circulating loops of the Z-line

The information contained in the 7 register is transferred to the full adder circuit. All other information

ordered logical switching matrix shifted. This tion of the Z-lines is destroyed, however, since the

Operation corresponds to the one that necessarily requires the writing

Integration operation takes place. io operation every fiftieth bit of the under heads

As with the integration operation, the track passing by will have to rewrite. The sum of the delta-y increments over the information destroyed by adding is, however, shifted relatively registers into the adder. The adder is unimportant and only belongs to a single iteration, asks the one in the carry flip-flop FDYOS, in the Y- and R-Re flip-flop FDY02 of the summing register and in the 15 register tracks there is no since the read and write heads read flip-flop FDYOl of the F-register contained a full half a track length apart and the information from. In this way, the adder roundabout consequently receives rewriting of the roundabout information which entails the carry over, the information to be added in the same position, numbers as well as the y-number, and effects the in the the information during every other opera -Addition would occur according to the recorded information.

tion. As with the integration operation, the cyclic operation is normally only used for test purposes for the sign of the sum of the delta Y increments. For example, a cycle would be provided during the operation of the full adder of the F-operation, if it were desired, to be held for gisters in the flip-flop FDY02 so that the respective integrators can be seen at the same time in order to carry out a speaking addition or subtraction to check,
can be. In addition to the conversion controlled by the universal computer

The Λ register is not run during servo operation, Table II contains a command "Do nothing",

used. The servo overflow is enabled by the front of the entire DDA 30 to have one

sign of the y-number and continuously occurring specific function, e.g. B. an integration, continues,

positive Delta X values generated. 30 without information being generated or any other information

Function disruptive function is taken over according to the above-mentioned conditions. Of the

the amount flip-flop FDZOO is always set when an instruction is required to make the machine work

an overflow in binary encryption is generated, do not interrupt if no for the operation

in contrast to an in ternary encryption, a special command is required.

generated overflow. On the other hand, the sign becomes 35 “. j »i_ · -jai

Overflow flip-flop FDZlO in the true or summary of the operation of the system

Incorrect state depending on the sign of the y-number The mutual connection of the digital computer 10

after the addition with the delta F increments and the DDA 30, basically two categories

brought. rien be divided. First, the universal

As mentioned above, single numbers of the y-register and the

operated in which ternary numbers in binary numbers initial condition trace through each of its own

be converted to process the sign of the delta JSf instructions that contain an addressable memory

Increments kept positive by showing a positive position. Second, the universal

Input signal is provided. In certain cases computer 10 and the DDA with logic circuit

however, the programmer may wish to provide 45 arrangements to enable the

to change the delta Α 'values in order to enable special universal operating computers 10 to independently

to execute. standard functions related to the operation of the

It should be noted that the delta DDA 30 is performing the decryption.

y increments are made in a way that is essentially

lichen identical to that of the decryption of the 5 ° sal calculator 10 numbers from the F register track or the

Call delta-y increments during the integration operation to trace them within

tion is. That is, the decryption signals are processed by the general-purpose computer 10. This allows

programmed in the program tracks, and who add numbers in these tracks of the DDA,

appropriate Z-line operation is read to subtract those to compare with other numbers,

To determine the meaning of the information located there. 55 to multiply, generate and in different

process in a different way to make corrections

Feed circulation operation, make logical links and

to fulfill other purposes. An example of the extreme

The circulation operation is from the universal computer 10 possibilities that are opened up by the fact that a

ordered. Circular operation begins when the next 60 position of the DDA is addressed as a memory position

control flip-flop FDK03 set and the flip-flop can be, it follows that a certain

FDK04 is deleted. It is also interesting that the y-number in a particular integrator goes to the /! Register

Circulation command from the universal computer is given priority and there for control purposes with a number

final command is. While it is present, neither one can be compared with the help of the result of the

Integration operation can also be carried out in a servo operation. 65 Compare a first or a second command selected

When the wrap-around command is received, a corrected y-number can be passed back in

the DDA runs a number of operations. Which the y-register position can be brought out

Information in the y-register and the information in which the original y-number was taken. It

it will be understood that the general purpose computer 10 also uses each number held in a particular register which can route store instructions to the F register or the initial condition trace. In this way can do a certain processing, for example a calculation of a series of initial conditions or a correction of a certain F-number can be carried out and the relevant number can be brought into the correct position of the DDA 30. All address commands of the general-purpose computer can be used in a substantially analogous manner to carry out operations to influence the DDA.

The second category of operations includes all operations that the general-purpose computer 10 automatically for the digital integration system 30

leads. These operations are carried out under the command "Control the DDA" of the universal computer 10 of these operations, information is transferred from the initial condition trace to initial Γ numbers for Providing the y register will circulate information within the DDA 30 and being cleared becomes information is transferred from the initial condition trace back to the general purpose computer 10 and the operation becomes of DDA 30 initiated. It goes without saying that it is

ίο These are operations that are often performed must be when the DDA 30 is in operation. The creation of logic circuits for automatic Performing these functions saves significant uptime both during setup as well as when checking the system.

In addition 7 sheets of drawings

Claims (5)

Patent claims: 1. Combination computer system consisting of a universal computer part and a differential analyzer part (DDA), the universal computer having a multiple memory, an arithmetic unit with several registers and a control unit and the differential analyzer part a y-register, an λ-register, an overflow memory and initial conditions memory characterized in that a sequence control register (K; flip-flop FDKOi to FDK04) which determines the mode of operation of the differential analyzer is provided, which both from a program memory (31) of the differential analyzer which can not be erased during operation of the differential analyzer (30) as well as from the universal computer (10) can be set that, in addition to the control commands that can be triggered by the program memory of the differential analyzer for carrying out the integration processes in the differential analyzer, the universal computer commands commands for transferring the contents of the initial condition memory of the differential analyzer to the y-register and the Lö between memories and registers (R, Z) of the differential analyzer can be triggered and that memory and registers of the differential analyzer (Y, initial condition register) can also be addressed with memory commands from the general-purpose computer for data transfer from and to arithmetic registers - (Λ, M, B). 2. Combination computing system according to claim 1, characterized in that the differential · analyzer (30) works with variable word length that the general purpose computer (10) and the differential analyzer (30) have a common storage drum that all control commands of the differential analyzer (30) are permanently stored on the storage drum and the differential analyzer (30) has an adder which can be controlled by these control commands in such a way that during a drum revolution numerous additions can be carried out. 3. Combination computing system according to claim 1 or 2, characterized in that all data and instructions within the differential analyzer are ternary encrypted. 4. Combination computing system according to claim 2 or 3, characterized in that Z-tracks of the magnetic drum (result tracks) have several reading heads and that two acceptance flip-flops (FDZOO, FDZ10) are provided as a buffer. 5. Combination computing system according to claim 1, 2, 3 or 4, characterized in that a read flip-flop (FDYOl) is provided as the input channel for the y-register (F i g. 3), via which the universal computer (10) correct y-numbers without interfering with the differential analyzer operation.