DE112022005506T5 - Halbleiterbauteil - Google Patents

Halbleiterbauteil Download PDF

Info

Publication number
DE112022005506T5
DE112022005506T5 DE112022005506.5T DE112022005506T DE112022005506T5 DE 112022005506 T5 DE112022005506 T5 DE 112022005506T5 DE 112022005506 T DE112022005506 T DE 112022005506T DE 112022005506 T5 DE112022005506 T5 DE 112022005506T5
Authority
DE
Germany
Prior art keywords
encapsulation
layer
semiconductor device
thickness
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112022005506.5T
Other languages
German (de)
English (en)
Inventor
Yusuke Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of DE112022005506T5 publication Critical patent/DE112022005506T5/de
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/40Encapsulations, e.g. protective coatings characterised by their materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/352Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
DE112022005506.5T 2021-12-21 2022-12-07 Halbleiterbauteil Pending DE112022005506T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021-207462 2021-12-21
JP2021207462 2021-12-21
PCT/JP2022/045145 WO2023120196A1 (ja) 2021-12-21 2022-12-07 半導体装置

Publications (1)

Publication Number Publication Date
DE112022005506T5 true DE112022005506T5 (de) 2024-09-26

Family

ID=86902306

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112022005506.5T Pending DE112022005506T5 (de) 2021-12-21 2022-12-07 Halbleiterbauteil

Country Status (5)

Country Link
US (1) US20240332101A1 (https=)
JP (1) JPWO2023120196A1 (https=)
CN (1) CN118414699A (https=)
DE (1) DE112022005506T5 (https=)
WO (1) WO2023120196A1 (https=)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010129758A (ja) * 2008-11-27 2010-06-10 Toshiba Corp 半導体装置及びその製造方法
JP2012199342A (ja) * 2011-03-20 2012-10-18 Fujitsu Ltd 樹脂モールド基板の製造方法および樹脂モールド基板
JP7179526B2 (ja) * 2018-08-10 2022-11-29 ローム株式会社 半導体装置および半導体装置の製造方法
JP7421877B2 (ja) * 2019-06-27 2024-01-25 ローム株式会社 半導体装置

Also Published As

Publication number Publication date
JPWO2023120196A1 (https=) 2023-06-29
WO2023120196A1 (ja) 2023-06-29
US20240332101A1 (en) 2024-10-03
CN118414699A (zh) 2024-07-30

Similar Documents

Publication Publication Date Title
DE69526895T2 (de) Verfahren zur Herstellung einer halbleitenden Anordnung und einer Halbleiterscheibe
DE602004005760T2 (de) Halbleitervorrichtung
DE102013103015B4 (de) Gitter-Gehäuse auf Wafer-Ebene vom Fan-Out-Typ und Verfahren zum Herstellen eines Gitter-Gehäuses auf Wafer-Ebene vom Fan-Out-Typ
DE112005001949B4 (de) Verfahren zum Bereitstellen von Stapelchipelementen
DE102011053871B4 (de) Multichip-Halbleitergehäuse und deren Zusammenbau
DE102014102006B4 (de) Halbleitermodul
DE4230187A1 (de) Baueinheit mit speicher-ic, sowie verfahren zum herstellen einer solchen baueinheit
DE102014100509B4 (de) Verfahren zur herstellung und testung eines chipgehäuses
DE10009733A1 (de) Halbleitervorrichtung und Verfahren zum Herstellen derselben
DE102013204344A1 (de) Halbleitervorrichtung und Verfahren zum Herstellen selbiger
DE10210903A1 (de) Halbleiterpackungsbauelement geringer Dicke, Verfahren zu seiner Herstellung und zugehörige Elektronikkomponente
DE102008064373B4 (de) Halbleiteranordnung und Verfahren zur Herstellung einer Halbleiteranordnung
DE112006003372T5 (de) Vorrichtung und Verfahren zur Montage eines oben und unten freiliegenden eingehausten Halbleiters
DE102015116152A1 (de) Elektronische Vorrichtung mit Kapselungsstruktur mit verbesserter elektrischer Zugänglichkeit und Verfahren zum Herstellen der elektronischen Vorrichtung
DE102013102230A1 (de) Halbleiterpackages und Verfahren zu deren Ausbildung
DE112022003837T5 (de) Halbleitervorrichtung und herstellungsverfahren
DE10238781A1 (de) Halbleitervorrichtung
DE102016124270A1 (de) Halbleiter-package und verfahren zum fertigen eines halbleiter-package
DE19526511A1 (de) Halbleitervorrichtung und Verfahren zu deren Herstellung und Montage
DE102019127007B4 (de) Stapel elektrischer bauelemente und verfahren zur herstellung desselben
DE69419881T2 (de) Verpackte Halbeiteranordnung und deren Herstellungsverfahren
DE102018130965A1 (de) Gehäuse-in-gehäuse struktur für halbleitervorrichtungen und verfahren zur herstellung
DE102017129924A1 (de) Verkapseltes, anschlussleiterloses Package mit zumindest teilweise freiliegender Innenseitenwand eines Chipträgers
DE4234700A1 (de) Halbleiterkompaktanordnung
DE102015122282A1 (de) Elektronisches Bauteil und Verfahren zu dessen Herstellung

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0023290000

Ipc: H10W0074400000