DE112013007511A5 - Verfahren zur Herstellung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen, Anordnung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen und oberflächenmontierbare Trägervorrichtung - Google Patents

Verfahren zur Herstellung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen, Anordnung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen und oberflächenmontierbare Trägervorrichtung Download PDF

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Publication number
DE112013007511A5
DE112013007511A5 DE112013007511.3T DE112013007511T DE112013007511A5 DE 112013007511 A5 DE112013007511 A5 DE 112013007511A5 DE 112013007511 T DE112013007511 T DE 112013007511T DE 112013007511 A5 DE112013007511 A5 DE 112013007511A5
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DE
Germany
Prior art keywords
surface mount
substrates
disposing
making
substrate
Prior art date
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Granted
Application number
DE112013007511.3T
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English (en)
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DE112013007511B4 (de
Inventor
Choo Kean Lim
Dr. Chang Chee Jia
Choon Keat Or
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of DE112013007511A5 publication Critical patent/DE112013007511A5/de
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Publication of DE112013007511B4 publication Critical patent/DE112013007511B4/de
Active legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
DE112013007511.3T 2013-10-17 2013-10-17 Verfahren zur Herstellung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen, Anordnung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen und oberflächenmontierbare Trägervorrichtung Active DE112013007511B4 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2013/071720 WO2015055247A1 (de) 2013-10-17 2013-10-17 Verfahren zur herstellung einer vielzahl von oberflächenmontierbaren trägervorrichtungen, anordnung einer vielzahl von oberflächenmontierbaren trägervorrichtungen und oberflächenmontierbare trägervorrichtung

Publications (2)

Publication Number Publication Date
DE112013007511A5 true DE112013007511A5 (de) 2016-07-28
DE112013007511B4 DE112013007511B4 (de) 2021-07-22

Family

ID=49448139

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112013007511.3T Active DE112013007511B4 (de) 2013-10-17 2013-10-17 Verfahren zur Herstellung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen, Anordnung einer Vielzahl von oberflächenmontierbaren Trägervorrichtungen und oberflächenmontierbare Trägervorrichtung

Country Status (5)

Country Link
US (1) US9627304B2 (de)
CN (1) CN105612623B (de)
DE (1) DE112013007511B4 (de)
TW (1) TWI557874B (de)
WO (1) WO2015055247A1 (de)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6310298B1 (en) * 1997-12-30 2001-10-30 Intel Corporation Printed circuit board substrate having solder mask-free edges
TWI244186B (en) * 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
DE102005053842B4 (de) * 2005-11-09 2008-02-07 Infineon Technologies Ag Halbleiterbauelement mit Verbindungselementen und Verfahren zur Herstellung desselben
DE102006005994A1 (de) * 2006-02-08 2007-08-16 Infineon Technologies Ag Halbleiterbauteil mit einem Halbleiterchip und Verfahren zur Herstellung derartiger Halbleiterbauteile
TW200921879A (en) * 2007-11-15 2009-05-16 Bridge Semiconductor Corp Manufacturing method of light emitting diode package substrate
GB0807485D0 (en) 2008-04-24 2008-06-04 Welding Inst Method of applying a bump to a substrate
US8080827B2 (en) * 2008-07-31 2011-12-20 Bridgelux, Inc. Top contact LED thermal management
US8598030B2 (en) 2010-08-12 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making conductive post with footing profile

Also Published As

Publication number Publication date
CN105612623A (zh) 2016-05-25
TW201519407A (zh) 2015-05-16
US20160268186A1 (en) 2016-09-15
TWI557874B (zh) 2016-11-11
CN105612623B (zh) 2018-05-08
DE112013007511B4 (de) 2021-07-22
WO2015055247A1 (de) 2015-04-23
US9627304B2 (en) 2017-04-18

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