DE112011105995B4 - Manufacturing process for a non-planar all-round gate circuit - Google Patents

Abstract

A method (200) for forming a semiconductor device comprising: providing (202) a substrate having a surface having a first lattice constant and a fin formed on the surface of the substrate; said fin comprises alternating layers of a semiconductor material having a second lattice constant and a sacrificial material having a third lattice constant, the second lattice constant being different from the first lattice constant and the third lattice constant; forming (204) a sacrificial gate electrode over a channel region of the fin; Forming (206) a pair of sidewall spacers on opposite sides of said sacrificial gate electrode with a sacrificial portion of the fin protruding from each of said sidewall spacers; removing (208) the sacrificial portion of the fin to expose the source and drain regions of the substrate ; Forming (210) embedded epitaxial source and drain regions on said source and drain regions of the substrate, said embedded epitaxial source and drain regions being coupled to the fin and having a fourth lattice constant that is different from of the first lattice constant; Ent removing (212) said sacrificial gate electrode to expose the channel region of the fin; removing (214) the sacrificial material between the layers of semiconductor material in the channel region of the fin to form a plurality of channel nanowires, said plurality of channel nanowires including a lowermost channel nanowire; application (218) a gate dielectric layer encircling all of the channel nanowires and depositing (220) a gate electrode on the dielectric layer and which completely encircles all of the channel nanowires.

Description

BACKGROUND

TECHNICAL AREA

The embodiments of this invention relate to the field of semiconductor components and in particular to a non-planar all-round gate circuit and its production method.

DESCRIPTION OF RELATED ART

Semiconductor manufacturers continue to shrink the structure size of transistors in order to achieve higher packing density and higher performance. There is a need to increase transistor currents while reducing short-channel effects such as parasitic capacitance and blocking shunts for the next generation devices. One way to increase transistor currents is to use more flexible semiconductor materials to form the channel. The higher carrier mobility in the channel supports higher transistor currents. Carrier mobility is a measure of the speed at which carriers flow in semiconductor materials under an electrical field of an external component. Process-induced stress (also known as stress) on the semiconductor body is another way of increasing the driver currents. The induction of stress on the semiconductor body increases the mobility of the carrier and thus the driver currents in the transistors.

Non-planar transistors, such as the tri-gate transistor, are a new development in semiconductor manufacturing for controlling short-channel effects. In tri-gate transistors, the gate borders on three sides of the channel area. Since the gate structure encloses the fin on three surfaces, the transistor basically has three gates that control the current flow through the fin or the channel area. These three gates enable more extensive discharge in the fin and lead to fewer short-channel effects due to the steeper sub-threshold current oscillations and smaller drain-induced threshold reductions. Unfortunately, the fourth side, the lower part of the channel, is far from the gate electrode and is therefore not closely controlled by the gate. As the size of the transistors is continuously reduced to below 20-25 nm technology nodes, parasitic shunt paths between the source and the drains become problematic for tri-gate transistors.

US 2011/0 062 417 A1 , US 2011/0 163 355 A1 , WO 2011/119 717 A1 and US 2010/0 297 816 A1 also disclose semiconductor devices and manufacturing processes therefor.

SUMMARY OF THE INVENTION

The invention is defined in the independent claims. Advantageous refinements are specified in the dependent claims.

Figure list

• Die 1A bis 1D ein nicht-planares Gate-Rundum-Bauelement mit eingebetteten epitaktischen Source und Drain-Bereichen gemäß einer Ausführungsform der vorliegenden Erfindung illustrieren.
• 1E ist eine Illustration eines nicht-planaren Gate-Rundum-Bauelements ohne integrierte Source und Drain-Bereiche.
• 2 ist ein Flussdiagramm, das die Schritte eines Verfahrens zum Aufbau eines nicht-planaren Gate-Rundum-Bauelements gemäß einer Ausführungsform der vorliegenden Erfindung zeigt.
• Die 3A bis 3M zeigen die dreidimensionalen und zweidimensionalen Ansichten, die Schritte eines Verfahrens zum Aufbau eines nicht-planaren Gate-Rundum-Bauelements gemäß einer Ausführungsform der vorliegenden Erfindung darstellen.
• 4 zeigt ein Rechenelement 400 gemäß einer Implementierung dieser Erfindung.

The various embodiments of the present invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which:

• The 1A to 1D illustrate a non-planar all-round gate device with embedded epitaxial source and drain regions according to an embodiment of the present invention.
• 1E is an illustration of a non-planar all-around gate device with no integrated source and drain regions.
• 2nd FIG. 14 is a flowchart showing the steps of a method of building a non-planar all-around gate device according to an embodiment of the present invention.
• The 3A to 3M Figure 3 shows the three-dimensional and two-dimensional views illustrating steps of a method of building a non-planar all-round gate device according to an embodiment of the present invention.
• 4th shows a computing element 400 according to an implementation of this invention.

DETAILED DESCRIPTION

The present invention is a novel all-round gate transistor and manufacturing method. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can operate without some of these specific details. In other instances, well-known semiconductor processing methods and features have not been specifically described in detail so as not to unnecessarily obscure the present invention. References in this specification to "one embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the occurrence of the expression "in one embodiment" at different points in the description does not always necessarily refer to the same Embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment can be combined anywhere with a second embodiment, the two embodiments are not mutually exclusive.

The embodiments of the present invention include a non-planar wrap-around transistor with channel nanowires wrapped all around by a dielectric gate layer and a gate electrode. The gate electrode completely surrounding the channel nanowires increases gate control and results with improved short channel effects because parasitic shunt paths are completely cut off. The channel nanowires are located between the source and drain regions. In one or more embodiments of the present invention, the channel nanowires are made of undoped germanium and the lattice is stressed uniaxially. The undoped germanium offers higher carrier mobility than conventional silicon and the uniaxial stress on the grid further increases the carrier mobility of the channel nanowires, whereby very high transistor currents are achieved. In one embodiment of the present invention, the source and drain regions are formed by etching off a fin adjoining the channel nanowires, and then the “embedded epitaxial” source and drain regions are formed by epitaxial growth of a semiconductor material from the substrate. Embedded epitaxial source and drain regions provide either additional energy or anchors for the channel nanowires, which support the elevation or maintenance, or the elevation and maintenance, of the uniaxial loading of the grid. In addition, in one embodiment of the present invention, the all-around gate transistor includes a bottom gate insulating layer formed between the substrate and the lower channel nanowire so that the gate electrode is completely formed around the lower channel nanowire without capacitive coupling to the substrate can. One or more embodiments of the present invention include a non-planar wrap-around transistor with one of the embedded source and drain epitaxial regions or an insulating layer on the lower gate formed between the substrate and the lower channel nanowire, or both.

1A to 1D illustrate a non-planar all-round gate device 100 according to an embodiment of the present invention. 1A is a three-dimensional view from above / from the component side 100 inside the dielectric layer 101 , 1B is a cross section of the integrated epitaxial source 106 and drain 107 , and 1C is a cross section through the gate electrode 118 . 1D is a three-dimensional view from above / from the component side 100 without the dielectric layer 101 . Component 100 contains a substrate 102 with a top 104 . The epitaxial source area 106 and the drain area 107 are on the top 104 of the substrate 102 and the channel nanowires 110 are between the embedded epitaxial source area 106 and the drain area 107 coupled. The integrated epitaxial source area 106 and the drain area 107 can be summarized as an integrated epitaxial source / drain pair. A gate dielectric layer 116 is on and around every channel nanowire 110 formed, except for the ends of the channel nanowires 110 where the channel nanowires 110 to the embedded epitaxial source area 106 and drain area 107 be coupled. A gate electrode 118 is on the dielectric layer 116 formed and encloses each channel nanowire 110 Completely.

In one embodiment, the surface include 104 of the substrate 102 , the embedded source 106 and drain areas 107 , as well as the channel nanowires 110 one material each with a lattice constant. The lattice constant of the surface 104 differs from the lattice constants of the embedded epitaxial source 106 and drain areas 107 as well as the channel nanowires 110 . In a particular embodiment, the lattice constants of the embedded epitaxial source 106 and drain areas 107 as well as the channel nanowires 110 larger than the lattice constant of the surface 104 . In such an embodiment, the surface exists 104 of the substrate 102 made of silicon germanium, the channel nanowires 110 made of undoped germanium and the integrated epitaxial source area 106 and drain area 107 made of germanium. The lattice mismatch (eg the mismatch of the lattice constant) between the embedded epitaxial source region 106 and drain area 107 , the channel nanowires 110 and the surface 104 leads to grid loading on the channel nanowires 110 and the embedded epitaxial source 106 and drain areas 107 . In one embodiment, the grids of the channel nanowires 110 and the integrated epitaxial source area 106 and drain area 107 uniaxial in a direction parallel to length 120 of the channel nanowires 110 claimed and the grids in a perpendicular direction to length 120 of the nanowires 110 relieved. The lattice mismatch between the surface 104 and the embedded epitaxial source 106 and drain areas 107 In one embodiment, the embedded epitaxial source and drain regions also result 107 an energy for the channel nanowires 110 deliver. The energy can maintain the uniaxial Grid loading of the channel nanowires 110 support.

In one embodiment, the channel nanowires 110 comprise a single crystalline material that has greater carrier mobility than bulk crystalline silicon. The greater mobility of the carrier enables the component 100 to achieve higher driver currents and greater performance. In a particular embodiment, the channel nanowires are made 110 made of undoped germanium (Ge). The lack of dopants minimizes the scattering of charge carriers and helps maximize the carrier mobility of the channel nanowires 110 .

As in 1A and 1B shown, the embedded epitaxial source-106 and drain regions 107 in one embodiment of the present invention in a source / drain trench 108 be applied, the surface 104 of the substrate 102 under the surface of the shallow trench isolation layer 105 is spared. Training the Embedded Source 106 and drain area 107 in the source / drain trench 108 supports inclusion of growth of embedded epitaxial source 106 and drain areas 107 . The embedded source 106 and drain areas 107 do not necessarily have to be formed in a trench and can be on the surface 104 of the substrate 102 located planar to or above the isolation area 103 located. Integrated epitaxial source-106 and drain areas 107 can be <111> faceted, with the width 122 is larger than the width at the bottom 124 at the top of the embedded epitaxial source 106 and drain areas 107 . In such an embodiment, that is the side walls 126 and 128 corresponding area is the <111> lattice orientation of the embedded epitaxial source-106 and drain regions 107 .

In one embodiment, device contains 100 a lower gate insulation 114 that on the surface 104 of the substrate 102 and under the lowest channel nanowire 115 is appropriate. The lower gate insulation 114 serves as a capacitive insulation barrier to avoid parasitic coupling of the surface 104 of the substrate 102 through the gate electrode 118 . How the bottom gate insulation works 114 as a capacitive insulation barrier depends on the material from which it is formed and its thickness. In one embodiment, the bottom gate insulation is provided 114 of any dielectric material (silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric materials, etc.) that cause the parasitic coupling of the surface 104 of the substrate 102 through the gate electrode 118 prevent. In a specific embodiment, the bottom gate insulation is provided 114 from a silicon oxide layer. In one embodiment, the thickness of the bottom gate insulation is sufficient to isolate the surface 104 of the substrate 102 against capacitive coupling through the gate electrode 118 . In a particular embodiment, the bottom gate insulation is 114 between 100-300Å strong. The lower gate insulation 114 enables the lowest channel nanowire 115 completely around the gate electrode 118 to wrap. If the bottom gate insulation 114 the lower channel nanowire would not have been present 115 controlled by a tri-gate or similar structure to provide capacitive coupling between the gate electrode 118 and the surface 104 of the substrate 102 to avoid and to avoid that an undesired conductive channel is formed in the substrate when the component is “switched on”.

In one embodiment of the present invention, substrate 102 comprise one or more epitaxial single-crystalline semiconductor layers (e.g. silicon, germanium, silicon germanium, gallium arsenide, indium phosphide, indium gallium arsenide, aluminum gallium arsenide etc.) which grow on a specific crystalline substrate (silicon, germanium, gallium arsenide, sapphire etc.) to grow. In such an embodiment, the epitaxially grown semiconductor layers are one or more buffer layers 109 whose lattice constants differ from that of the individual crystalline substrate. The buffer layers 109 can do this, the lattice constant from the individual crystalline substrate to the surface 104 to let it grow. For example, substrate 102 epitaxially grown silicon germanium (SiGe) buffer layers 109 on an individual crystalline silicon substrate. The germanium concentration of the SiGe buffer layers 109 can increase from 30% germanium in the bottom buffer layer to 70% germanium in the top buffer layer, the lattice constant is gradually increased.

Shallow ditch areas (STI) 103 can in one embodiment on substrate 102 being constructed. The shallow ditch areas (STI) 103 serve to reduce current leakage between the components 100 that are formed adjacent to each other. A trench layer (STI) 105 can in the STI areas 103 to be available. The STI layer 105 may include any well-known dielectric material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric material, or any combination thereof.

As in 1B shown, the channel nanowires over the surface 104 of the substrate 102 and between the embedded epitaxial source 106 and drain areas 107 educated. The channel nanowires 110 can from any known Materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, InP, and carbon nanotubes are formed. The channel nanowires 110 can be made from any known material that can be reversed from an insulating to a conductive state by applying external electrical fields. Ideally, in one embodiment, the channel nanowires are used to achieve higher device performance 110 formed from an undoped single-crystal semiconductor material with a lattice load, the carrier mobility of which is higher than that of the single-crystal silicon. As already explained above, the lack of dopants minimizes the scattering of charge carriers and supports the maximization of the carrier mobility and thus increases the driver current. The lattice load in the channel nanowires 110 increases carrier mobility and improves device performance. Usually are channel nanowires 110 compressively stressed to increase hole mobility in P-type transistor elements and in N-type transistors to achieve increased electron mobility. In one embodiment, the grids of the channel nanowires 110 uniaxial in a direction parallel to length 120 of the channel nanowires 110 claimed and the grids in a perpendicular direction to length 120 of the nanowires 110 relieved. In a further embodiment, the channel nanowires 110 be doped single-crystalline semiconductor material. For example, the channel nanowires 110 be formed from doped single-crystalline silicon. If the channel nanowires 110 are normally doped to a P-type conductivity when an NMOS transistor element is formed, and to an N-type conductivity when a PMOS transistor element is formed.

As in 1B can channel nanowires 110 parallel to the surface 104 run and a vertical array of channel nanowires 110 form. In one embodiment, the number of channel nanowires lies between the embedded epitaxial source 106 and drain areas 107 between 3 and 6. A higher number of channel nanowires 110 allow the conduction of a stronger driver current through the device 100 . The channel nanowires 110 have strength 130 , Width 132 and length 120 . In one embodiment of the present invention, the strength is 130 between about 5-30 nm, the width 132 between about 5-50 nm and the length 120 is between 10-100 nm. In one embodiment, the nanowires 110 nanowires shaped as loops, their width 132 is greater than the strength 130 of the channel nanowires. In another embodiment, the average of the channel nanowires can 110 be circular or oval instead of square. The length 120 the channel nanowires essentially defines the length of the gate (Lg) of the transistor element 100 . The effective "width" of the gate (Wg) of a channel nanowire 110 is the size of the channel nanowire 110 . The effective “width” of the channel nanowire gate 110 For example, in the case of a channel nanowire with a square cross section, the sum is twice the width 132 and double the strength 130 of the channel nanowire 110 . The effective "width" of the gate (Wg) of a transistor element 100 is the sum of the sizes of the channel nanowires 110 .

As in 1B are shown, the embedded epitaxial source 106 and drain areas 107 at opposite ends of the channel nanowires 110 formed and are made with the channel nanowires 110 coupled. The embedded epitaxial source 106 and drain areas 107 can be formed from all known materials that have a lattice constant. Ideally, the embedded source 106 and drain areas 107 formed from an epitaxially grown single crystal semiconductor such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In one embodiment, the embedded epitaxial source 106 and drain areas 107 formed from a single crystalline semiconductor material with a lattice constant from the surface 104 of the substrate 102 deviates. As described above, the mismatch of the lattice constant between the embedded epitaxial source 106 and drain areas 107 and the surface 104 of the substrate 102 a lattice load in the embedded epitaxial source 106 and drain areas 107 and thus improves the electron mobility and the performance of the transistor. In one embodiment, the embedded epitaxial source 106 and drain areas 107 uniaxial in a direction parallel to length 120 claimed, but the grids become longitudinal in a perpendicular direction 120 relieved. The mismatch of the lattice constant between the embedded epitaxial source 106 and drain areas 107 and the surface 104 of the substrate 102 also causes the embedded epitaxial source 106 and drain areas 107 a force on the channel nanowires 110 exercise, thereby maintaining the lattice stress in the channel nanowires 110 can be supported. In one embodiment, the embedded epitaxial source 106 and drain areas 107 formed from the same single crystalline semiconductor material used to form the channel nanowires 110 is used.

In a particular embodiment, the lattice constant of the embedded epitaxial source is 106 and drain areas 107 larger than the lattice constant of the surface 104 of the substrate 102 . In such an embodiment, the embedded epitaxial source 106 and Drain areas 107 pressurized and deliver a compressive force on the channel nanowires 110 . In a specific embodiment, the embedded epitaxial source 106 and drain areas 107 made of epitaxial monocrystalline germanium and the surface 104 of the substrate 102 formed from epitaxial single-crystal silicon germanium. The germanium source 106 and drain areas 107 exert a pressure force on the channel nanowire 110 out. In one embodiment, the surface 104 of the semiconductor substrate 102 are formed from a semiconductor material (eg silicon germanium) which has a first lattice constant, and the channel nanowires 110 formed from a second semiconductor material (eg germanium), which has a second lattice constant that is greater than the first lattice constant; and the embedded epitaxial source 106 and drain areas 107 can be formed from a third semiconductor material (eg gallium arsenide (GaAs)) that has a third lattice constant that is greater than the lattice constant of the channel nanowires 110 (second lattice constant) and the compressive stress in the channel nanowires 110 can further increase.

In a further embodiment, the lattice constant of the embedded epitaxial source 106 and drain areas 107 smaller than the lattice constant of the surface 104 of the substrate 102 . In such an embodiment, the embedded epitaxial source 106 and drain areas 107 tensile and deliver a tensile force to the channel nanowires 110 . In one embodiment, the surface 104 of the semiconductor substrate 102 from a single-crystalline semiconductor material that has a first lattice constant, and the channel nanowires 110 a second semiconductor material that has a second lattice constant and the embedded epitaxial source 106 and drain areas 107 can be formed from a third semiconductor material that has a third lattice constant that is less than the lattice constant of the channel nanowires 110 (second lattice constant) in order to further increase the tensile force in the channel nanowires.

Normally, the embedded epitaxial source 106 and drain areas 107 formed into an N-type conductivity type when forming an NMOS transistor and formed into a P-type conductivity type when forming a PMOS transistor. In one embodiment of the present invention, the embedded epitaxial source 106 and drain areas 107 a doping concentration between 1E18 atoms / cm3 and 1E21 atoms / cm3. The embedded epitaxial source 106 and drain areas 107 can be formed with a uniform concentration or include partial areas of the different concentrations or dopant profiles. In one embodiment, in which the component 100 is formed as a symmetrical transistor, the embedded epitaxial source 106 and drain areas 107 the same doping concentration and the same profile. In a further embodiment, in which the component 100 is formed as an asymmetrical transistor, the doping concentration profile of the embedded epitaxial source 106 and drain areas 107 vary to achieve certain electrical characteristics, as is well known in the art.

The source 106 and drain areas 107 are considered to be "integrated epitaxial" source and drain regions because, as will be explained in more detail below, they are removed by removing parts of the channel nanowires used to create them 110 used fin and the subsequent growth of the source and drain pair are formed. For example, in one embodiment, the parts of the fin that are used to build up the claimed channel nanowires 110 were removed, and then the source and drain pair from the surface 104 of the substrate 102 bred. The lattice of the epitaxially deposited source and drain pair settles on the lattice of the surface 104 of the substrate. That is, the lattice of the underlying substrate changes the lattice direction and growth of the overlying embedded epitaxial source 106 and drain areas 107 dictates. The use of the embedded epitaxial source 106 and drain areas 107 improves device performance by providing additional force to the channel nanowires and by providing anchors to the channel nanowires to maintain uniaxial stress on the channel nanowires 110 that already exists from previous processes, such as the transfer of structural information from the Finn. The embedded epitaxial source and drain regions are stressed and therefore further stress the adjacent nanowire channels. The load on the channel nanowires can be further increased by using a semiconductor material with a different constant than the semiconductor material used to form the channel nanowires.

Furthermore, although the semiconductor device 100 ideally integrated epitaxial source 106 and drain areas 107 to increase the stress on the channel nanowires 110 the embodiments do not necessarily include integrated epitaxial source and drain regions. In one embodiment of the present invention, as in 1E shown, a transistor 150 a source 156 and drain area 157 , which consists of a fin film stack, which is used to create the uniaxially stressed channel nanowires 110 is used include. For example, the source 156 and drain areas 157 out alternating layers of the semiconductor material 160 and the sacrificial material 170 (e.g. germanium or silicon germanium) and the substrate 102 that is used to form stressed channel nanowires 110 is used. In this the source 156 and drain areas 157 formed from a heterogeneous stack of single-crystalline semiconductor films. The source 156 and drain areas 157 can be doped to a desired conductivity type and a desired conductivity level, as is known in specialist circles. In addition, if desired, increased source and drain regions can be caused by the deposition of additional epitaxial semiconductor material (not shown) on the source 156 and drain areas 157 are formed in order to increase the strength of the source and drain regions and to reduce current crowding and thus to reduce the contact resistance of the component. The transistor 150 includes gate insulation 114 to the gate 118 below the bottom nanowire 115 against capacitive coupling to the substrate 102 to isolate.

As in the 1B and 1C is shown, the dielectric layer 116 on and around all channel nanowires 110 formed around. The gate dielectric layer 116 can be any known gate dielectric layer, such as, but not limited to, SiO2, SiON, and SiN. In one embodiment, the dielectric gate layer is a high-K gate dielectric layer such as a metal oxide dielectric (for example Ta2O5, TiO2, HfO2, HfSiOx, ZrO2 etc.). The gate dielectric layer 116 can also consist of other types of high-K dielectric layers, such as, but not limited to, PZT and BST. The dielectric gate layer can also consist of any combination of the above-mentioned dielectric materials. The gate dielectric layer 116 can be formed with a thickness of about 10 - 60 A. In a specific embodiment, the dielectric gate layer is made 116 made of HfO2 and was formed with a thickness of about 1 - 6 nanometers.

A gate electrode 118 is on the dielectric layer 116 formed and encloses each channel nanowire 110 Completely. The gate electrode 118 runs in a perpendicular direction to length 120 of the channel nanowires 110 . The gate electrode 118 can be formed from a suitable gate electrode material. In one embodiment, the gate electrode 118 a metal gate electrode made of, for example, but not limited to, Ti, TiN, TaN, W, Ru, TiAl and all combinations thereof. In one embodiment, in which the component 100 is an NMOS transistor, the gate electrode 118 from a material with a work function between 3.9 - 4.2 eV. In one embodiment, in which the component 100 is a PMOS transistor, the gate electrode 118 be made of a material with a work function between 4.8 and 5.2 eV. In one embodiment, in which the channel nanowires 110 in the component 100 are undoped or very little doped, the gate electrode 118 can be formed from a material with a mid-gap work function between 4.3-4.7 eV. In a specific embodiment, the gate electrode is made 118 made of TiAl.

Because the gate electrode 118 and the dielectric gate layer 116 every channel nanowire 110 can completely enclose component 100 be a transistor that operates in a completely depleted state in which the channel nanowires when turned on (“ON”) 110 completely deplete, thus offering the beneficial electrical properties and performance of a fully depleted transistor. If the component 100 "ON" is switched in each channel nanowire 110 a space charge zone and an inversion layer are formed on the surface of each channel nanowire. The inversion layer has the same conductivity types as the embedded epitaxial source 106 and drain areas 107 and forms a conductive channel between the embedded epitaxial source 106 and drain areas 107 so that the current can flow between them. The space charge zone depletes the free carriers below the inversion layers. The carriers in each channel nanowire 110 are depleted, except for the inversion layer, so the transistor can be considered a "completely depleted" transistor. Fully depleted transistors have improved electrical performance features over incompletely depleted or partially depleted transistors. If a transistor is operated as a completely depleted transistor, the transistor receives an ideal or very steep sub-threshold gradient. A very steep sub-threshold gradient leads to improved short-channel effects such as improved drain-induced threshold lowering (DIBL).

2nd is a flow chart 200 10 showing the steps of a method of building a non-planar all-round gate device according to an embodiment of the present invention. The 3A to 3M Figure 3 shows the three-dimensional and two-dimensional cross-sections illustrating steps of a method for building a non-planar all-round gate device according to an embodiment of the present invention. The process begins with step 202 in the flowchart 200 by providing a substrate 301 with a fin formed on it 304 . The substrate 301 is the material on which the non-planar gate device is formed. The substrate 301 has a surface 303 with a lattice constant. In one embodiment, the substrate comprises 301 a single crystal layer with a lattice constant. In such an embodiment, the substrate 301 one or more buffer layers 311 include, which are grown between an individual crystalline substrate and the top single crystalline layer. The buffer layers 311 can serve to gradually change the lattice constant from that of the individual crystalline substrate to that of the uppermost single-crystalline layer. The buffer layers 311 can be formed from an epitaxially grown, single-crystalline semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP and InP. The single crystalline substrate on which the buffer layers 311 can be formed, can be any single-crystalline material with a lattice constant (e.g. silicon, germanium, gallium arsenide, sapphire etc.). In a particular embodiment, substrate 301 include epitaxially grown silicon germanium (SiGe) buffer layers on an individual single crystalline silicon substrate. The germanium concentration of the SiGe buffer layers can increase from 30% germanium in the bottom buffer layer to stress-free 70% germanium in the top buffer layer, thereby increasing the lattice constant step by step.

In one embodiment, the fin 304 with alternating layers of a semiconductor material 308 and a sacrificial material 310 educated. The layers of the semiconductor material 308 then become channel nanowires 343 shaped. The layers of sacrificial material 310 induced by a mismatch of the lattice constant to the layers of the semiconductor material 308 a lattice stress on the layers of the semiconductor material 308 . In one embodiment, the layers can be made of semiconductor material 308 and the layers of sacrificial material 310 formed from any known material that has a lattice constant. Ideally, the layers are made of the semiconductor material 308 and the layers of sacrificial material 310 formed from a single-crystalline semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In one embodiment, the layers have the semiconductor material 308 a lattice constant other than the lattice constant of the layers of the sacrificial material 310 and the surface 303 of the substrate 301 . The Finn 304 is due to the mismatch of the grid between the surface 303 , the layers of the semiconductor material 308 and the layers of sacrificial material 310 strained. In a specific embodiment, the layers have the semiconductor material 308 a larger lattice constant than the lattice constant of the layers of the sacrificial material 310 and the surface 303 . The layers of the semiconductor material 308 can, for example, undoped germanium, the surface 303 can silicon germanium with 70% germanium concentration, and the layers of the sacrificial material 310 can be silicon germanium with 70% germanium concentration. For such an embodiment, the lattice mismatch between the materials results in the layers of the semiconductor material 308 in the fin 304 be subjected to pressure. In another embodiment, the layers have the semiconductor material 308 a smaller lattice constant than the lattice constant of the layers of the sacrificial material 310 and the surface 303 . The layers of the semiconductor material 308 can, for example, silicon, the surface 303 can silicon germanium, and the layers of sacrificial material 310 can be silicon germanium. For such an embodiment, the lattice mismatch between the materials results in the layers of the semiconductor material 308 in the fin 304 be stressed. Because the sacrificial material layer 310 and the semiconductor material layer 308 alternate and have different lattice constants, the semiconductor material layers are replaced by the underlying sacrificial material layer 310 claimed biaxially.

The Finn 304 can be formed by first alternating layers of the semiconductor material 308 and the sacrificial material 310 by conventional epitaxial vapor deposition processes evenly on the surface 303 of the substrate 301 be applied. Then the even layers of the semiconductor material 308 and the sacrificial material 310 structured using conventional photolithography and etching processes. In one embodiment of the present invention, the substrate 301 also etched so that the lower part of the fin 304 a substrate portion 309 , as in 3A shown, owns. So that the substrate portion 309 the Finn the lower sacrificial material 310 the Finnish man 304 In one embodiment, the substrate portion 309 the Finnish man 304 thicker than the sacrificial material layers 310 to provide additional space between the substrate and the lowermost channel nanowire so that a lower gate separating film and a gate electrode / gate dielectric can be formed between the substrate and the lower channel nanowires. During the structuring process, the substrate 301 also be structured so that there is a substrate area 312 continuous with fin 304 and the shallow trench isolation area (STI area) 315 forms in one embodiment. The STI area 315 is used to reduce the current leakage between non-planar all-round gate components that are formed adjacent to each other. In one embodiment, at least one to the fin 304 continuous part of the substrate area 312 the buffer layers 311 of the substrate 301 include. In one embodiment, the STI areas 315 with a dielectric STI layer 305 filled. The dielectric STI layer 305 can be any known dielectric layer, such as, but not on limited, include silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric, or any combination thereof. The dielectric STI layer 305 is formed by first using a conventional chemical vapor deposition process a dielectric STI layer 305 on substrate 301 and about Finn 304 is applied evenly. The dielectric STI layer 305 is initially of greater strength than the combined strength of the fin 304 and the substrate area 312 upset. Then the dielectric STI layer 305 planarized using a conventional chemical mechanical planarization process. The dielectric STI layer 305 is then recessed using a conventional etching process to fin 304 to expose as in 3A pictured. In one embodiment, the STI dielectric is under the surface 303 of the substrate 301 sunk so that the lower part of the fin 304 from the substrate 301 is formed as in 3A pictured. In this way Finn includes 304 a substrate portion 309 which is the lower sacrificial material 310 the Finnish man 304 forms. In one embodiment, the substrate portion 309 the Finnish man 304 thicker than the sacrificial material layers 310 to provide additional space between the substrate and the lowermost channel nanowire so that a lower gate separating film and a gate electrode / gate dielectric can be formed between the substrate and the lower channel nanowires. Alternatively, an individual sacrificial layer between the surface 303 and the bottom semiconductor material layer 308 be formed.

The Finn 304 has the side walls 302 and 306 , a height of fins 316 , a width of fins 318 and a fin length 320 . In the formation of fins 304 are the side walls 302 and 306 unlimited levels that of the Finn 304 a grid relaxation in the perpendicular direction to the fin length 320 enable. This means that in the case of fin formation, the above-described two-axially stressed layers are reduced to essentially uniaxially stressed layers. In one embodiment, the fin 304 uniaxial in a direction parallel to the fin length 320 claimed, but the grids become longitudinal in a perpendicular direction 320 relieved. In one embodiment, the fin 304 with a fin width 318 below 30 nm, and ideally below 25 nm. In one embodiment, the fin height is 316 less than the height, whereby integration problems such as the tilting of the fin, profile distortions of the fin and poor uniformity of the critical dimensions of the fin begin to occur. In a particular embodiment, the fin height is 316 between 30 - 75 nm.

The thickness of the layers of the semiconductor material 308 and layers of sacrificial material 310 influence the electrical properties of the channel nanowires 343 and the integration and performance of the device 100 . In one embodiment, the layers are of the semiconductor material 308 sufficiently strong to form channel nanowires 343 to avoid with excessive surface scattering effect and thus high channel resistance and low carrier mobility. The layers of the semiconductor material 308 are therefore sufficiently thin around channel nanowires 343 to form the component 100 allow to work in a completely impoverished manner. The thickness of the layers of sacrificial material 310 affects the subsequent distances between the channel nanowires 343 and thus the ability of the dielectric gate layer 350 and the gate electrode 352 , completely around each channel nanowire 343 to build. In one embodiment, the layers are sacrificial material 310 sufficiently strong so that the dielectric gate layer 350 subsequently completely around the channel nanowires 343 can form and the gate electrode 352 on the dielectric gate layer 350 can form to the channel nanowires 343 completely enclose. The thickness of the layers of the semiconductor material 308 and layers of sacrificial material 310 also affect the fin height 316 . In one embodiment, the layers are of the semiconductor material 308 and the layers of sacrificial material 310 sufficiently thin to be a fin height 316 to achieve which is below the level at which integration problems begin to occur. In a particular embodiment, the layers of semiconductor material 308 are formed in a thickness of about 5 to 50 nm and the layers of the sacrificial material 310 are formed with a thickness of about 5 to 30 nm.

The total number of alternating layers of the semiconductor material 308 and the sacrificial material 310 affect the height of the fins 316 and the drive current capacity of the device. The number of layers of the semiconductor material 308 corresponds to the number of channel nanowires 343 which are then formed. A higher number of channel nanowires 343 enable a higher drive current capacity of the component 100 . Too many layers of the semiconductor material 308 and the sacrificial material 310 however lead to a fin height 316 that cannot be integrated. In one embodiment, the number of layers 308 and 310 sufficiently low for an integrable fin height 316 to achieve. In a particular embodiment, the fin has 304 about 3-6 layers of the semiconductor material 308 and about 3-6 layers of the sacrificial material 310 .

With reference to step 204 in the flowchart 200 and the corresponding 3B and 3C becomes a gate sacrificial electrode 352 over the area 328 the Finnish man 304 educated. The gate sacrificial electrode 352 defines the channel area of the Transistor. The gate sacrificial electrode 352 is achieved by uniformly applying a dielectric gate sacrificial layer 322 to the Finn 304 educated. The dielectric gate sacrificial layer 322 is on the surface and the sidewalls 302 , 306 the Finnish man 304 applied. The dielectric gate sacrificial layer 322 can be applied with a thickness of about 10 - 50 A. As in 3B a gate sacrificial layer is then shown 324 evenly on the dielectric gate sacrificial layer 322 and over the Finn 304 applied. The gate sacrificial layer 324 will be of greater strength than the Finn strength 316 applied. The gate sacrificial layer 324 can be planarized using a conventional chemical mechanical planarization process. As in 3C is shown, then the victim gate 326 by structuring the gate sacrificial layer 324 formed using conventional photolithography and etching processes. The gate sacrificial electrode 326 will over the channel area 328 the Finnish man 304 formed and has a strength 329 which is greater than the height of the fins 316 . The gate sacrificial electrode 326 then serves the channel area 328 the Finnish man 304 during the removal of the victim portions 332 the Finnish man 304 to protect.

During the structuring of the gate sacrificial electrode, the dielectric gate sacrificial layer becomes 322 on the victim shares 332 the Finnish man 304 on the opposite sides of the gate sacrificial electrode 352 exposed. The dielectric gate sacrificial layer 322 serves during the structuring and formation of the gate sacrificial electrode 326 as an etch stop and thus prevents damage to the fin 304 . In one embodiment, the dielectric gate sacrificial layer 322 and the gate sacrificial layer 324 formed from materials with sufficiently different etch selectivity, the dielectric gate sacrificial layer 322 as an etch stop for etching the gate sacrificial layer 324 can serve. In a particular embodiment, the gate dielectric layer is 322 a dielectric layer (eg silicon oxide, silicon nitride and silicon oxynitride) and the gate sacrificial layer 324 is formed from a semiconductor material (eg polysilicon). The dielectric gate sacrificial layer 322 and the gate sacrificial layer 324 can be applied using conventional chemical vapor deposition techniques. Then the dielectric gate sacrificial layer 322 from the surface and the side walls 302 , 306 of the victim's share 332 the Finnish man 304 using a conventional wet etching process to remove the victim portions 332 the Finnish man 304 to expose. In the embodiment in which the dielectric gate sacrificial layer 322 is a silicon oxide layer, the dielectric gate sacrificial layer 322 removed with a diluted HF in a wet etching process.

With reference to step 206 in the flowchart 200 and the corresponding one 3C becomes a pair of sidewall spacers 330 on the opposite side walls 334 the gate sacrificial electrode 326 educated. The pair of sidewall spacers 330 can be formed with the conventional methods known to those skilled in the art for forming selective spacers. In one embodiment, a conformal dielectric spacer layer, such as silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, is first applied uniformly to all structures, including fins 304 and the gate sacrificial electrode 326 applied. The dielectric spacer is applied conformally so that it rests on both vertical surfaces, such as the sidewalls 302 , 306 , 334 , and the horizontal surfaces, such as the surface of the gate sacrificial electrode 326 , is essentially the same strength. The dielectric spacer layer can be applied using conventional chemical vapor deposition processes such as vacuum gas deposition (LPCVD) and plasma-assisted gas phase deposition (PECVD). In one embodiment, the dielectric spacer layer is applied with a thickness between approximately 2 and 10 nanometers. An unstructured, anisotropic etching process is then carried out using conventional anisotropic etching processes, such as reactive ion etching (RIE), on the dielectric spacer layer. During the anisotropic etching process, the majority of the dielectric spacer is removed from the horizontal surfaces, the dielectric spacer remains on the vertical surfaces such as the side walls 334 the gate sacrificial electrode 326 and the side walls 302 , 306 the Finnish man 304 . Because the strength 329 the gate sacrificial electrode 326 is greater than the height of the fins 316 , is the thickness of the remaining dielectric spacer after anisotropic etching on the sidewalls 334 the gate sacrificial electrode 326 larger than on the side walls 302 , 306 the Finnish man 304 . It is this difference in strength that is the selective formation of the sidewall spacers 330 on the side walls 334 the gate sacrificial electrode 326 enables. An unstructured isotropic etching process is then performed to remove the remaining dielectric spacer from the sidewalls 302 , 306 the Finnish man 304 to remove a pair of sidewall spacers 330 remains on the opposite side walls 334 the gate sacrificial electrode 326 . In one embodiment, the isotropic etching process is a wet etching process. In a specific embodiment, in which the spacer layer consists of silicon nitride or silicon oxide, a wet etchant solution comprising phosphoric acid (H3PO4) or a buffered etching oxide (BOE) is used for the isotropic etching process. In an alternative embodiment, the isotropic etching process is a dry etching process. In such an embodiment, NF3 is in the downstream plasma reactor used to isotropically etch the dielectric spacers.

With reference to step 208 in the flowchart 200 and the corresponding one 3D become the victim shares 332 the Finnish man 304 removed to the source / drain area 334 of the substrate 301 to expose. The percentage of victims 332 the Finnish man 304 can be removed using conventional etching methods such as wet etching or plasma dry etching. In one embodiment, wherein the fin 304 alternating layers of germanium 308 and silicon germanium 310 , a wet etch solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) is used to remove the sacrificial portions 332 the Finnish man 304 selectively remove. The channel area 328 the Finnish man 304 is through the victim gate 326 and the pair of sidewall spacers 330 protected from etching. In one embodiment, the surface 303 of the substrate 301 while removing the victim's share 332 the Finnish man 304 recessed to a source / drain trench 336 to build. The source / drain trench 336 serves to accommodate the subsequent growth of the embedded epitaxial source 338 and drain regions 339 . In one embodiment, the source / drain trench 336 formed with a depth between 20 and 40 nm. Alternatively, the victim shares 332 the Finnish man 304 removed so the surface 303 of substrate 301 over or planar to the dielectric STI layer 305 lies.

With reference to step 210 in the flowchart 200 and the corresponding one 3E the embedded epitaxial source 338 and drain areas 339 on the source / drain areas 334 of the substrate 301 educated. In one embodiment, the embedded epitaxial source 338 and drain areas 339 formed with conventional epitaxial deposition processes such as low pressure vapor deposition, gas phase epitaxy and molecular beam epitaxy. In one embodiment, the embedded epitaxial source 338 and drain areas 339 in the source / drain trench 336 . The embedded epitaxial source 338 and drain areas 339 couple to the channel areas 328 the Finnish man 304 and rise above the surface of the dielectric STI layer 305 . The embedded epitaxial source 338 and drain areas 339 can be formed from all known materials that have a lattice constant. Ideally, the embedded source 338 and drain areas 339 formed from an epitaxially grown single crystal semiconductor such as, but not limited to, Si, Ge, SiGe, GeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP and InP. In one embodiment, the embedded epitaxial source 338 and drain areas 339 formed from a single crystal semiconductor material with a lattice constant that is different from the lattice constant of the surface 303 of the substrate 301 deviates. In a particular embodiment, the lattice constant is the embedded epitaxial source 338 and drain regions 339 larger than the lattice constant of the surface 303 of the substrate 301 .

In a specific embodiment, the embedded epitaxial source 338 and drain areas 339 formed from germanium and the surface 303 of the substrate 301 formed from silicon germanium. In one embodiment, the embedded epitaxial source 338 and drain areas 339 formed from the same single-crystalline semiconductor material (eg Ge) that is used to form the channel nanowires. In one embodiment of the present invention, the embedded epitaxial source 338 and drain areas 339 formed from a material (eg GaAs) whose lattice constant is greater than that of the semiconductor material (eg SiGe) on the surface 303 of the substrate 301 and is greater than the lattice constant of the semiconductor material (eg Ge) 308 that is used to form the channel nanowires to further increase the uniaxial lattice stress in the channel nanowires.

In another specific embodiment, the embedded epitaxial source 338 and drain areas 339 formed from silicon and the surface 303 of the substrate 301 formed from silicon germanium. In one embodiment of the present invention, the embedded epitaxial source 338 and drain areas 339 formed from the same single-crystalline semiconductor material (eg Si) that is used to form the channel nanowires. In one embodiment of the present invention, the embedded epitaxial source 338 and drain areas 339 formed from a material (eg silicon carbide or silicon doped with carbon) whose lattice constant is smaller than that of the semiconductor material (eg SiGe) on the surface 303 of the substrate 301 and is less than the lattice constant of the semiconductor material (eg Si) 308 that is used to form the channel nanowires to further increase the uniaxial tensile stress in the channel nanowires.

The mismatch of the lattice constant between the embedded epitaxial source 338 and drain areas 339 and the surface 303 of the substrate 301 creates a grid load, with the embedded epitaxial source 338 and drain areas 339 uniaxial in a direction parallel to the length 320 the Finnish man 304 be stressed on the grid. The integrated epitaxial source 338 and drain areas 339 become perpendicular to length in one direction 329 the Finnish man 304 relieved of the grid, since the to the side walls 335 and 337 associated areas during the formation of the embedded epitaxial source 338 and drain areas 339 remain unused. The mismatch of the lattice constant also ensures that the embedded epitaxial source 338 and drain areas 339 a force on the canal area 328 the Finnish man 304 exercise. Because the layers of the semiconductor material 308 in the channel area 328 the Finnish man 304 then the channel nanowires 343 form, practice the embedded epitaxial source 338 and drain areas 339 then a force on the channel nanowires 343 from maintaining lattice stress in the channel nanowires 343 can support. In one embodiment, the lattice constant of the embedded epitaxial source is 338 and drain areas 339 larger than the lattice constant of the surface 303 of the substrate 301 . In such an embodiment, the embedded epitaxial source 338 and drain areas 339 pressurized and deliver a compressive force on the channel nanowires 343 . In one embodiment, the lattice constant of the embedded epitaxial source is 338 and drain areas 339 smaller than the lattice constant of the surface 303 of the substrate 301 . In such an embodiment, the embedded epitaxial source 338 and drain areas 339 tensile and deliver a tensile force to the channel nanowires 343 .

In general, in one embodiment, during the structuring of a stack of layers forming nanowires and sacrificial layers therebetween, a first uniaxial stress is built up along the channel regions of the layers forming nanowires. The embedded source and drain regions are then formed by etching away the outer portions of the fin and then forming the epitaxial source and drain regions in their place. In such an embodiment, the embedded epitaxial source and drain regions are grown from a crystalline surface of a substrate below the fin. If the removed outer parts with the alternating layers forming nanowires are heterogeneous and the intermediate sacrificial layers are composed differently, the replacement with embedded source and drain regions by epitaxial growth replaces the heterogeneous parts by homogeneously composed regions. Thus a new lattice mismatch is added on both sides of the etched fin. The embedded epitaxial source and drain areas further increase the uniaxial stress on the layers that already form the nanowires. In addition, after the subsequent sacrificial layers have been removed, the embedded epitaxial source and drain regions act as anchors for the discrete nanowires then formed. Since the embedded epitaxial source and drain regions are epitaxially grown from the underlying substrate, the anchoring is effective for maintaining the first uniaxial stresses formed along the channel regions of the nanowires during the structuring of the fin. The embedded epitaxial source and drain areas maintain and increase the uniaxial stress on the nanowire channel parts that are finally formed. It should be noted that the above-described replacement of the heterogeneous layers by a homogeneous layer can also be carried out with the same material as used for the layers forming the nanowire. In another embodiment, however, to further increase the uniaxial stress, a different material than all materials used in the heterogeneous layer stack can be epitaxially grown in order to form the embedded epitaxial source and drain regions. For example, in one embodiment, the epitaxial source and drain regions are formed from a material with a higher lattice constant than all materials in the heterogeneous fin. In this embodiment, a uniaxial compressive stress is further increased in the nanowire channel parts that are finally formed. In another embodiment, the epitaxial source and drain regions are formed from a material with a smaller lattice constant than all materials in the heterogeneous fin. In this embodiment, a uniaxial tensile stress in the finally formed nanowire channel parts is further increased.

In one embodiment, the surface is 303 of the source / drain regions 334 of the substrate 301 a single crystalline material with a <100> orientation that acts as a seed layer for the epitaxial growth of the embedded epitaxial source-338 and drain regions 339 serves. The embedded source 338 and drain areas 339 so grow in a <100> direction. The side walls 335 and 337 belonging <111> surface can be formed during the formation of the embedded epitaxial source 338 and drain areas 339 grow at a more favorable pace and cause the embedded epitaxial source 338 and drain areas 339 <11 1> are faceted.

It must be recognized that this is not required, although it is desirable to use the embedded epitaxial source 338 and drain areas 339 by etching away the percentage of victims 332 the Finnish man 304 and then epitaxially growing to form the source and drain regions, as in FIGS 3D and 3D shown to increase the stress on the channel nanowires. In an alternative embodiment, the victim shares 332 the Finnish man 304 not etched away, but retained to form the source and drain regions for the component, as in 1E shown. The victim shares 332 the Finnish man 304 can too doped by known techniques such as ion implantation to form the source and drain regions of a desired conductivity type and concentration levels. In addition, an epitaxial semiconductor film can be on the surface and sidewalls of the victim portions 334 the Finnish man 304 are grown to form raised source and drain regions to reduce current crowding.

Then, referring to 3F , an interlayer dielectric layer (ILD) 340 evenly applied to all structures, including the raised source 338 and drain areas 339 , the gate sacrificial electrode 326 and the pair of sidewall spacers 334 . The dielectric spacer 340 can be applied with conventional chemical vapor deposition processes (e.g. vacuum gas deposition (LPCVD) and plasma-assisted gas phase deposition (PECVD)). In one embodiment, the ILD layer 340 formed from any known dielectric material such as, and not limited to, undoped silicon oxide, doped silicon oxide (eg BPSG, PSG), silicon nitride and silicon oxynitride. The ILD layer 340 is then processed with a conventional chemical mechanical planarization process around the top of the gate sacrificial electrode 326 and the top of the pair of sidewall spacers 334 to expose.

With reference to step 212 in the flowchart 200 and the corresponding 3G and 3H becomes the gate sacrificial electrode 326 removed to the channel area 328 the Finnish man 304 to expose. 3H is the corresponding two-dimensional cross section of the 3H . The ILD layer 340 protects the embedded source 338 and drain areas 339 during removal of the sacrificial gate electrode 326 . The gate sacrificial electrode 326 can be removed using conventional etching methods such as wet etching or plasma dry etching. In one embodiment, in which the gate sacrificial electrode 326 made of polysilicon and the ILD layer 340 Made of silicon oxide, a wet etching solution such as TMAH can be used to selectively remove the sacrificial gate electrode 326 be used. The dielectric gate sacrificial layer 322 on the canal area 328 the Finnish man 304 serves as an etch stop and protects the channel area 328 the Finnish man 304 during removal of the sacrificial gate electrode 326 . Then the dielectric gate sacrificial layer 322 using a conventional etching process to remove the channel area 328 the Finnish man 304 before step 214 in the flowchart 200 to expose. In the embodiment in which the dielectric gate sacrificial layer 322 is a silicon oxide layer, the dielectric gate sacrificial layer 322 removed with a diluted HF in a wet etching process.

With reference to step 214 in the flowchart 200 and the corresponding one 31 become the layers of sacrificial material 310 between the layers of the semiconductor material 308 in the channel area 328 the Finnish man 304 to form the channel nanowires 343 away. The layers of sacrificial material 310 can with all known etchants that selectively on the layers of the semiconductor material 308 act, be removed, the etchant the layers of the sacrificial material 310 at a much faster pace than the layers of semiconductor material 308 etches. In one embodiment, the etchant etches the layers of the semiconductor material 308 selective while the layers of sacrificial material 310 not be etched. In one embodiment, in which the layers of the semiconductor material 308 made of germanium and the layers of sacrificial material 310 The layers of the sacrificial material can consist of silicon germanium 310 with a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. In one embodiment, in which the layers of the semiconductor material 308 made of silicon and the layers of sacrificial material 310 The layers of the sacrificial material can consist of silicon germanium 310 with a wet etchant such as, but not limited to, aqueous carboxylic acid / nitric acid / HF solution and aqueous citric acid / nitric acid / HF solution. Removing layers of sacrificial material 310 leaves voids 342 between the layers of the semiconductor material 308 . The cavities 342 between the layers of the semiconductor material 308 are between about 5 and 30 nm thick. The remaining layers of the semiconductor material 310 form a vertical array of channel nanowires 343 that with the embedded epitaxial source 338 and drain areas 339 be coupled. The channel nanowires formed 343 are between about 5 and 50 nm thick. The channel nanowires 343 run parallel to the surface 303 and are aligned to form a single column of channel nanowires 343 with a bottom channel nanowire 344 to form at the bottom of the column.

In one embodiment, as in 31 the entire sacrificial material is shown 310 between the embedded epitaxial source and drain regions, including the portions below the sidewall spacers 330 , away. Etching off the portions between the spacers simplifies manufacture because the sacrificial material is removed 310 can be based on the selectivity of the etching with respect to the sacrificial material and the embedded epitaxial source and drain regions and thus an overetching can be used to remove the sacrificial material. The removal of the sacrificial material 310 below the spacers 330 however, can result in a slightly enlarged opening between the spacer 330 over the top channel nanowire 343 to lead. This can lead to the gate electrode subsequently formed having a somewhat longer gate length between the channel nanowires compared to the gate length over the uppermost channel nanowire. In one embodiment, time is etched so that part of the sacrificial material 310 that is adjacent to the embedded source and drain regions after etching the sacrificial material 310 between the spacers 330 remains to the channel nanowires 343 to build. In this way, the gate electrode subsequently formed can have the same gate length on all surfaces of the channel nanowires.

With reference to step 216 in the flowchart 200 and the corresponding 3y and 3K becomes a lower gate insulation 348 on the surface 303 of the substrate 301 and under the lowest channel nanowire 344 educated. The lower gate insulation 348 is first formed by a dielectric layer 346 evenly around and over the channel nanowires 343 is applied as in 3y shown. The dielectric layer 346 fills the cavities 342 between the channel nanowires 343 , including the area between the lowest channel nanowire 344 and the surface 303 of the substrate 301 , completely out. The dielectric layer 346 also forms the surface of the ILD layer 340 . In one embodiment, the dielectric layer 346 formed from any known dielectric material such as, but not limited to, silicon oxide, silicon oxide, silicon nitride and silicon oxynitride. In a specific embodiment, the dielectric layer 346 formed from silicon oxide. Ideally, the dielectric layer 346 applied using a highly compliant application process such as low pressure vapor deposition (LPCVD), ALD technologies or a spin coating process to ensure that the voids 342 between the channel nanowires 343 are completely filled out. Then, as in 3K shown the dielectric layer 346 recessed from top to bottom using a conventional isotopic dielectric etching process. In a particular embodiment, in which the dielectric layer 346 consists of silicon oxide, a time-shifted HF wet etching process is used to cut out the dielectric layer. During the recess of the dielectric layer 346 becomes the major part of the dielectric layer 346 removed, a thin layer remains on the surface 303 of the substrate 301 and under the lowest channel nanowire 344 which is the bottom gate insulation 348 forms, back. The thickness of the bottom gate insulation 348 depends on the length of time in which the dielectric layer 346 is spared. In one embodiment, the recess is long enough to achieve a thickness of the bottom gate insulation that is sufficiently thick to cover the surface 303 of the substrate 301 against capacitive coupling through the gate electrode 352 to isolate. In one embodiment, the recess is made over a sufficiently long period of time to achieve a thickness of the lower gate insulation that is sufficiently thin that the void between the lowermost channel nanowire 344 and the bottom gate insulation 348 is large enough for the dielectric gate layer 350 can completely enclose the lowest channel nanowire and the gate electrode 352 the lowest channel nanowire 344 can form. In one embodiment, the thickness formed is the bottom gate insulation 348 sufficiently strong to the surface 303 of the substrate 301 against capacitive coupling through the gate electrode 352 to protect and thin enough to allow the dielectric gate layer 350 and the gate electrode 352 the lowest channel nanowire 344 can completely enclose. In a particular embodiment, the thickness of the bottom gate insulation is 348 between about 100-300A.

Referring to the steps 218 and 220 of the flowchart 200 and the corresponding 3L and 3M , becomes a gate dielectric layer 350 around each channel nanowire 343 formed and a gate electrode 352 on the dielectric gate layer 350 formed that all channel nanowires 343 encloses. 3M is the corresponding three-dimensional cross section of 3L . The gate dielectric layer 350 can be formed from all known gate dielectric materials as described above. The gate dielectric layer 350 is formed using a highly compliant application process such as an ALD process to ensure that the dielectric gate layer has a uniform thickness around each channel nanowire 343 having. In a specific embodiment, the dielectric gate layer consists of HfO2 and is applied with a thickness of 1 to 6 nanometers. The gate dielectric layer 350 is applied evenly and also forms the surface of the ILD layer 340 . Then a gate electrode is evenly placed on the dielectric gate layer 350 applied to the gate electrode 352 to build. The gate electrode 352 can be formed from any known gate electrode material as described above. The gate electrode material is applied using a conformal application process, such as an ALD process, to ensure that the gate electrode 352 on the dielectric gate layer 350 as well as all around and between all channel nanowires 343 is applied. The even on the surface of the ILD layer 340 applied electrode material and dielectric gate layer 350 are then planarized chemically and mechanically until the Surface of the ILD layer 340 as in the 3L and 3M shown, exposed. The resulting device 300 that with the one in the flowchart 200 described method is a non-planar all-round gate device according to an embodiment of the present invention.

4th shows a computing element 400 according to an implementation of this invention. The computing element 400 houses a printed circuit board 402 . The circuit board 402 can be a number of components, including and not limited to a processor 404 and at least one communication chip 406 , include. The processor 404 is physical and electrical with the circuit board 402 coupled. In some implementations there is at least one communication chip 406 also physically and electrically with the circuit board 402 coupled. In other implementations is the communication chip 406 Part of the processor 404 .

Depending on its applications, the computing element 400 other components with the circuit board 402 may or may not be physically and electrically coupled. The other components include, but are not limited to, volatile memory (e.g. DRAM), non-volatile memory (e.g. ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a screen, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a satellite navigation system (GPS), a compass, an accelerometer, a gyroscope, a loudspeaker, a camera and a mass storage device (such as a hard disk drive, compact disk (CD), digital versatile disk (DVD) and so on).

The communication chip 406 enables wireless communication to transfer data to and from the computing element 400 . The term "wireless" can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the connected devices do not contain any wires, although this may be the case in some embodiments. The communication chip 406 Can implement any number of wireless standards or protocols, including but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as all other wireless protocols that are referred to as 3G, 4G, 5G and beyond. The computing element 400 can a variety of communication chips 406 contain. For example, a first communication chip 406 for wireless communication over short distances such as Wi-Fi and Bluetooth and a second communication chip 406 can be used for long distance wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

The processor 404 of the computing element 400 includes an integrated circuit dielectric built into the processor 404 is packed. In some implementations of the invention, the integrated circuit dielectric of the processor includes one or more devices, such as non-planar wrap-around devices, that are formed in accordance with the implementations of the invention. The term “processor” can refer to all components or parts of a component that process electronic data from registers and / or memories in order to convert this electronic data into other electronic data that can be stored in registers and / or memories.

The communication chip 406 also includes an integrated circuit dielectric embedded in the communication chip 406 is packed. According to another implementation of the invention, the integrated circuit dielectric of the communication chip comprises one or more components, such as non-planar all-round gate components, which are formed according to the implementations of the invention.

In further implementations of the invention, a different one from the computing element 400 hosted component include an integrated circuit dielectric that includes one or more devices, such as non-planar gate wrap devices formed in accordance with the implementations of the invention.

In various implementations, the computing element 400 a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor , a set-top box, an entertainment control device, a digital camera, a portable music player or a digital video recorder. In other implementations, the computing element 400 any other electronic, data processing device.

One or more embodiments of the present invention include a non-planar wrap-around transistor with one of the embedded source and drain epitaxial regions or an insulating layer on the lower gate formed between the substrate and the lower channel nanowire, or both.

Claims (15)

A method (200) to form a semiconductor device, comprising: Providing (202) a substrate having a surface having a first lattice constant and a fin formed on the surface of the substrate; said fin comprises alternating layers of a semiconductor material having a second lattice constant and a sacrificial material having a third lattice constant, the second lattice constant being different from the first lattice constant and the third lattice constant; Forming (204) a sacrificial gate electrode over a channel region of the fin; Forming (206) a pair of sidewall spacers on opposite sides of said sacrificial gate electrode with a sacrificial portion of the fin protruding from each of said sidewall spacers; Removing (208) the sacrificial portion of the fin to expose the source and drain regions of the substrate; Forming (210) embedded epitaxial source and drain regions on said source and drain regions of the substrate, said embedded epitaxial source and drain regions coupled to the fin and having a fourth lattice constant that differs from that first lattice constant differs; Removing (212) said sacrificial gate electrode to expose the channel region of the fin; Removal (214) of the sacrificial material between the layers of the semiconductor material in the channel region of the fin to form a plurality of channel nanowires, said plurality of channel nanowires including a lowermost channel nanowire; Applying (218) a gate dielectric layer encasing all of the channel nanowires, and Applying (220) a gate electrode on the dielectric layer and completely enclosing all the channel nanowires. The procedure according to Claim 1 , said fin having a length and wherein said fin is subjected to lattice uniaxially in a direction parallel to the length of the fin and lattice relaxed in a perpendicular direction to the length of the fin. The procedure according to Claim 1 , wherein the embedded epitaxial source and drain regions are latticed uniaxially in a direction parallel to the length of the fin, and lattice unloaded in a perpendicular direction to the length of the fin. The procedure according to Claim 1 , said epitaxial source and drain regions exerting a force on the multiplicity of channel nanowires, wherein said multiplicity of channel nanowires are uniaxially strained in a direction parallel to the length of the fin and relieved of strain in a perpendicular direction to the length of the fin, and wherein said force is Maintains uniaxial lattice stress in the majority of nanowires. The procedure according to Claim 1 , wherein removing the sacrificial portion of the fin to expose the source and drain regions of the substrate includes recessing the surface of the substrate to form the source and drain trenches, and wherein said embedded epitaxial source and drain regions in the source and drain trenches are formed. The procedure according to Claim 1 , wherein the embedded epitaxial source and drain regions are formed by epitaxial growth and [111] -facetted. The procedure according to Claim 1 , further comprising bottom gate insulation that is on the surface of the substrate and under the lowermost channel nanowire, said bottom gate insulation being formed with a thickness sufficient to resist the surface of said substrate from capacitive coupling to protect said gate electrode. The procedure according to Claim 1 , wherein the second lattice constant and the fourth lattice constant are larger than the first lattice constant and the third lattice constant. The procedure according to Claim 1 , wherein the semiconductor material is a single-crystalline semiconductor material whose carrier mobility is greater than single-crystal silicon. The procedure according to Claim 1 , wherein the semiconductor material is undoped Ge, the sacrificial material is SiGe, the majority of the channel nanowires are undoped Ge and the embedded epitaxial source and drain regions are Ge. The procedure according to Claim 7 , wherein the lower gate insulation consists of silicon oxide. A method of forming a semiconductor device comprising: providing a substrate having a surface having a first lattice constant and a fin formed on the surface of the substrate; said fin comprises alternating layers of a semiconductor material with a second lattice constant and a sacrificial material with a third Lattice constant, the second lattice constant being different from the first lattice constant and the third lattice constant; Forming a sacrificial gate electrode over a channel region of the fin; Forming a pair of sidewall spacers on opposite sides of said sacrificial gate electrode; Removing said gate sacrificial electrode to expose the channel area of the fin; Removal of the sacrificial material between the layers of the semiconductor material in the channel region of the fin to form a plurality of channel nanowires, said majority of channel nanowires including a lowermost channel nanowire; Superposition of a dielectric material over and around said multiplicity of channel nanowires; Etching said dielectric layer to remove said dielectric except on the surface of the substrate under the lowermost channel nanowire to form bottom gate insulation, said bottom gate insulation not in physical contact with the lowermost channel nanowire; Applying a gate dielectric layer that encloses all channel nanowires and applying a gate electrode on the dielectric layer and completely encloses all channel nanowires. The procedure according to Claim 12 , said fin being one length and said fin being uniaxially strained in a direction parallel to the length of the fin and strain relieved in a perpendicular direction to the length of the fin. The procedure according to Claim 12 which further comprises forming a source region and a drain region in said fin on opposite sides of said gate sacrificial electrode. The procedure according to Claim 12 a sacrificial portion of the fin protruding from each of said sidewall spacers; Removing the sacrificial portion of the fin to expose the source and drain regions of the substrate and forming embedded epitaxial source and drain regions on said source and drain regions of the substrate, said embedded epitaxial source and drain regions are coupled to the fin and have a fourth lattice constant that differs from said first lattice constant.

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