KR102459732B1 - Manufacturing method of semiconductor device with gate-all-around channel - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device having a gate all-around channel. The method includes the steps of: forming a multiple nanosheet structure in which an optional sacrificial layer and a channel layer are alternately stacked on a substrate; forming a source/drain regrowth region by selectively etching the multiple nanosheet structure; removing a portion of the optional sacrificial layer according to a preset channel length; forming a source/drain layer on a region from which the source/drain regrowth region and the optional sacrificial layer are partially removed; and removing the remainder of the optional sacrificial layer.

Description

Method of manufacturing a semiconductor device having a gate all-around channel

The present invention relates to a method of manufacturing a semiconductor device having a gate all-around channel, and more particularly, to a method of manufacturing a semiconductor device having a gate all-around channel having a multi-nanosheet structure.

Advances in technologies such as artificial intelligence and smart phones require high integration and low power consumption due to the increase in information processing amount of semiconductor devices. As a method for increasing the integration of semiconductor devices, a gate-all-around (GAA) channel transistor using a three-dimensional structure has been proposed.

As shown in FIG. 1A , the gate all-around channel transistor has a structure in which a dielectric layer having a high dielectric constant (high-k) and a gate electrode surround the channel layer. The gate all-around channel transistor uses a three-dimensional structure to increase device integration and prevent leakage current by forming an independent channel layer. In addition, there are advantages of reducing a gate leakage current, controlling a gate field, and reducing an operating voltage.

Recently, as shown in FIG. 1B, multiple channel layers of the gate all-around channel transistor are formed to increase the current for the same input voltage, and the channel material is replaced with In(Ga)As instead of Si to achieve a low driving voltage. drive is possible It can be seen that In(Ga)As has about 10 times faster electron mobility than Si as shown in FIG. 1c.

That is, a gate all-around channel transistor having a multi-nanosheet structure having multiple In(Ga)As channel layers is being developed as a high-integration and high-performance device satisfying high current density and low power consumption.

An embodiment of the present invention prevents deformation of the channel layer by supporting the channel layer by overgrowth of the source/drain layer in the lateral direction, reduces the contact resistance between the source/drain layer and the channel layer, and without a separate masking process An object of the present invention is to provide a method of manufacturing a semiconductor device having a gate all-around channel capable of easily adjusting the channel length.

In embodiments, a method of manufacturing a semiconductor device having a gate all-around channel may include: forming a multi-nanosheet structure in which selective sacrificial layers and channel layers are alternately stacked on a substrate; forming a source/drain regrowth region by selectively etching the multi-nanosheet structure; removing a portion of the selective sacrificial layer according to a preset channel length; forming a source/drain layer on the source/drain regrowth region and the region from which the selective sacrificial layer is partially removed; and removing the remainder of the optional sacrificial layer.

Here, the selective sacrificial layer includes InP, and the channel layer includes In _x Ga _(1-x) As (0≤x≤1).

Here, the selective sacrificial layer is removed using an etching solution of H ₃ PO ₄ : HCl: CH ₃ COOH = 1:1:2.

Here, the multi-nanosheet structure further includes a sacrificial layer for protecting a channel formed at an interface between the selective sacrificial layer and the channel layer.

Here, the sacrificial layer for protecting the channel includes In _x Al _(1-x) As (0≤x≤1).

Here, the sacrificial layer for protecting the channel is removed simultaneously with the rest of the selective sacrificial layer using an etching solution of H ₃ PO ₄ : HCl: DI water = 1:1:1.

Here, the sacrificial layer for channel protection is removed using an etching solution of H ₃ PO ₄ : HCl: DI water = 1:1:38 after the remainder of the selective sacrificial layer is removed from the sacrificial layer for channel protection.

Here, the source/drain layer includes InGaAs.

Here, the method further includes forming source/drain electrodes on the source/drain layer after forming the source/drain layer.

Here, the forming of the source/drain regrowth region may include: forming a mask pattern exposing the source/drain regrowth region on the multi-nanosheet structure; and etching the multi-nanosheet structure using the mask pattern as an etch mask.

Here, the mask pattern includes any one of SiO ₂ and Al ₂ O ₃ .

Here, the method further includes removing the mask pattern after forming the source/drain electrodes.

Here, after removing the remainder of the selective sacrificial layer, forming a dielectric layer surrounding the channel layer; and forming a gate electrode surrounding the channel layer and the dielectric layer.

Here, the dielectric layer includes at least one of Al ₂ O ₃ , HfO, and a combination thereof.

The disclosed technology may have the following effects. However, this does not mean that a specific embodiment should include all of the following effects or only the following effects, so the scope of the disclosed technology should not be construed as being limited thereby.

The method of manufacturing a semiconductor device having a gate all-around channel according to an embodiment of the present invention prevents deformation of the channel layer by supporting the channel layer by overgrowth the source/drain layer in the lateral direction, and the source/drain layer and the channel It is possible to reduce the contact resistance between the layers.

In addition, the method of manufacturing a semiconductor device having a gate all-around channel according to an embodiment of the present invention can easily adjust the channel length without a separate masking process by adjusting the channel length when the channel layer is released.

1A is a schematic diagram showing an FET having a single nanosheet channel structure.
1B is a schematic diagram illustrating an FET having a multi-nanosheet channel structure.
1C is a graph illustrating electron mobility of Si and InGaAs.
2 is a diagram illustrating a method of manufacturing a semiconductor device having a gate all-around channel.
3 is a transmission electron micrograph showing a multi-nanosheet channel structure.
4 and 5 are diagrams for explaining a problem in the method of manufacturing the semiconductor device having the gate all-around channel shown in FIG. 2 .
6A to 6H are diagrams illustrating a method of manufacturing a semiconductor device having a gate all-around channel according to an embodiment of the present invention.

Since the description of the present invention is merely an embodiment for structural or functional description, the scope of the present invention should not be construed as being limited by the embodiment described in the text. That is, since the embodiment is capable of various changes and may have various forms, it should be understood that the scope of the present invention includes equivalents capable of realizing the technical idea. In addition, since the object or effect presented in the present invention does not mean that a specific embodiment should include all of them or only such effects, it should not be understood that the scope of the present invention is limited thereby.

On the other hand, the meaning of the terms described in the present application should be understood as follows. When a component is referred to as being “connected” to another component, it may be directly connected to the other component, but it should be understood that other components may exist in between. On the other hand, when it is mentioned that a certain element is "directly connected" to another element, it should be understood that the other element does not exist in the middle. On the other hand, other expressions describing the relationship between elements, that is, "between" and "between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The singular expression is to be understood to include the plural expression unless the context clearly dictates otherwise, and terms such as "comprises" or "have" refer to the embodied feature, number, step, action, component, part or these It is intended to indicate that a combination exists, and it should be understood that it does not preclude the possibility of the existence or addition of one or more other features or numbers, steps, operations, components, parts, or combinations thereof.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Terms defined in the dictionary should be interpreted as being consistent with the meaning of the context of the related art, and cannot be interpreted as having an ideal or excessively formal meaning unless explicitly defined in the present application.

FIG. 2 is a view showing a method of manufacturing a semiconductor device having a gate all-around channel, FIG. 3 is a transmission electron micrograph showing a multi-nanosheet channel structure, and FIGS. 4 and 5 are the gate all-around channels shown in FIG. It is a diagram illustrating a problem of a method of manufacturing a semiconductor device having an around channel.

Referring to FIG. 2 , first, as shown in (a), an epitaxial wafer 10 is prepared. The epitaxial wafer 10 may be formed using a metal-organic chemical vapor deposition (MOCVD) method, and may include a substrate 11 , a buffer layer 13 , a selective sacrificial layer 15 , a sacrificial layer 17 for channel protection, and a channel. layer 19 . Here, the substrate 11 may include InP, the buffer layer 13 may include InAlAs, the selective sacrificial layer 15 may include InP, the channel protection sacrificial layer 17 may include InAlAs, and the channel layer 19 may include InGaAs.

The selective sacrificial layer 15 and the channel layer 19 are sequentially stacked to form a single nanosheet structure, and a single nanosheet is multiplied according to the desired number of channel layers 19 to form a multiple nanosheet structure. can be formed

In this case, the channel protection sacrificial layer 17 may be formed at each interface between the selective sacrificial layer 15 and the channel layer 19 to protect the channel layer 19 . That is, the selective sacrificial layer 15, the channel protection sacrificial layer 17 and the channel layer 19, the channel protection sacrificial layer 17, and the selective sacrificial layer 15 are stacked in the same order to form a multi-nanosheet structure. can

Then, as shown in (b), a mask pattern 20 is formed on the epitaxial wafer 10 . Here, the mask pattern 20 may be formed of an insulating film such as SiO ₂ , Al ₂ O ₃ . In this case, the mask pattern 20 may be patterned to expose the source/drain regrowth planned region in consideration of a preset channel length. That is, the channel length can be adjusted by the mask pattern 20 .

Then, as shown in (c), the source/drain regrowth region 30 is formed by etching multiple nanosheets using the mask pattern 20 as an etch mask.

Then, as shown in (d), a source/drain layer 40 is grown on the source/drain regrowth region 30 . Here, the source/drain layer 40 may include n+ type In(Ga)As. Then, after depositing the source/drain electrodes 50 on the source/drain layer 40 , the mask pattern 20 is removed.

Then, as shown in (e), the selective sacrificial layer 15 is removed using a wet etching process. Here, in the wet etching process, in order to remove only the selective sacrificial layer 15 , the etch selectivity between the selective sacrificial layer 15 and the channel protective sacrificial layer 17 satisfies about 85:1 H ₃ PO ₄ : HCl: CH ₃ COOH = 1:1:2 etching solution may be used.

Then, as shown in (f), the sacrificial layer 17 for protecting the channel is selectively removed. Here, the sacrificial layer 17 for protecting the channel may be removed using an etching solution of H ₃ PO ₄ : HCl: DI water = 1:1:38.

Then, as shown in (g), a dielectric layer 60 surrounding the channel layer 19 is formed. Here, the dielectric layer 60 may include at least one of a material having a high dielectric constant, for example, Al ₂ O ₃ , HfO, and a combination thereof.

Next, as shown in (h), the gate electrode 70 surrounding the channel layer 19 and the dielectric layer 60 may be formed to complete the gate all-around channel transistor. Here, the gate electrode 70 may include TiN. That is, as shown in FIG. 3 , the gate all-around channel transistor may have a multi-nanosheet structure having multiple channel layers 19 .

However, when the multi-nanosheet structure is formed by the manufacturing method as described above, as shown in FIG. 4 , in the process of removing the selective sacrificial layer 15 in order to release the channel layer 19 , the etching solution The channel layer 19 is in contact with each other due to surface tension (A), or the channel layer 19 is sagged by gravity after the selective sacrificial layer 15 is removed (B) due to external factors such as 19) may be deformed.

In addition, as shown in FIG. 5 , since the channel length Lc is adjusted with the mask pattern 20, the length of the channel length in the short axis direction (L _c,1 ) and the major axis direction length (L _{c, 2} ) for each A separate masking process is required. And, since both end surfaces of the channel layer 19 are in contact with the source/drain layer 40 , the contact resistance between the channel layer 19 and the source/drain layer 40 is determined by the thickness of the channel layer 19 . . That is, as the thickness of the channel layer 19 decreases, the contact resistance may increase.

6A to 6H are diagrams illustrating a method of manufacturing a semiconductor device having a gate all-around channel according to an embodiment of the present invention.

Referring to FIG. 6A , an epitaxial wafer 100 is first prepared. Here, the epitaxial wafer 100 may include a substrate 110 , a buffer layer 120 , a selective sacrificial layer 130 , a channel protection sacrificial layer 140 , and a channel layer 150 . Here, the substrate 110 includes an inorganic substrate or an organic substrate for providing a semiconductor device, and a rigid or flexible substrate may be used.

For example, Si, GaN, GaAs, SiC, AlN, BN, GaN, InP, etc. may be used for the substrate 110 , and sapphire, glass, and quartz may be used as the insulating substrate. In an embodiment of the present invention, a case in which the substrate 110 is an InP (100) substrate will be described as an example. In addition, the buffer layer 120 is formed on the substrate 110 and may include InAlAs.

The selective sacrificial layer 130 is formed on the buffer layer 120 and may be made of InP. The channel protection sacrificial layer 140 is formed on the selective sacrificial layer 130 , and the channel protection sacrificial layer 140 induces the epitaxial growth of the channel layer 150 , while the selective sacrificial layer 130 and the channel layer 150 . ) may be formed of a material that suppresses an intermixing phenomenon between constituent materials constituting it. In addition, the sacrificial layer 140 for protecting the channel may use a material that is lattice-matched to the channel layer 150 . For example, the sacrificial layer 140 for protecting the channel may include In _x Al _(1-x) As (0≤x≤1).

The channel protection sacrificial layer 140 prevents the formation of a natural oxide film by exposing the channel layer 150 to the air during the selective sacrificial layer 130 removal process, thereby eliminating the need for a natural oxide film removal process and removing the natural oxide film. A phenomenon in which a thickness loss of the channel layer 150 occurs due to the process may be prevented.

The channel layer 150 is formed on the sacrificial layer 140 for protecting the channel, and may include In _x Ga _(1-x) As (0≤x≤1). According to an embodiment of the present invention, the selective sacrificial layer 130 and the channel layer 150 are sequentially stacked to form a single nanosheet structure, and a single nanosheet is formed multiple according to the desired number of channel layers 150 . Thus, it can be formed into a structure of multiple nanosheets. That is, the multi-nanosheet has a structure in which the selective sacrificial layer 130 and the channel layer 150 are alternately stacked. Here, the multi-nanosheet structure according to an embodiment of the present invention may further include a channel protection sacrificial layer 140 formed at each interface between the selective sacrificial layer 130 and the channel layer 150 .

That is, the multi-nanosheet structure may be formed in the same order as the selective sacrificial layer 130 , the channel protection sacrificial layer 140 , the channel layer 150 , the channel protection sacrificial layer 140 , and the selective sacrificial layer 130 . . An embodiment of the present invention has been described as an example in which the channel layer 150 is formed in triple, but the embodiment of the present invention is not limited thereto. can Here, the selective sacrificial layer 130 , the channel protection sacrificial layer 140 , and the channel layer 150 may be formed by a MOCVD method in a continuous process.

Referring to FIG. 6B , a mask pattern 200 exposing the source/drain re-growth region is formed on the epitaxial wafer 100 . Here, the mask pattern 200 includes an insulating layer such as SiO ₂ , Al ₂ O ₃ . Then, the source/drain regrowth region 300 is formed by etching multiple nanosheets using the mask pattern 200 as an etch mask.

Referring to FIG. 6C , a portion of the selective sacrificial layer 130 is removed so that only the selective sacrificial layer 130 corresponding to the preset channel length Lc remains. That is, according to an embodiment of the present invention, the channel length may be adjusted by the process of removing the selective sacrificial layer 130 . Here, the selective sacrificial layer 130 may be removed by a wet etching process.

In this case, the process conditions of the wet etching process may be controlled so that only the selective sacrificial layer 130 corresponding to the preset channel length remains. For example, the etching depth of the selective sacrificial layer 130 may be controlled by adjusting the process time of the wet etching process. Here, in the wet etching process, in order to remove only the selective sacrificial layer 130 , the etch selectivity between the selective sacrificial layer 130 and the channel protection sacrificial layer 140 satisfies about 85:1 H ₃ PO ₄ : HCl: CH ₃ COOH = 1:1:2 etching solution may be used.

Referring to FIG. 6D , a source/drain layer 400 is grown on the source/drain regrowth region 300 . Here, the source/drain layer 400 may be formed of n+ type In(Ga)As. In this case, the source/drain layer 400 is lateral epitaxial overgrowth (LEO) on the region where the selective sacrificial layer 130 is partially removed.

That is, the source/drain layer 400 according to an embodiment of the present invention overgrowth from both ends of the channel layer 150 in the lateral direction to increase the contact area with the channel layer 150 , and the channel layer 150 . It can serve as a support to support the Due to this, the contact resistance between the channel layer 150 and the source/drain layer 400 is reduced, and the channel layer 150 is deformed when the selective sacrificial layer 130 and the channel protection sacrificial layer 140 are removed. can prevent

Referring to FIG. 6E , the source/drain electrode 500 is formed on the source/drain layer 400 . Then, the mask pattern 200 is removed.

Referring to FIG. 6F , the selective sacrificial layer 130 and the channel protecting sacrificial layer 140 are removed. Here, the selective sacrificial layer 130 and the channel protection sacrificial layer 140 may be sequentially removed by a wet etching process or may be simultaneously removed. For example, the selective sacrificial layer 130 may be removed first, and then the sacrificial layer 140 for channel protection may be removed. In this case, the selective sacrificial layer 130 may be removed using an etching solution of H ₃ PO ₄ : HCl: CH ₃ COOH = 1:1:2, and the sacrificial layer 140 for channel protection is H ₃ PO ₄ : HCl. : It can be removed using an etching solution of DI water = 1:1:38.

In addition, when the selective sacrificial layer 130 and the channel protection sacrificial layer 140 are simultaneously removed, it may be removed using an etching solution of H ₃ PO ₄ : HCl: DI water = 1:1:1. In this case, since the channel layer 150 is supported by the source/drain layer 400 , it is possible to prevent deformation by the etching solution or gravity.

Referring to FIG. 6G , a dielectric layer 600 surrounding the channel layer 150 is formed. Here, the dielectric layer 600 may include a material having a high dielectric constant, for example, at least one of Al ₂ O ₃ , HfO, and a combination thereof.

Referring to FIG. 6H , the gate electrode 700 surrounding the channel layer 150 and the dielectric layer 600 may be formed to complete the gate all-around channel transistor. Here, the gate electrode 700 may include TiN.

Here, the exemplary embodiment of the present invention has been described with the FET structure as an example, but the exemplary embodiment of the present invention is not limited thereto, and may be applied to various semiconductor devices having the multi-channel layer 150 . For example, it can be applied to Fin FET, Tunnel FET, Nanowire FET, NCFET, HEMT, and the like.

As described above, in the method of manufacturing a semiconductor device having a gate all-around channel according to an embodiment of the present invention, a channel using a selective sacrificial layer 130 in a multi-nanosheet structure including a plurality of channel layers 150 is used. Since the length is adjusted, a masking process of individually patterning the mask pattern 200 to adjust the channel length is unnecessary.

In addition, the source/drain layer 400 is overgrown on the region where the selective sacrificial layer 130 is partially removed to form a contact area with the channel layer 150 to extend inwardly from both ends of the channel layer 150 . to increase and support between adjacent channel layers 150 .

For this reason, the selective sacrificial layer 130 and the channel protection sacrificial layer 140 are formed to reduce the contact resistance between the source/drain layer 400 and the channel layer 150 and release the channel layer 150 . In the removal process, it is possible to prevent the channel layer 150 from sticking to each other due to the surface tension of the etching solution or from sagging the channel layer 150 due to gravity.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it can be done.

100: epi wafer
200: mask pattern
300: source/drain regrowth region
400: source/drain layer
500: source / drain electrode
600: dielectric layer
700: gate electrode

Claims (14)

forming a multi-nanosheet structure in which selective sacrificial layers and channel layers are alternately stacked on a substrate;
forming a source/drain regrowth region by selectively etching the multi-nanosheet structure;
removing a portion of the selective sacrificial layer according to a preset channel length;
forming a source/drain layer on the source/drain regrowth region and the region from which the selective sacrificial layer is partially removed; and
removing the remainder of the optional sacrificial layer;
The multi-nanosheet structure is
Further comprising a sacrificial layer for channel protection formed at the interface between the selective sacrificial layer and the channel layer,
The method of manufacturing a semiconductor device having a gate all-around channel, wherein the sacrificial layer for protecting the channel includes In _x Al _(1-x) As (0≤x≤1). According to claim 1,
The optional sacrificial layer includes InP,
The channel layer is a method of manufacturing a semiconductor device having a gate all-around channel including In _x Ga _(1-x) As (0≤x≤1). According to claim 1,
The optional sacrificial layer is
A method of manufacturing a semiconductor device having a gate all-around channel that is removed using an etching solution of H ₃ PO ₄ : HCl: CH ₃ COOH =1:1:2. delete delete According to claim 1,
The method of manufacturing a semiconductor device having a gate all-around channel in which the channel protection sacrificial layer is simultaneously removed with the remainder of the selective sacrificial layer using an etching solution of H ₃ PO ₄ : HCl: DI water = 1:1:1. 7. The method of claim 6,
The sacrificial layer for protecting the channel is removed using an etching solution of H ₃ PO ₄ : HCl: DI water = 1:1:38 after the remainder of the selective sacrificial layer is removed. Fabrication of a semiconductor device having a gate all-around channel Way. According to claim 1,
The method of manufacturing a semiconductor device having a gate all-around channel in which the source/drain layer includes InGaAs. According to claim 1,
The method of manufacturing a semiconductor device having a gate all-around channel further comprising the step of forming a source/drain electrode on the source/drain layer after the step of forming the source/drain layer. 10. The method of claim 9,
The step of forming the source/drain regrowth region includes:
forming a mask pattern exposing the source/drain re-growth region on the multi-nanosheet structure; and
and etching the multi-nanosheet structure using the mask pattern as an etch mask. 11. The method of claim 10,
The mask pattern is a method of manufacturing a semiconductor device having a gate all-around channel including any one of SiO ₂ and Al ₂ O ₃ . 11. The method of claim 10,
and removing the mask pattern after forming the source/drain electrodes. According to claim 1,
After removing the remainder of the optional sacrificial layer
forming a dielectric layer surrounding the channel layer; and
The method of manufacturing a semiconductor device having a gate all-around channel further comprising the step of forming a gate electrode surrounding the channel layer and the dielectric layer. 14. The method of claim 13,
The dielectric layer is
A method of manufacturing a semiconductor device having a gate all-around channel including at least one of Al ₂ O ₃ , HfO, and a combination thereof.

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