DE1109422B - Asynchrone binaere Additions- und Subtraktionseinrichtung - Google Patents

Asynchrone binaere Additions- und Subtraktionseinrichtung

Info

Publication number
DE1109422B
DE1109422B DEJ18099A DEJ0018099A DE1109422B DE 1109422 B DE1109422 B DE 1109422B DE J18099 A DEJ18099 A DE J18099A DE J0018099 A DEJ0018099 A DE J0018099A DE 1109422 B DE1109422 B DE 1109422B
Authority
DE
Germany
Prior art keywords
output
circuit
carry
input
digit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DEJ18099A
Other languages
German (de)
English (en)
Inventor
Melvin Ross Marshall
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE1109422B publication Critical patent/DE1109422B/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Quality & Reliability (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
DEJ18099A 1959-05-11 1960-05-11 Asynchrone binaere Additions- und Subtraktionseinrichtung Pending DE1109422B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US812504A US2998191A (en) 1959-05-11 1959-05-11 Asynchronous add-subtract system

Publications (1)

Publication Number Publication Date
DE1109422B true DE1109422B (de) 1961-06-22

Family

ID=25209776

Family Applications (1)

Application Number Title Priority Date Filing Date
DEJ18099A Pending DE1109422B (de) 1959-05-11 1960-05-11 Asynchrone binaere Additions- und Subtraktionseinrichtung

Country Status (4)

Country Link
US (1) US2998191A (enExample)
DE (1) DE1109422B (enExample)
GB (1) GB875153A (enExample)
NL (2) NL250876A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1524268B1 (de) * 1966-06-04 1970-07-02 Zuse Kg Anordnung zur Fehlerermittlung in Rechenwerken

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL246812A (enExample) * 1958-12-29
US3233117A (en) * 1959-08-25 1966-02-01 Ibm High speed logical circuits employing a negative resistance device
BE639864A (enExample) * 1962-11-14
US4994993A (en) * 1988-10-26 1991-02-19 Advanced Micro Devices, Inc. System for detecting and correcting errors generated by arithmetic logic units

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2861744A (en) * 1955-06-01 1958-11-25 Rca Corp Verification system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1524268B1 (de) * 1966-06-04 1970-07-02 Zuse Kg Anordnung zur Fehlerermittlung in Rechenwerken

Also Published As

Publication number Publication date
US2998191A (en) 1961-08-29
NL250876A (enExample)
GB875153A (en) 1961-08-16
NL135201C (enExample)

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