DE10345257A1 - Chipkarte mit Kontaktfelder und Verfahren zum Herstellen solcher Kontaktfelder - Google Patents

Chipkarte mit Kontaktfelder und Verfahren zum Herstellen solcher Kontaktfelder Download PDF

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Publication number
DE10345257A1
DE10345257A1 DE10345257A DE10345257A DE10345257A1 DE 10345257 A1 DE10345257 A1 DE 10345257A1 DE 10345257 A DE10345257 A DE 10345257A DE 10345257 A DE10345257 A DE 10345257A DE 10345257 A1 DE10345257 A1 DE 10345257A1
Authority
DE
Germany
Prior art keywords
contact fields
chip card
functional areas
producing
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10345257A
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English (en)
Other versions
DE10345257B4 (de
Inventor
Frank Pueschner
Wolfgang Schindler
Ewald Simmerlein
Peter Stampka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10345257A priority Critical patent/DE10345257B4/de
Priority to CNA2004800282981A priority patent/CN1860492A/zh
Priority to KR1020067006014A priority patent/KR20060073631A/ko
Priority to EP04786834A priority patent/EP1668572A1/de
Priority to PCT/DE2004/002118 priority patent/WO2005031638A1/de
Publication of DE10345257A1 publication Critical patent/DE10345257A1/de
Priority to US11/392,451 priority patent/US7579679B2/en
Application granted granted Critical
Publication of DE10345257B4 publication Critical patent/DE10345257B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

Chipkarte mit einem einen integrierten Schaltkreis enthaltenden Chipmodul, der auf einer Hauptfläche für eine externe Kontaktierung eine Kontaktzone mit mehreren zueinander beabstandeten Kontaktfeldern aufweist, die mit dem integrierten Schaltkreis elektrisch verbunden sind, wobei mindestens ein Kontaktfeld aus ersten Funktionsbereichen mit ersten Oberflächen und aus zweiten Funktionsbereichen mit zweiten Oberflächen zusammengesetzt ist und wobei die ersten Oberflächen der ersten Funktionsbereiche bezüglich der Hauptfläche höher liegen als die zweiten Oberflächen der zweiten Funktionsbereiche.
DE10345257A 2003-09-29 2003-09-29 Chipkarte mit Kontaktfelder und Verfahren zum Herstellen solcher Kontaktfelder Expired - Fee Related DE10345257B4 (de)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE10345257A DE10345257B4 (de) 2003-09-29 2003-09-29 Chipkarte mit Kontaktfelder und Verfahren zum Herstellen solcher Kontaktfelder
CNA2004800282981A CN1860492A (zh) 2003-09-29 2004-09-23 具有接触区域的芯片卡和制造这种接触区域的方法
KR1020067006014A KR20060073631A (ko) 2003-09-29 2004-09-23 칩 카드 및 이에 대한 칩 모듈용 컨택 영역 제조 방법
EP04786834A EP1668572A1 (de) 2003-09-29 2004-09-23 Chipkarte mit kontaktfeldern und verfahren zum herstellen solcher kontaktfelder
PCT/DE2004/002118 WO2005031638A1 (de) 2003-09-29 2004-09-23 Chipkarte mit kontaktfeldern und verfahren zum herstellen solcher kontaktfelder
US11/392,451 US7579679B2 (en) 2003-09-29 2006-03-29 Chipcard with contact areas and method for producing contact areas

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10345257A DE10345257B4 (de) 2003-09-29 2003-09-29 Chipkarte mit Kontaktfelder und Verfahren zum Herstellen solcher Kontaktfelder

Publications (2)

Publication Number Publication Date
DE10345257A1 true DE10345257A1 (de) 2005-04-28
DE10345257B4 DE10345257B4 (de) 2008-10-02

Family

ID=34384330

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10345257A Expired - Fee Related DE10345257B4 (de) 2003-09-29 2003-09-29 Chipkarte mit Kontaktfelder und Verfahren zum Herstellen solcher Kontaktfelder

Country Status (6)

Country Link
US (1) US7579679B2 (de)
EP (1) EP1668572A1 (de)
KR (1) KR20060073631A (de)
CN (1) CN1860492A (de)
DE (1) DE10345257B4 (de)
WO (1) WO2005031638A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100723493B1 (ko) 2005-07-18 2007-06-04 삼성전자주식회사 와이어 본딩 및 플립 칩 본딩이 가능한 스마트 카드 모듈기판 및 이를 포함하는 스마트 카드 모듈
DE102008028300B4 (de) * 2008-06-13 2021-10-07 Tdk Electronics Ag Leiterplatte mit flexiblem Bereich und Verfahren zur Herstellung
FR2932910B1 (fr) * 2008-06-20 2011-02-11 Smart Packaging Solutions Sps Carte sans contact avec logo securitaire
US8991711B2 (en) * 2012-07-19 2015-03-31 Infineon Technologies Ag Chip card module
DE102013105575A1 (de) * 2013-05-30 2014-12-04 Infineon Technologies Ag Chipkartenmodul, Chipkarte, und Verfahren zum Herstellen eines Chipkartenmoduls

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19630049A1 (de) * 1996-07-25 1998-01-29 Siemens Ag Chipkarte mit einer Kontaktzone und Verfahren zum Herstellen einer solchen Kontaktzone
WO2000021027A1 (de) * 1998-10-05 2000-04-13 Orga Kartensysteme Gmbh Verfahren zur herstellung eines trägerelements für einen ic-baustein zum einbau in chipkarten
DE10207002A1 (de) * 2002-02-19 2003-08-28 Orga Kartensysteme Gmbh Verfahren zum Implantieren von Chipmodulen in Datenträgerkarten

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2695234B1 (fr) * 1992-08-26 1994-11-04 Gemplus Card Int Procédé de marquage d'une carte à puce.
EP0835497B1 (de) * 1995-06-27 2013-03-27 Morpho Cards GmbH Chipkarte
US6232563B1 (en) * 1995-11-25 2001-05-15 Lg Electronics Inc. Bump electrode and method for fabricating the same
DE19604319B4 (de) * 1996-02-07 2007-02-22 Sagem Orga Gmbh Chipkarte
KR100499306B1 (ko) 1997-01-23 2005-11-22 세이코 엡슨 가부시키가이샤 반도체장치및그제조방법
US6644552B1 (en) * 2002-07-09 2003-11-11 John Herslow Composite card

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19630049A1 (de) * 1996-07-25 1998-01-29 Siemens Ag Chipkarte mit einer Kontaktzone und Verfahren zum Herstellen einer solchen Kontaktzone
WO2000021027A1 (de) * 1998-10-05 2000-04-13 Orga Kartensysteme Gmbh Verfahren zur herstellung eines trägerelements für einen ic-baustein zum einbau in chipkarten
DE10207002A1 (de) * 2002-02-19 2003-08-28 Orga Kartensysteme Gmbh Verfahren zum Implantieren von Chipmodulen in Datenträgerkarten

Also Published As

Publication number Publication date
DE10345257B4 (de) 2008-10-02
KR20060073631A (ko) 2006-06-28
US20060246628A1 (en) 2006-11-02
EP1668572A1 (de) 2006-06-14
CN1860492A (zh) 2006-11-08
US7579679B2 (en) 2009-08-25
WO2005031638A1 (de) 2005-04-07

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R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee