DE102010043661A1 - Vehicle control unit testing device for use in hardware in-the-loop simulator, has computing unit and signal generating card that are connected with serial bus interface for receiving and/or sending time and angle synchronous messages - Google Patents

Abstract

The device has a computing unit utilized for executing an environment model. A signal generating card is utilized for providing a signal for an electronic control unit. A serial bus i.e. Ethernet, is utilized for bidirectionally transmitting data between the computing unit and the signal generating card. The computing unit and the signal generating card are connected with a serial bus interface for receiving and/or sending a time synchronous message and an angle synchronous message. An independent claim is also included for a hardware in-the-loop (HIL) simulator comprising a combining device.

Description

Technical area

The invention relates to a device for testing at least one electronic control and / or regulating device, wherein in the text both an actual control device and a control device is referred to as a control device. Furthermore, the invention relates to an HIL simulator.

State of the art

Devices for testing, in particular those designed as HIL simulators, are known from the prior art and are used in particular for the testing of control devices.

HIL simulators, which are often referred to in the art as "simulator" or "HIL" for short, each comprise at least one computer unit, wherein the computer unit (English: computation node) or the computer units in particular have the task of so-called models (the often comprising at least one environment model) that at least partially replicates an environment of an electronic device or a more complex technical system.

The abbreviation "HIL" (derived from the English phrase "hardware in the loop") is an international, especially in German-speaking countries used, technical term for a test method in which an "embedded system" (abbreviation: "ES"), In particular, an electronic control unit (ECU), or a mechatronic module via its inputs and outputs to an adapted counterpart, which is often referred to as HIL simulator, and used to simulate the real environment of the embedded system is connected. During the test of the embedded system ES, therefore, at least part of the input signals for the ES are provided by the HIL simulator and at least part of the output signals of the ES are sent to the HIL simulator.

For example, by means of an environment model that is executed on an HIL simulator, the temporal behavior of the environment of the system to be tested can be simulated. Should z. B. an HIL simulator an embedded system, in particular a control unit (ECU) test, then the HIL simulator is configured as at least partially replica of the real environment of the control unit. The HIL simulator can therefore communicate in this case via its inputs and outputs or bidirectional communication channels with the control unit and thus act as an adapted counterpart of the control unit.

The HIL simulation usually has to run in real time and is used in development to shorten development times and save costs. In particular, recurring processes can be simulated and / or automated. This has the advantage that a new development version of a control program can be tested under the same criteria as the previous version. Thus, it can be demonstrated in detail whether an error has been eliminated or not (re-testing).

The tests on real systems (eg a braking system of a motor vehicle) can be greatly reduced and in addition system limits can be determined without jeopardizing the real system and its users (eg car and driver).

The HIL simulation is always just a simplification of reality and therefore can not replace the test on the real system. If there are too large discrepancies between the HIL simulation and the reality, the underlying models are too simplistic in the simulation. Then the simulation models have to be developed further.

Before going into the details of the invention, some aspects of developing control devices and related development tools will first be elucidated, as these aspects provide a better understanding of the invention.

The prerequisite for a simulation of a controlled system (ECU) for a ECU with an HIL simulator is the existence of an environment model, which is often referred to as a route model. This environment model for an HIL simulator is often represented by a block diagram created by a graphical modeling environment whose blocks are connected by signal lines for transmitting signals. An example of one of the common graphic development environment for creating graphical programs is the product Simulink of the US company The MathWorks. Details of this product can be found on the Internet at www.mathworks.com or www.mathworks.com/products/simulink be removed.

However, known alternative representations for an environment model are in particular also computer programs which were created either by means of a higher, non-graphical programming language, such as the C ++ programming language, or indeed were created by means of a graphical programming language, but the models created herewith, for example, beside or Alternatively to signal flow diagrams also have control flow charts.

Other known development environments for creating environment models or controlled system models have the options of combining non-graphical environment models or their parts with graphical environment models or their parts, for example, the graphic model parts signal flow and / or control flow diagrams and / or not - Causal diagrams, which are neither signal flow nor control flow diagrams, have.

The control algorithms that are designed to be executed on a control unit ECU are often implemented using an o. G. developed graphical modeling environment, in particular a so-called function control program is generated as a result of the function development for the control unit.

Methods for automatically or semi-automated generation of control system programs using block diagrams from graphical modeling environments are well known in the art and are used primarily in applied research and industrial development in the wide field of development and deployment of electronic control systems, particularly in the fields of mechatronics , automotive applications (here control systems are preferably referred to as control devices), in aerospace, in plant and process engineering and other technical fields in which process control tasks must be solved in the broadest sense.

The term "control system" is used hereafter as a generic term for a technical device which is essentially used for the tasks described above (measuring, controlling, regulating, calibrating) in said fields; in a broader sense, it can generally be an electronic, programmable system. The term is not limited to what is narrowly defined in the system-theoretical sense as a control. Hereinafter, reference will be made to a controller as an example of a control system.

To derive and explain the concept of the invention, it is helpful to first explain basic concepts and typical work processes in this field. The ultimate goal of the planned control of any technical process is achieved essentially over - or part of - the following stations: controller design by simulation (functional development), test of the control concept in the real process with a powerful development control system (rapid control prototyping, RCP), (automated) transferring the control algorithm to a production controller, testing the control algorithm with the series controller in a partially or fully simulated outside world (Hardware-in-the-Loop Test, HIL) and finally fine-tuning the control parameters using a Series controller through the so-called calibration.

In functional development, a mathematical model of the technical process to be influenced or examined, as well as the controller to be used, is first created using a computer-aided graphic modeling environment. Typically, modeling in these graphical environments is done by means of the block diagram representation known from systems theory, in which individual blocks have a certain mathematical functionality, from simple algebraic operations to complicated dynamic behavior. Blocks of a block diagram are interconnected by signal lines, and input signals of a block are, for example, linked together and / or impressed upon transmission by such a block, and the results of these transformations are generally output by signals for further use output.

The modeling environments often offer the possibility of numerical simulation of the block diagram in addition to the mere model creation, and it is thus possible, for example, with the aid of a process model, various simulation algorithms by simulation, without physical connection to the real process, to design and debug. This abstract part of a model / block diagram is referred to below as a function model.

In order to use the closed-loop control concept developed in the simulation in the real process, the control algorithm must be transferred to a program for a control system, which is connected to the process to be controlled via corresponding I / O devices, and supplemented by instructions in order to obtain the I / O To be able to address devices at all.

Within the scope of the teaching of this invention, an I / O device is understood as meaning a large bandwidth of possible technical devices with one or more outside world interfaces. In addition to the usual devices with analog and digital input and output channels include u. a. also devices with intelligent signal processing for the pre- and postprocessing of (raw) data, data bus modules, devices for signal conditioning, but eg. B. also power modules. An I / O device can technically form a separate unit that can be added to a computer unit (for example, internal bus slot in the computer unit, coupling via an external communication interface), but it can also be an integral part of a computer unit, eg. B. if implemented in a processor I / O device functionality integrated.

The teaching of the invention is basically limited to any specific device-technical embodiment, or dependent on such.

Such a program, both functional calculation shares, z. B. from the functional model, as well as shares for influencing hardware components (eg I / O devices) and can be operated on a HIL simulator or on a control system (eg, an automotive control unit), is referred to below as the environment model (if execution is provided on an HIL simulator) or as the overall control program or as the overall control model.

In practice, on the other hand, the modeling environment on the one hand and the environment model or overall control program on the other are often operated on different computing devices: modeling environments are typically run on PCs or workstations with popular standard operating systems, and environment models or overall control programs on computing devices equipped with a real-time operating system, for example To perform control tasks within a predefined time interval.

The transmission of the environment model or function model, or a part thereof, into an executable program for an HIL simulator or a control system consists, as indicated above, not only from the programmatic simulation of the mathematical calculations (function model), but it must In addition, the physical variables to be read in via the I / O devices, as well as the manipulated variables to be output via the I / O devices, are taken into account in the overall control program and corresponding function calls are provided at a suitable point in the course of the program. B. use appropriate software libraries with driver functionality for the I / O devices.

The accomplishment of this task by manual programming is extremely error-prone, time-consuming, cost-intensive and is therefore largely automated in practice, since the interfaces to the I / O devices are already modeled in the modeling environment. For this purpose, supplementary block libraries are used to describe the I / O devices or the I / O boards of the HIL simulator and / or the control system, whereby different blocks have different I / O devices, components of them (e.g. Channels of digital-to-analog converters, digital I / O channels) and z. T. complex configurable modules (eg data buses and definition of the messages transmitted by them and their timing behavior, generation / analysis of signal waveforms by digital signal processors) represent their properties in the modeling environment or the block diagram, z. B. dialog windows or similar means are adjustable.

The portion of a block diagram that broadly specifies the use of I / O devices or I / O boards is referred to below as the I / O model and the blocks used in this model section as I / O blocks , The I / O blocks should include all those blocks that are used to affect hardware components, even if they are not primarily I / O devices (eg, pure computational devices in multiprocessor systems or computational devices as part of intelligent I) / O devices that use slave processors to handle their tasks, for example).

Some known development environments for creating an environment model or controller model provide, for example, that I / O blocks are connected to the signal lines or inserted into the signal lines whose signals are passed through the control system I / O devices or I / O boards of the HIL simulator should be output or read in. For this reason, in these development environments, the functional model and the I / O model are interwoven in the method described above, even though the conceptual separation made here may give the impression of two cleanly separable / separated model parts.

With the aid of a translation program, it is then possible to transfer the block diagram, or parts of it, into an overall control program executable on the control system, often with the intermediate step of code generation from the block diagram, then compilation of the code by one for the control system or for the computer unit of the HIL simulator suitable compiler and possibly the left required software modules to an executable unit. Block diagrams may also be translated by an appropriate translation program into an interpreter language executed by a corresponding interpreter. The tools needed for this can be part of the modeling environment, but they can also represent separate applications, with information about the block diagram then being used for example. B. file-based exchanged or programming interfaces of the modeling environment can be used.

A common practice is a separate computer unit (host computer) for operating the modeling environment and the translation program and the computer unit for operating the overall control program or the environment model (on the target computer or on the computer unit of a HIL simulator) by communication interfaces with each other with the advantage that in the modeling environment developed control concepts or concepts for the simulation of the controlled system including a corresponding description of the I / O devices or I / O cards used, their parameterization and transmitted by them signals from the host system fully automated can be transferred into an environment model or into an overall control program.

If, however, the environment model has been developed and translated, for example, on the computer unit of the HIL simulator itself and not on a separate host computer, then the transmission from the host computer to the computer unit of the HIL simulator is unnecessary. In this case, the computer unit of the HIL simulator can, for example, be designed such that it supports and executes two operating systems. For example, a real-time operating system can be provided for the execution of the environment model, and a standard operating system, such as Microsoft Windows 7, for the execution of the modeling environment, ie for the development of the environment model Applications of the HIL simulation should be sufficient if a computer unit is provided both for the execution of the modeling environment and for the execution of the environment model, which is equipped only with a standard operating system, which therefore does not belong to the genus of real-time operating systems.

Once the environment model is loaded on the computing unit of the HIL simulator and at least a selection from the set of I / O channels of the I / O devices or I / O boards of the HIL simulator with the corresponding I / O ports are connected to the tested ECU / s, the HIL simulation can be started.

For example, the method described above, together with the networking of the system components, has also been used successfully for many years in the field of rapid control prototyping, ie a method for the rapid design, implementation and testing or testing of controllers and controls. Comparable methods and networked architectures of computer units and I / O devices are also used in HIL tests, in the sole or supplementary execution of measurement tasks (data acquisition) and in the calibration of control parameters in closed control systems (eg series control units ), in which computer unit and associated I / O devices are often implemented in a device-specific unit.

Systems that support the work process described above belong to the state of the art from which the invention is based (see, for example, dSPACE GmbH: Product Catalog 2010, product documentation for dSPACE Release in spring 2010), in particular "Real-Time Interface (RTI), Implementation Guide "(Including block-based modeling of I / O devices and target computers, code generation for these block libraries), TargetLink (including code generation for (serial) controllers from block diagrams); or The MathWorks: Product Documentation for Release 2010b, especially MATLAB & Simulink (Environment for mathematical, block-based modeling and simulation), "Real-Time Workshop, User's Guide", xPC Target (blocks for model-based I / O device description, code generation for I / O devices, real-time operating system for PC hardware).

Conventional devices for testing at least one electronic control unit and conventional HIL simulators have performance bottlenecks in the execution of comparatively complex models, in particular complex environment models, or offer due to the hardware architecture only limited flexibility in hardware expansion or spatial hardware distribution or have another of the already mentioned disadvantages of the prior art.

Description of the invention

The object of the present invention is therefore to develop the prior art or at least partially overcome the disadvantages of the prior art.

The object of the invention is achieved by a device having the features of claim 1.

The object of the invention is further solved by an HIL simulator having the features of claim 2.

Advantageous developments of the HIL simulator according to the invention are specified in the dependent claims.

With reference to the figures, which show preferred embodiments of the HIL simulator according to the invention, the invention will be further explained below.

The 1 and 2 show by way of example and schematically some modules of an HIL simulator with connected ECU ECU, as well as connected to the HIL simulator real load. In 3 The interaction between the HIL simulator internal FRU, FR, FIU and PSB and the external ECU connected to the HIL simulator are illustrated schematically by means of an example. For reasons of clarity not all modules, components and connections are shown in the figures.

The device according to the invention for testing at least one electronic control unit ECU has at least one computer unit CN for executing at least one environment model, and at least one signal generation board SGB for providing at least one signal for the electronic control unit ECU, and at least one serial bus IOCN for bidirectional data transmission from the computer unit CN to the signal generation card SGB or vice versa, wherein both the computer unit CN and the signal generation card SGB each have at least one interface 12a . 12b to the serial bus, and these interfaces 12a . 12b are provided and arranged to receive and / or send time synchronization messages as well as angle synchronization messages.

The HIL simulator according to the invention 1 comprises a device for testing at least one electronic control unit ECU, this device having at least one computer unit CN for executing at least one environment model, and at least one signal generation board SGB for providing at least one signal for the electronic control unit ECU, and at least one serial bus IOCN for bidirectional data transmission from the computer unit CN to the signal generation card SGB or vice versa, and wherein both the computer unit CN and the signal generation card SGB each have at least one interface 12a . 12b to the serial bus, and these interfaces 12a . 12b are provided and arranged to receive and / or send time synchronization messages as well as angle synchronization messages.

In a preferred embodiment of the HIL simulator according to the invention 1 , the serial bus IOCN is an Ethernet connection.

Another advantageous embodiment of the HIL simulator 1 According to the invention, it is characterized in that the time synchronization messages and / or the angle synchronization messages are encompassed by at least one network protocol of a network protocol stack of the serial bus.

Furthermore, it can be provided that in the HIL simulator 1 both the computer unit CN and the signal generation card SGB are provided and arranged to switch between the reception or the Sending at least two consecutively transmitted via serial bus IOCN time synchronization messages or angle synchronization messages perform a calculation of time or angle values.

It can preferably be provided that in the HIL simulator 1 the environment model provided for execution on the computer unit CN comprises a model part for providing master data records for time and / or angle calculation, and the computer unit is provided and arranged to transmit the master data records to the first serial bus.

A further preferred development of the HIL simulator 1 can be designed such that the HIL simulator at least one busbar FR and a fault relay device FRU for producing a switchable connection of at least one control unit port E1, E2, E3, E4 of the control unit ECU to the busbar FR of the HIL simulator 1 includes.

In this case, furthermore, an error insertion unit FIU from the HIL simulator 1 , wherein the fault insertion unit FIU is provided and arranged to make a switchable connection to at least one busbar FR and to switch different fault conditions.

Furthermore, the HIL simulator according to the invention 1 a device for summarizing channels.

In addition, the HIL simulator 1 have a device for residual bus simulation.

According to a further preferred embodiment of the HIL simulator according to the invention, it is provided that the HIL simulator is provided and set up to execute a so-called residual bus simulation synchronously or independently of other simulations, which will be described in more detail below.

An essential prerequisite for the so-called compound test, that is the test of several connected via bus control devices, consists in monitoring the communication between the control units, which takes place by means of known buses and bus protocols such as CAN, LIN or FlexRay.

Here are the behavior in normal operation, so if all control units of the control unit network available, connected to the bus and are functional, but especially in case of failure, z. B. in case of failure of a bus subscriber (in particular a control unit) or in case of incorrect content of the bus messages or electrical errors (short circuits) on the bus lines, particularly important and to test.

If specific control units are initially examined separately by means of the HIL simulator according to the invention or if in a composite test of several control units which are connected to a bus, not all provided control units are present which will later belong to the network, then the so-called residual bus simulation is used in which the missing bus subscribers (especially the missing control devices) are emulated by the HIL simulator.

To execute the residual bus simulation, the corresponding bus interface of the HIL simulator is connected to the bus of the control unit network. Also, prior to running the tests, all communication based on the CAN or LIN or FlexRay database (including the signal scaling) must be specified along with the dynamic behavior, eg. Using the software MATLAB / Simulink ^{® of} the US company The MathWorks.

Usually, when testing ECUs used in automobiles, for example, several hundred messages and thousands of signals are often to be considered.

One of the tasks of the HIL simulator according to the invention can thus consist in the context of the residual bus simulation to provide signals or messages "expected" by one / more controller / e and processed after receipt, but these signals or messages not can be sent from one or more further control units, because this / s further control unit / e, for example, for the test in question is not yet available / ready.

The HIL simulator thus fills the "gap" of the missing signals or messages, this "gap", as indicated above, especially because there may be a normally present but at a test run (not yet) located in the control unit network control unit of its signals and messages to send therefore can not send to the bus.

Assuming that the emulation of the signals and messages to be replaced by means of the HIL simulator (which in particular simulates the missing ECUs) leads to a bus data traffic which is essentially identical to the data traffic in the case of a complete ECU network ( Without one / more missing / s or inoperable / s control unit / s) would be present, it can be assumed that it makes no difference from the perspective of the existing ECUs, whether a signal or a message from the HIL simulator or (in a later test) comes from a controller.

• – Eine sogenannte statische Restbus-Simulation zeichnet sich im Wesentlichen dadurch aus, dass vom HIL-Simulator feste, vordefinierte Werte (Daten) auf den Steuergeräte-Bus übertragen werden. Diese Werte sind in diesem Fall somit nicht in Abhängigkeit von der simulierten Umgebung des Steuergerätes veränderlich. Üblicherweise ist bei der statischen Restbussimulation im Verlauf der Simulation als einzige Einflussnahme lediglich vorgesehen, die Übertragung der vordefinierten Werte seitens des HIL-Simulators auf den Steuergeräte-Bus zu übertragen, die Übertragung zu wiederholen oder zu beenden.
• – Eine sogenannte dynamische Restbus-Simulation zeichnet sich im Wesentlichen dadurch aus, dass die vom HIL-Simulator auf den Steuergerätebus zu übertragenden Werte (Daten) vor der Übertragung mittels eines auf dem HIL-Simulator ablaufenden Modells neu berechnet werden und zwar bevorzugt unter Berücksichtigung des jeweils vorliegenden Zustandes vorhandenen Steuergeräte und/oder deren Funktionalitäten.

The basic sequence of the residual bus simulation described above can essentially be transferred to other buses (in addition to CAN, LIN, FlexRay). Depending on the required complexity of the residual bus simulation and the approach influenced by it, the following categorization can be carried out:

• - A so-called static residual bus simulation is essentially characterized by the fact that the HIL simulator transmits fixed, predefined values (data) to the ECU bus. These values are thus not variable in this case, depending on the simulated environment of the control unit. Usually, in the case of the static residual bus simulation in the course of the simulation, the only influence is merely to transmit the transmission of the predefined values on the part of the HIL simulator to the control unit bus, to repeat the transmission or to end it.
• A so-called dynamic residual bus simulation is essentially characterized by the fact that the values (data) to be transferred from the HIL simulator to the control unit bus are recalculated before transmission by means of a model running on the HIL simulator, preferably taking into account the each existing state existing control devices and / or their functionalities.

A residual bus simulation by means of so-called replay is essentially characterized in that data of a selected bus subscriber, for example telegrams, which transmits a selected control device to a bus (eg a CAN bus) are recorded in advance and preferably in one File are stored (eg in a so-called log file) and then the data of said selected bus station is transmitted by reading this file from the HIL simulator on the bus.

Alternatively, it is possible to have the residual bus simulation not performed by a HIL simulator but by other electronic devices.

As has already been described elsewhere in this text, the HIL simulator according to a preferred embodiment of the invention preferably has a computer unit (English: Computation Node), abbreviated CN; a Signal Generation Board, abbreviated SGB; a power supply unit (power supply or voltage source); a switch card (English: Power Switch Board), abbreviated PSB, which preferably also includes circuit elements for an error insertion unit (English: Failure Insertion Unit), abbreviated FIU; a Signal Measurement Board, abbreviated SMB; and / or a bus card (English: Bus Board).

By way of example, reference is made in this connection to the CN, the SGB, the SMB, the FIU and bus cards, which are developed and distributed by the applicant of this patent. As CN of a HIL simulator, for example, a processor card or a PC or an industrial computer can act. Likewise, a plurality of computers or a plurality of processor cards together or a networked system comprising at least one computer and at least one separate processor card can jointly form the computer unit CN.

Depending on the selection, two or more of the channels of one or more SGB and / or SMB can be combined to form a functional unit, as explained below. The HIL simulator can in principle be equipped without PSB and / or without FIU, but this would usually lead to a limited range of functions of the HIL simulator, if the relevant functions, not by means of other system components, such as by peripheral electrical circuitry , which are arranged outside the simulator, and preferably have a data transmission connection to a CN and possibly to other cards of the HIL simulator, be provided as an alternative.

It can optionally be provided to design a PSB which comprises circuit elements of an FIU in such a way that this PC board can be replaced by a combination of a PSB without circuit elements on the one hand, and a separate FIU board on the other hand, but the separation of the functional elements goes on on two separate boards often associated with a higher spatial footprint. According to a preferred embodiment of the HIL simulator according to the invention, the latter is equipped with a device for combining channels, wherein selected channels can be combined to form a composite channel by means of this device, which is referred to in the following text as a summarizing device, abbreviated ZFV.

Depending on the field of application and technical design, in particular depending on the number of combined channels, the process of combining channels in the art is sometimes referred to as channel bonding.

In the context of this patent application, the "composite channel" is thus understood to mean a channel which arises with the interconnection or with the connection of at least two channels by means of a summary device. However, the summary device of the HIL simulator is preferably not only provided and arranged to summarize channels, but it is also part of the scope of the summary device to separate the composite channel or channels. The term "separation" is thus to be understood as the separation of at least one channel from a composite channel.

As well as the non-composite ("normal") channels, the gatherable channels may also be particularly provided and arranged to provide analog or digital electrical signals to provide electrical currents and voltages to actuators or sensors, to circuit breakers, especially those whose maximum current value to be transmitted is above a defined value (for example, 1 ampere) to provide simple or complex timed and / or angularly controlled current and / or voltage waveforms, and / or to provide ohmic, inductive, capacitive, or composite loads This patent right claim under a "compound load" is to be understood as meaning an electrical load which is composed of measurable ohmic and / or inductive and / or capacitive components.

Preferably, in the HIL simulator assembled electrical loads are provided which have electrical characteristics, in particular an ohmic resistance, an electrical capacitance and an inductance, which essentially correspond to the electrical characteristics of the "real loads", whereby under a "real load In particular, an electrical component or an electrical unit (for example, an electric motor, a piezoelectric actuator or a solenoid valve) is to be understood, which is or are provided, for example, to be electrically connected to a control device and possibly also via optical fibers and preferably also to utilize energy and / or data, which originate from the control unit.

In addition, both the non-composite ("normal") channels and the summarizable channels may be provided and arranged to measure physical quantities, such as currents, voltages, times between events, frequencies, etc. Preferably, the individual channels are electrically isolated from each other, but can preferably be galvanically connected again by the summary device.

A further preferred embodiment of the channels provides that these are protected by means of electronic protection circuits to avoid overloading the channels, in particular by currents which are above the specified values.

Optionally, instead of or in addition to the electronic protective circuit, one or more fuses or self-resetting thermal fuses (eg multifuse fuses) or electromechanical fuses may be provided to protect the channels.

Furthermore, the HIL simulator according to the invention can have a configuration software and / or a configurable electronic component, by means of which a tripping limit value (English: trigger value) for electronic protection circuits for securing the channels is adjustable or configurable. Optionally, a channel may have multiple overload protection devices simultaneously, with a combination of at least two or all of the protection devices protecting that channel, namely the fuse and / or the electromechanical fuse and / or the software-side configurable protection circuitry and / or the hardware configurable or exchangeable protective circuit.

One or more channels can preferably be assigned a so-called "Failure Routing Unit", abbreviated FRU. Under a FRU here is a device to understand the one Channel or multiple channels with a busbar for the error simulation (English: Fail Rail), abbreviated FR, or multiple busbars FR1, FR2, ..., FRn for fault simulation electrically conductively connect, the busbar FR preferably with the FIU, which is described elsewhere in this application, electrically conductively connected. Thus, a channel is preferably via FRU and via FR with an FIU electrically connected.

A preferred embodiment of the HIL simulator according to the invention comprises at least two bus bars FR or at least two electrically conductive wires FR11, FR12, FR21, FR22 which differ in at least one electrical property, such as the electrical resistance lining, the capacitance surface and / or the dielectric strength.

For example, it is possible to provide simulation scenarios in which a plurality of signal channels, which are combined to form a combined channel, are preferably time-synchronized via FRU and via summarized FR, consisting of FR1, FR2,..., FRn, and via FIU with an electrical fault potential taking advantage of the fact that the optionally adjustable high current flowing between the combined channel and FIU is distributed among the FR1 to FRn.

Thus, in these simutation scenarios, an overload of a FR at higher currents within the specified limits can be counteracted.

The example of channels of a SGB will now be explained in more detail how and for what purpose a summary device in a HIL simulator is preferably used. By way of example, it should be assumed that a first and a second signal channel of a SGB are provided, wherein both these two individual signal channels each provide a so-called sawtooth signal of a tilting oscillator.

It should be further assumed that, for example, the maximum current value of a single signal channel is limited to a maximum of 300 mA, for example, not to overload the Kippschwinger or to prevent, for example, the triggering of an electrical fuse a single channel. In addition, assume that it is necessary for a simulation scenario to provide a sawtooth signal with a maximum current of 500 mA.

This task would not be solvable with a single channel under the boundary conditions of this example, because this channel alone is not specified for the required maximum current and is not dimensioned.

However, according to the aforementioned further preferred embodiment of the HIL simulator according to the invention for the above-described application, the summary device offers the possibility of obtaining the sawtooth signal with the maximum current of 500 mA from the addition of two partial currents.

This can be achieved, for example, by two separate signal channels each synchronously providing a sawtooth signal with a partial current with a maximum of 250 mA and the summary device combines by parallel connection the two partial currents to a total current which is a maximum of 500 mA.

An embodiment of the SGB can provide that the signals that can be provided by the SGB are specified as a so-called wavetable, abbreviated WT, sometimes also referred to as a signal value table.

The person skilled in the art has known for several decades how virtually any desired signals can be generated by means of stored waveform tables WT, see, for example US Pat. 4133241 , which is why in this description text to details can be omitted.

The method of signal synthesis by means of WT is known to be used not only in electronic instruments, but in particular also for simulation applications or, more generally, for test applications.

In test and simulation applications in the automotive industry, in mechanical engineering and in aerospace, WT signal synthesis is used, for example, to generate signals, in particular current and voltage waveforms as a function of physical variables (eg temperature, rotational speed, Speed, acceleration, etc.), these signals being, for example, the sensor signals in the Substantially similar, and can serve as an input signal of controllers, signal processing devices, etc.

In addition to the preparation by means of mathematical calculation, a WT can also be obtained by means of electronic recording from a known signal source, optionally followed by a signal change (eg filtering out of harmonics or interference signals) following the recording of the signal WT is stored in the final version and provided for signal synthesis.

In accordance with a further preferred embodiment of the HIL simulator according to the invention, the latter has one or more current sinks (software: current sinks), abbreviated "CS". A further preferred embodiment of the HIL simulator can comprise at least one combined current sink current source, abbreviated to "CSS which can be controlled via software.

The current value, which is affected by the current sinks, can either be either constant or variable, depending on the settings using the configuration software. In particular, the current value, which is influenced by current sink, depending on a time value or an angle value or both the time values and the angle value (for example, crankshaft angle or camshaft angle of an internal combustion engine or the internal combustion engine model) may be changeable, which means in these cases, the following functional dependencies exist: a) Ics = function (time) or b) Ics = function (angle) or c) Ics = function (time, angle). Comparable functional dependencies may also exist for the combined current sink power source.

In order to achieve higher current values, it may be provided to connect several current sinks in the HIL simulator by means of the summary device. However, the summary device of the HIL simulator according to the invention can not only be provided to summarize channels for the purpose of adding the individual streams of individual channels, but the summary device can in particular to achieve higher voltages or increase the so-called bus width, ie to increase the number of Data paths of a bus to be used.

A voltage increase can be achieved in particular by means of the combining device by way of the series connection of two individual voltage supply channels or signal channels. An increase in the bus width of a parallel bus, which consists of at least two individual bus channels can be achieved in particular by means of the summary device, these at least two individual bus channels are operated in parallel after their summary and preferably synchronized with each other.

For different reasons, an absolutely symmetrical loading of the individual channels of a composite channel is generally not feasible or not with economically justifiable effort in terms of circuit complexity representable or even unintentional in certain applications.

For example, in the case of a composite signal channel or power supply channel, for reasons of circuit technology there is usually an asymmetrical current distribution with regard to the individual channels, which are connected to one another by the said summarizing device.

The causes of these asymmetries may be, for example, in the manufacturing tolerances or deviations of the electronic components, which are inevitable even with identically constructed electrical circuits of the channels in the rule. Based on an exemplary case in which a connected channel comprises two power supply channels, will be illustrated below, as an unbalanced load in the control or regulation of associated with the associated channel two individual channels can be considered.

For this example case, it should further be assumed that each of the two individual channels is dimensioned for a maximum current of 10A. Without taking into account the unbalance of the connected channel, this would result in a maximum current of 20 A for it.

However, considering the imbalance requires a reduction of the maximum current of the connected channel. Depending on the circuitry realization, it may be appropriate to use a Discount of, for example, 1% to 30%, preferably 20%. Taking into account the preferred discount results in the example case that of the said 20 A, a deduction of 20%, ie 4 A, takes place.

This results in a maximum current of 16 A for the connected channel. A power control associated with the individual channels or the connected channel would, in the case described, preferably automatically ensure that the load of the connected channel does not exceed the limit of 16 A.

Should it be necessary to provide a current of 20 A under the same conditions with regard to the individual channels, then, as already described, then a third individual channel would have to be added to the connected channel.

In a comparable way as the already described connected signal channels or channels of the power supply unit are used in the HIL simulator in order to be able to provide the user-required current values more flexibly, it is provided according to a further preferred embodiment of the HIL simulator according to the invention, connect two or more individual measurement channels of a Signal Measurement Card (SMB) to a connected measurement channel.

For example, a connected current sense measurement channel, which includes two individual current sense channels connected in parallel, may be configured to measure higher currents than those which a single current sense channel would be able to measure in accordance with its circuitry design and dimension. According to a further preferred embodiment of the HIL simulator according to the invention, the latter has at least one switch card whose channels have in particular the task of having at least one current or voltage source which can be connected to one of the channels with at least one consumer or one connect electrical load or separate this consumer or this electrical load from the power source or voltage source.

Such channels can preferably be operated in parallel on the switch card, whereby a connected channel for switching, comprising two or more individual channels for switching, can be realized. By means of this parallel connection, it is possible, in particular, to switch higher currents than would be possible or permissible without this parallel connection.

Multi-processor systems, abbreviated to MP systems, have been common for use as computer units in HIL simulators for many years in order to scale both the computing power and the I / O performance.

It is known that usually the division of the computing processes into several processors increases the computing power in comparison to the calculation on a processor of the same category.

It can also be provided that each of the processors can access its connected I / O independently via short, low-latency and broadband connections. The clear separation of the processors which is typical for MP systems is particularly advantageous here: essential resources of the processors, such as cache and interrupt controllers, are not shared, for example, which has a limiting effect if the number of I / O accesses is too large.

Added to this is the modularity possible with MP systems. For example, test systems for individual control units or vehicle domains can be interconnected to composite simulators. The overall performance-critical communication between the processors within an HIL simulator or within a composite simulator comprising multiple networked HIL simulators is through dedicated bus connections.

The configuration of the communication preferably takes place within the simulation with MP extensions of the software model, as well as the distribution of the overall model and the distribution of the tasks to the individual processors.

In order to obtain optimal overall performance, it may be preferable for each of the individual models u. a. the simulation step size, the integration algorithm and trigger conditions are set individually.

A similar approach is also applicable to multi-core processor boards, abbreviated MC processor boards, whose individual processor cores can internally exchange data over very fast connections, for example via a shared memory. The user can so the individual processor cores of a multi-core processor connect the processors in a multiprocessor system and also seamlessly couple several of these systems together. In addition, MP systems can also consist of mixed multi-core processors and single-core processors.

For communication between multiple processor boards usually bus connections are used. The data exchange between tasks on different processor cores or different processor boards is configured by the user with special simulation blocks.

The programming interface of the simulation blocks is often uniform, even if the subordinate communication is usually realized physically different, in particular with respect to the internal processor communication within the multi-core processors on the one hand and the bus connections between processor boards on the other hand.

This achieves consistency in the scaling of the computing power for MC and MP systems. For MC processors, it is typical that the performance of the common I / O interface does not increase to the same extent as the computational power. In the case of real-time simulations with a large number of I / O accesses, this can lead to losses in the performance of the computer unit. Because of their clear separation of processor resources, MP systems are often superior to MC processors in some I / O-intensive applications.

Nevertheless, MC systems can advantageously be used for many computation-intensive real-time simulations, in particular also for those in which a comparatively high data exchange rate between the computer unit and the I / O card or I / O cards is required.

A special feature is the synchronous multitasking in an MC processor. It is not specified by the user which processor core should perform which task, but an internal planning unit usually integrated in the processor, often referred to as a scheduler, autonomously distributes the computational load the individual processor cores. This approach has the advantage that the simulation model does not need to be split by the user for calculation on multiple processor cores.

The individual processor cores of an MC system can also be used for completely different tasks. For example, a processor core may be designated to process only the communication of the HIL simulator with the host system, and the remaining processor cores may be available only for the simulation model calculation.

This has the advantage that the calculation time of the simulation model, which is critical in real-time calculations, is not or only insignificantly influenced by the communication with the host.

It is also possible to run different operating systems on the processor cores of an MC or MP system. For example, in one MP system on one processor, the host system software can run and on another processor a real-time operating system and the calculation of the simulation model, in particular the environment model.

This distribution is also applicable to the individual processor cores of a processor in MC systems. Thus, in a processor with two processor cores on one processor core, the host system can operate and on the other processor core a real-time operating system.

On a processor with more processor cores, several different operating systems may each be assigned to one processor core, or an operating system may be assigned multiple processor cores to which the operating system can distribute its workload. If, for example, the computing unit of the HIL simulator comprises an MC processor in which at least one processor core for the execution of the host system software under a standard operating system, such as Microsoft Windows 7, is provided, and at least one further Processor core executing real-time application programs under a real-time operating system, this can make a separate host computer, which was previously commonly used for the operation of the real-time computer, superfluous.

The common types of work distribution among the processor cores of an MC processor can be classified as follows: Asymmetric multiprocessing (AMP) - Each processor core runs a separate operating system, abbreviated OS (operating system), or a separate installation of the same OS.

Typically, each software process is tied to a single processor core. Symmetric Multiprocessing (SMP) - A single OS operates all processor cores simultaneously. The OS can dynamically run any process on any available processor core, allowing full utilization of all processor cores. Bundled Multiprocessing (BMP) - Similar to the SMP, a single OS also operates all processor cores simultaneously, but it can limit individual processes to a specific processor core.

AMP provides better compatibility with legacy code, with SMP providing more concurrency and resource management. BMP combines the best of both methods. Just like with SMP, a single OS installation has the "overview" of all system resources. However, BMP goes one step further by allowing developers to limit processes and their threads to a specific core processor.

This approach allows the use of legacy application software without the need to invest a relatively large amount of time to modify this legacy application software to adapt to a multi-core environment. This approach also allows newer applications to take full advantage of parallel processing and dynamic load balancing through multi-core hardware.

An MP system can also be used to connect processors with different architectures. For example, the so-called x86, PowerPC and MIPS architectures may be mentioned in this context. Since some computational tasks can be executed with different efficiency on different processor architectures, it is therefore possible to implement a method on the MP system that assigns the respectively most suitable processor (s) to the respective computation tasks, which leads to a performance increase of the HIL simulator can lead.

Detailed information on MP and MC systems can be found in ATZ Elektronik ( Himmler, A., "Modular, Scalable Hardware-in-the-Loop Systems," ATZelektronik worldwide 5 (2): 36-39, 2010 ).

In a further embodiment of the invention, the connection of so-called real loads and equivalent loads, which simulate only the electrical characteristics of a real load, is provided.

As real load is often an electrical or electromechanical module, for example, a sensor or an electric motor, referred to, this module is in the later field of application of a control unit ECU, connected to this, for example, to transmit sensor signals to the controller or as influenced by the controller actuator act.

A substitute load is often also an electrical or electromechanical module, for example an electromagnet or an adjustable or non-adjustable ohmic resistor or a capacitor or an electrical circuit structure comprising resistors, capacitors and / or coils, which are essential in a simulation, in particular electrical , Property of a corresponding real load comes close. For example, for simulation purposes, an ohmic resistor acting as a surrogate load can replace a sensor (real load).

For simulations, real or equivalent loads are often used when their mathematical modeling is too costly or a mathematical model of real or spare load does not sufficiently match their behavior in interaction with a ECU.

Real loads are preferably connected externally to the HIL simulator, since in particular the spatial limitation through the housing or the slots or drawers of the HIL simulator need not be considered. For example, spatially large real loads, in particular large electric motors, can be externally connected to the HIL simulator. If the spatial extent of the real loads or equivalent loads allow, they can alternatively also be arranged within the HIL simulator, in particular also within a wiring drawer of an HIL simulator.

Real loads are preferred to the HIL simulator and not directly to the ECU to be tested. ECU connected in order to be able to carry out the error simulation (see text section on FIU and FRU) even under real load. In a further embodiment of the invention replaceable load drawers are provided for the HIL simulator, in which, for example, all replacement and real loads for the test of different control devices are.

If a load adaptation on the HIL simulator has to be made at all for the test of different control devices, this adaptation can therefore preferably take place by replacing a load drawer of the HIL simulator.

In addition, an HIL simulator may have so-called break-out boxes and / or so-called load cards with equivalent loads that do not have to be changed when changing the variant of a control unit.

In an advantageous embodiment, individual units or modules of the HIL simulator are designed as drawers. In this way, the simulator can be quickly converted to different requirements.

For example, wiring elements of the wiring of the simulator may be arranged within a drawer. In this way, especially with an adaptation of the internal wiring only the exchange of prepared drawers is necessary and not a single change of many cables.

This saves a tremendous amount of time in adapting the simulator to new requirements, such as testing another ECU. Such replaceable drawers, which may be located within the simulator housing and include wiring elements of the HIL simulator wiring, will be referred to as "wiring drawer" hereafter.

On the outer sides and / or inner sides of the wiring drawers, connections (connection sockets and / or connection plugs) for special external hardware, so in particular peripheral external loads or, for example, control devices that can be connected to the HIL simulator can be located.

In order to create or change the connectivity for special hardware, it is only necessary to exchange prepared drawers adapted to the specific hardware mentioned above.

Real loads can also be built into drawers. When replacing real loads of one, such as throttle valves of an internal combustion engine, only the replacement of prepared drawers is necessary and not a single change of many connections.

According to an advantageous embodiment of a wiring drawer for the HIL simulator so in particular the wiring adjustments to the real loads within the associated drawer are provided and consequently a wiring change outside this drawer after a drawer replacement usually superfluous or at least less extensive than without such a wiring drawer would.

To test the correct or desired function of control units when electrical faults occur, these faults are preferably included in the simulation.

For this purpose, for example, electrical inputs or outputs of a control unit ECU by means of an HIL simulator 1 short-circuited to the ground potential, abbreviated GND, or to a supply voltage terminal POT or other inputs or outputs of the control unit or the HIL simulator.

According to a further advantageous embodiment of the HIL simulator according to the invention 1 includes this as in 3 schematically illustrated in a simplified form, a combination of at least one so-called error forwarding device FRU, the in 3 are shown as dashed boxes within the two I / O cards (abbreviated: I / O-Bs), at least one busbar FR, and at least one fault introduction unit FIU.

Furthermore, in this exemplary embodiment of the HIL simulator 1 according to 3 the fault introduction unit FIU be connected to at least one switch card, also referred to as PSB, wherein it can alternatively also be provided that the switch card and the fault insertion unit in a component, in particular within a map, are united. Preferably, the switching states of the switches of the embodiment according to 3 , which may be embodied in particular as a semiconductor switch (for example transistors) or as relay components, of one or more computer units CN (in 3 not shown) and / or of microprocessors or FPGA components (in 3 not shown) on the input / output boards, also called I / O boards I / O-Bs, of the HIL simulator 1 controllable.

3 schematically shows a simplified illustrated to be tested ECU ECU, which is connected via a plurality of controller terminals E1, E2, E3, E4 with I / O cards of the HIL simulator.

The controller terminal E6 is connected to the ground potential GND of a power supply BAT, which may be designed in particular controlled power supply or as a battery. The control unit connection E5 is connected to the supply voltage connection POT of the power supply BAT. The switch S7, which is preferably arranged on a switch card, also called PSB, establishes in its second switch position a connection from the switches S2, S3, S5, S6 to the ground potential GND and thus also to E6.

In the first switch position of the switch S7, a connection is established by the switches S2, S3, S5, S6 to the supply voltage connection POT and thus also to E5.

To the I / O cards, also referred to as I / O-Bs, of the HIL simulator 1 In particular, the signal generation board SGB and the signal measurement board SMB, as well as other maps, enable the HIL simulator to exchange signals with the connected ECU ECU.

The signals can preferably be transmitted not only by means of electrical lines but also in particular with the aid of optical waveguides.

In an I / O card of the type described above, a failure routing unit (abbreviated as FRU) may be installed. With the error forwarding device FRU, the circuit, the example in 3 From the ECU terminals E1 and E2 or E3 and E4 emanates, be redirected to a busbar FR. The channels KE1, KE2 guided by the control unit terminals E1 and E2 of the control unit ECU to the upper illustrated I / OB form, with the first switch S21 closed and the second and third switches S20, S22 open, a circuit through an I / O functional unit IOFU1 which preferably simulates an element of the ECU environment, such as a sensor or a resistor.

Similarly, the connection from E3 and E4 to the lower I / O card I / OB is according to 3 and E3 and E4 can be assigned to a second I / O functional unit IOFU2. Out 3 shows that by means of the switches S20 and S22 of the upper fault relay FRU a connection to a first double-core line FR1 can be produced. Similarly, switches S30 and S32 are associated with the second double-core line FR2.

The electrically conductive wires FR11, FR12, FR21, FR22 are electrically insulated from each other. They are preferably realized as printed conductors on a card or as flexible or rigid cables.

The busbar FR preferably comprises at least two double-core lines FR1 and FR2. An error forwarding device FRU of an I / O card I / OB preferably consists of three switches, in 3 denoted S20, S21, S22 and S30, S31, S32, respectively.

A first switch S21 is used to interrupt the original circuit. This first switch S21 is preferably designed as a relay. The design as a relay causes the broken line has a free potential, a version as a semiconductor switch, however, would allow a normally unwanted capacitive coupling of the separate lines in the open state.

Starting from the ECU connection E1 in 3 For example, a second switch S20 is disposed before the first switch S21, and a third switch S22 is disposed behind the first switch S21. Via the second switch S20 and the third switch S22, the current can be diverted to a respective one wire of the busbar FR.

In the example according to 3 the busbar FR consists of two electrical double-wire lines FR1 and FR2. Preferably, the electrically insulated wires FR11 and FR12 associated with the double-core line FR1 have different electrical characteristics than the other electrically insulated wires FR21 and FR22 associated with the double-wire line FR2.

According to a preferred embodiment of the invention, the electrical properties of the busbar FR and the double-core lines FR1 and FR2 or their wires to the devices to be connected, or to the operating conditions during the ECU test in particular with respect to the line coverings (Resistance, capacity, etc.) are available, adjusted. By software, the switch positions on the I / O-Bs and the error insertion unit and thus also the wires for the different simulations are preferably selectable.

The busbar or one of the associated double-wire lines or their cores may be designed, for example, in such a way that comparatively high currents can be forwarded without risking damage to the busbar, or that a particularly low capacitance of one or more cores or cores ., If necessary connected thereto semiconductor switch is present, or that one of the double-core lines has a comparatively high dielectric strength.

Based on the schematic representation according to 3 It can be seen that the signals which originate, for example, from one of the control unit connections E1 to E4, can be routed to a fault introduction unit FIU via the busbar FR.

With the error insertion unit FIU various errors can be generated. If no fault is to be generated, then only one circuit is produced from one control unit connection via an I / O functional unit to another control unit connection, that is, for example, from E1 via IOFU1 to E2. Preferably, a computer program which is executed on the HIL simulator according to the invention, controls all switches, the 3 are shown, including the semiconductor switches S1 to S6.

Depending on the switch positions on: the I / O-Bs or the error forwarding devices FRU located there, the fault insertion unit FIU, the switch card, in 3 referred to as PSB, various errors are simulated for the test of the ECU.

Depending on which type of connection cable is to be occupied by a simulated error, it may be provided to adapt the switching sequence.

If, for example, the control unit connection E1 is a connection to a bus, for example a CAN bus, then the following switching order may be provided: First, the fault is prepared by means of the fault introduction unit FIU by preceding the corresponding switches of the fault introduction unit FIU in accordance with the error to be simulated are switched to the desired switching states, and only then the signal of the bus terminal E1 via second switch S20 of the error relay device FRU and via busbar FR, more precisely, the electrically conductive wire FR11, passed to the fault introduction unit FIU.

This is advantageous because the rerouting of a single bus line via the fault insertion unit FIU can already lead to the disturbance of the bus transmission due to the line length, as well as additional parasitic effects such as resistors or capacitances.

The fault insertion unit FIU consists of a plurality of switches, for example, as in 3 can be connected to each other. In the following, the mode of operation of an error entry unit FIU will be explained on the basis of an exemplary embodiment.

One of the simulated errors is a line break. To simulate this error, the circuit in the fault insertion unit FIU is interrupted by means of a switch S1 or S4 after the construction of the circuit via the busbar FR and the fault insertion unit FIU. These switches are preferably designed as a semiconductor switch. A semiconductor switch has the advantages over a relay that it does not bounce and can be relatively comparatively quickly and comparatively precise in time.

In a comparable manner, in addition to a cable break, it is also possible to simulate a loose contact by, for example, repeatedly opening and closing the switch S1 and / or the switch S4 in a chronologically predefined sequence.

Another simulatable fault is a short circuit of an I / O channel, for example a channel originating from the control unit connection E3, against a supply voltage connection POT. In order to simulate this error, the connection to the busbar FR, more precisely to the wire FR21, is initially established via the switch S30, for example. Subsequently, a conductive connection to the supply voltage connection POT is created via the switches S5 and S7.

In this starting position would have to simulate a short circuit of ECU terminal E3 to ground potential GND according to the example circuit according to 3 only the switch S7 are switched to its other switch position. Further embodiments, not shown, may provide that, starting from the busbar FR, a connection to further terminals with different potentials (eg POT2, POT3, both not shown) can be produced. Another simulatable fault is a short circuit between two I / O channels, especially between two channels of a control unit ECU.

According to the embodiment 3 will be explained below, such as the outgoing from the ECU terminals E1 and E3 I / O channels using HIL simulator 1 can be shorted. In the example considered here, the signal originating from the controller terminal E1 is conducted to the wire FR11 of the busbar FR by means of the closed second switch S20 of the upper I / O-B. The first switch S21 of the upper I / O-B is opened in this case. In addition, the signal originating from controller terminal E3 is conducted to the wire FR21 of the busbar FR by means of the closed second switch S30 of the lower I / O-B.

The first switch S31 of the lower I / O-B is opened in this case. The actual short circuit simulation between the two I / O channels, from E1 and E3 of the controller to the HIL simulator 1 are guided, is completed after the preparatory steps described above by closing the switch R5 of the error-introducing unit FIU.

Further fault simulations can be realized by further combinations of the switch states on the error routing devices FRU, on the fault injection unit FIU and / or on the switch board. Combined list of reference symbols / abbreviations and technical terms in German and partly in English Abbreviation and reference numbers English German ADC analog / digital converter Analog to digital converter AMP asymmetrical multiprocessing Asymmetric multiprocessor method board (generic term for printed circuit boards isertable into the HIL simulator) Map (generic term for the printed circuit boards with which the test system can be equipped) BAT voltage source Power supply (for example as a controlled power supply or as a battery) BMP Bundled multi-processor process for example. for example for example CAN Controller Area Network CAN CBU unit for channel bonding or channel bonding apparatus Summary device or device for combining channels CN computation node computer unit CO connector connector CS Current sink current sink CSS Current sink / source Combined current sink power source E1, E2, ... E6 Control unit connector ECU electronical control unit control unit IT embedded system Embedded system FIU failure insertion unit Error insertion unit FR fail rail Busbar or electrical conductor which is connectable to the FIU and the FRU FR1, FR2 Double-core cable FR11, FR12, FR21, FR22 veins FRU failure routing unit Error forwarder GND Ground ground potential HIL Hardware-in-the-Loop Hardware-in-the-loop HPC host computer Host computer I / O input / output Input / Output I / OB I / O board or I / O card Input / output card MTN first serial bus first serial bus IOFU I / O function unit I / O functional unit IOFU1 I / O function unit 1 I / O function unit 1 IOFU2 I / O function unit 2 I / O function unit 2 core core Processor core LAN local area network Local network MC multicore Multi-Core OS operating system operating system MP multiprocessor Multi-processor PL plans (word used in control theory) Controlled system (term in the context of control engineering) PSB power switch board switch card POS power supply Power supply unit POT connection to operating voltage Versorgungsspannunsganschluss PWM pulse-width modulation Pulse Width Modulation RT real time real time R4, R5, ... R9 switch Switch, from the FIU includes and preferably realized as a relay S1, S2, ... S6 switch Semiconductor switch, comprising of FIU S7 switch Semiconductor switch, covered by the switch card (PSB) S20 switch second switch of the upper I / O card acc. Fig. 3 S21 switch first switch of the upper I / O card acc. Fig. 3 S22 switch third switch of the upper I / O card acc. Fig. 3 S30 switch second switch of the lower I / O card acc. Fig. 3 S31 switch first switch of the lower I / O card acc. Fig. 3 S32 switch third switch of the lower I / O card acc. Fig. 3 sawtooth signal Sawtooth signal scheduler planning unit SGB signal generation board Signal generation map SMB signal measurement board Signal measuring card SM symmetrical multiprocessing Symmetric multi-processor method relaxation oscillator relaxation oscillator target computation unit Target computer (eg computer unit of a control unit ECU) trigger value Tripping limit WT wavetable Waveform table ZFV channel bonding unit (for channels) Summary device 1 HIL simulator HIL simulator 2 real load Real load 3 backplane Printed circuit board with connectors for receiving additional cards 4 cable harness harness 5 cable electric wire 10 second serial bus second serial bus 12a 12b Interface to the first serial bus Interfaces to the first serial bus (IOCN) 20 Chassis of the HIL simulator Housing of the HIL simulator

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 4133241 [0085]

Cited non-patent literature

• www.mathworks.com/products/simulink [0010]
• Himmler, A., "Modular, Scalable Hardware-in-the-Loop Systems," ATZelectronics worldwide 5 (2): 36-39, 2010 [0125]

Claims (10)

Device for testing at least one electronic control unit (ECU), this device comprising - at least one computer unit (CN) for executing at least one environment model, and - at least one signal generation board (SGB) for providing at least one signal for the electronic control unit (ECU) , and - at least one serial bus (IOCN) for bidirectional data transmission from the computer unit (CN) to the signal generation card (SGB) or vice versa, and wherein both the computer unit (CN) and the signal generation card (SGB) each have at least one interface ( 12a . 12b ) to the serial bus, and these interfaces ( 12a . 12b ) are arranged and arranged to receive and / or transmit time synchronization messages as well as angle synchronization messages. HIL simulator ( 1 ) comprising a device for testing at least one electronic control unit (ECU), said device comprising - at least one computer unit (CN) for executing at least one environment model, and - at least one signal generation board (SGB) for providing at least one signal for the electronic control unit (ECU), and - at least one serial bus (IOCN) for bidirectional data transmission from the computer unit (CN) to the signal generation card (SGB) or vice versa, and wherein both the computer unit (CN) and the signal generation card (SGB) at least an interface ( 12a . 12b ) to the serial bus, and these interfaces ( 12a . 12b ) are arranged and arranged to receive and / or transmit time synchronization messages as well as angle synchronization messages. HIL simulator ( 1 ) according to claim 2, characterized in that the serial bus (IOCN) is an Ethernet connection. HIL simulator ( 1 ) according to claim 2 or 3, characterized in that the time synchronization messages and / or the angle synchronization messages from at least one network protocol of a network protocol stack of the serial bus are included. HIL simulator ( 1 ) according to one of claims 2 to 4, characterized in that both the computer unit (CN) and the signal generation board (SGB) are provided and arranged to switch between the reception or the sending of at least two consecutively via serial bus (IOCN). transmitted time synchronization messages or angle synchronization messages perform a calculation of time or angle values. HIL simulator ( 1 ) according to one of claims 2 to 5, characterized in that provided for the execution on the computer unit (CN) environment model has a model part for providing master data sets for time and / or an angle calculation, and the computer unit is provided and set up to transfer the master records to the first serial bus. HIL simulator ( 1 ) according to one of claims 2 to 6, characterized in that the HIL simulator at least one busbar (FR) and a fault-forwarding device (FRU) for producing a switchable connection of at least one controller terminal (E1, E2, E3, E4 ) of the control unit (ECU) to the busbar (FR). HIL simulator ( 1 ) according to claim 7, characterized in that the HIL simulator comprises a fault insertion unit (FIU) which is provided and arranged to make a switchable connection to at least one busbar (FR), and to switch different fault conditions. HIL simulator ( 1 ) according to one of claims 2 to 8, characterized in that the HIL simulator comprises a device for combining channels. HIL simulator ( 1 ) according to one of claims 2 to 9, characterized in that a device for residual bus simulation is included by the HIL simulator.

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