DE102020131260A1 - Procedure for performing a test run with a test object - Google Patents

Abstract

The present invention relates to a method for carrying out a test run with a test object and a test bench for operating a test run with a test object. The overall model to be modeled is divided into sub-models, with functional sensor model units taking on the specific tasks of the associated sub-models and can be placed together with the associated digital-to-analog converters in the immediate vicinity of the associated test object signal inputs of the test object

Description

The present invention relates to a method for carrying out a test run with a test object and a test stand for operating a test run with a test object.

In a hardware-in-the-loop method (HiL method), test object signal inputs of a test object are connected to test outputs of a corresponding HiL test bench and test object signal outputs of a test object are connected to test inputs of the HiL test bench. The test object can include control or regulation hardware and is also referred to as a device under test (DUT). An overall model is modeled on the test bench using a central overall model unit. The central overall model unit can include one or more FPGAs and/or one or more real-time-capable PCs, which, however, are arranged in close proximity to one another. The central overall model unit of the test bench interacts with test object signal connections (test signal inputs and test signal outputs) of the test object via special test connections (test outputs and test inputs). Digital test signals to be controlled or regulated in a digital manner are emulated by the central overall model unit of the test stand. The digital test signals are converted to analog test signals using digital-to-analog converters and made available to analog test item signal inputs of the test item via the test outputs. Furthermore, analog test specimen signals are output from analog test specimen signal outputs of the test specimen. These are received via test inputs and converted to digital test specimen signals using analog-to-digital converters so that they can be received by the central overall model unit and processed for digital emulation of the test signals in accordance with the modeling of the overall model.

The electrical interconnection of all the described components, ie the central processing unit and also FPGAs and/or PCs within the central processing unit, the digital-to-analog converter, the analog-to-digital converter and the test object is carried out in the prior art, for example in the documents CN204086979U , CN102110010A , DE 102010043661 A1 exclusively via copper wires or connectors.

Furthermore, the use of a test bench leads in particular to long and therefore interference-prone cable paths between the digital-to-analog converters at the test outputs of the test bench and the test object signal inputs of the test object, as well as between the test object signal outputs of the test object and the analog-to-digital converters at the test inputs of the test bed. This is because the DUT signal connections (DUT signal inputs and DUT signal outputs) of the DUT are often not in close proximity to each other, unlike the test bench test connections (Test outputs and test inputs). This leads to significant problems in terms of signal integrity, particularly since analog DUT signals and test signals are transmitted via these line paths.

Hardware-in-the-loop test benches according to the prior art are also characterized by a long processing time as a result of the digital-to-analog conversion of the test signal. It is therefore not possible, or only possible in a very imprecise manner, using known test benches, to model overall models including semiconductor switches. For example, each semiconductor switch can be emulated by an IC (Integrated Circuit), which is very expensive on the one hand and also inflexible, since a new IC is required for each semiconductor switch to be emulated. If the behavior (impedance) of the semiconductor switch is not emulated, an associated gate driver of the test object must be removed. This represents a serious intervention in the test item and also significantly reduces the quality of the test run.

Methods for analog emulation of power semiconductors are known from the prior art, but these can only be parameterized by hardware changes, for example by changing the ICs on the test bench, and are therefore unusable for flexible test benches, see for example Qi, Analog IC Design for Real-Time Simulation of Power electronic circuits, IEEE 2008.

It is an object of the present invention to specify a flexible hardware-in-the-loop method and a flexible hardware-in-the-loop test bench, with the disadvantages mentioned above being able to be reduced or avoided on the test bench, an overall system to be modeled is divided into a number of subsystems, with at least one subsystem being modeled by a sensor model unit, one subsystem being modeled by a digital emulation circuit and one subsystem being modeled by a main submodel unit, with the main submodel unit being modeled with the sensor model unit to carry out the test run and the digital emulation circuit each communicate via signal connections, wherein the at least one sensor model unit emulates a digital test signal, which is converted into an analog test signal and transmitted to the test object, and wherein an analog test object signal received from the test object is converted into a digital test object signal, transferred to the digital emulation circuit and used to model the associated subsystem.

The object is also achieved by a test bench, with a number of sensor model units, a digital emulation circuit and a main partial model unit being provided, each of which is designed to model a subsystem of an overall system, with the main partial model unit and the number of sensor model units each being connected via signal connections and the main sub-model unit and the digital emulation circuit are connected via a signal connection in order to respectively communicate in order to carry out the test run, the number of sensor model units each being designed to emulate a digital test signal, a number of digital-to-analog converters being provided which each are designed to convert the associated digital test signal into an analog test signal and to transmit it to the test specimen, with an analog-to-digital converter being provided, which is designed to receive an analog test specimen signal from the test specimen, into a digit to convert the test sample signal and to transmit it to the digital emulation circuit, and wherein the digital emulation circuit is designed to model the associated subsystem using the digital test sample signal.

According to the invention, the overall model to be modeled is divided into sub-models, which means that instead of a central overall model unit, a number of functional sensor model units, a digital emulation circuit and a main sub-model unit are used, with further sub-models of the overall model also being able to be modeled using further sub-model units. The functional sensor model units each take on specific tasks of the associated sub-models and can be placed together with the associated digital-to-analog converters in the immediate vicinity of the associated test object signal inputs of the test object. The digital emulation circuit is configured to model the associated subsystem using the digital DUT signal and can be placed together with the associated analog-to-digital converter in close proximity to the associated DUT signal output of the DUT. Since the electrical connecting lines between the digital-to-analog converters and the test object and between the test object and the analog-to-digital converter are kept as short as possible, the signal integrity is compromised as little as possible. The digital signal connections between the main part model unit and the sensor model units and the digital emulation unit are much less susceptible to interference than electrical connection lines.

The main partial model unit preferably transmits partial model output variables and/or parameters to the sensor model unit and/or to the digital emulation circuit via the associated signal connection.

Furthermore, the digital emulation circuit and/or the digital emulation circuit can transmit a partial model output variable to the main partial model unit via the associated signal connection.

The analog-to-digital converter can be designed to convert the analog signal under test into a digital signal under test and to transmit it to the digital emulation circuit for modeling the subsystem.

The signal connections are preferably designed as optical waveguides. This eliminates the problem of signal integrity and problems of electromagnetic compatibility (EMC) on the digital signal connections. Likewise, the use of fiber optic cables makes the distance between the communicating participants secondary.

Due to the division of the overall model into sub-models and the associated division of a central model unit into sensor model units, the test bench has a modular design. In this way, partial model units that are not required (e.g. sensor model units) can be easily removed, or additional required model units can be added.

A partial model is preferably modeled by an analog emulation circuit associated with the digital emulation circuit, with the analog emulation circuit emulating an analog test signal and transmitting it to the test object.

For this purpose, an analog emulation circuit associated with the digital emulation circuit can be provided, which is designed to model a subsystem of the overall system. The analog emulation circuit is designed to model the associated subsystem, to emulate an analog test signal and to transmit it to the test object.

The overall model is thus subdivided into sub-models, with a number of functional sensor model units, a main sub-model unit and an analog emulation circuit and an associated digital emulation circuit being used instead of a central overall model unit. Thus, not all of the test signals of the test object for the calculation of the overall model are converted from digital to analog in the central processing unit, as is usual in the prior art, but hybrid signal processing is selected. This also test signals can be emulated, which an immediate have an effect on the examinee. In particular, the analog emulation circuit can be used to emulate impedances that have a direct effect on the test object. It is also possible to preprocess the test specimen signals, which are output via test specimen signal outputs of the test specimen, before transmission to other partial model units (ie other sensor model units or other hybrid partial model units comprising an analog emulation circuit and a digital emulation circuit) for the overall model calculation in a decentralized analog or hybrid manner.

Since the test signal is present in analog form in the analog emulation circuit, a digital-to-analog conversion of a digital test signal to an analog test signal can be dispensed with. In particular, but not exclusively, there can be a reaction from the analog emulation circuit to the test object due to an impedance expected by the test object. Since analog emulation is also much faster than digital emulation, time-critical functions such as semiconductor switches can be emulated in the analog emulation circuit.

The analog test signal can be converted into a digital test signal and made available to the digital emulation circuit for modeling the subsystem associated with the digital emulation circuit.

Preferably, the main sub-model unit emulates an electric motor.

A rotor position sensor model unit is preferably provided as a sensor model unit, which models a rotor position sensor, with rotor information being transmitted from the main sub-model unit via the signal connection as sub-model output variables to the rotor position sensor model unit, and with the rotor position sensor model unit emulating a rotor position sensor signal as a digital test signal and transmitting it to the test object.

However, a digital rotor position sensor model unit can also be provided, which models a rotor position sensor, with rotor information being transmitted from the main sub-model unit via the signal connection as sub-model output variables to the rotor position sensor model unit, and with the rotor position sensor model unit emulating a rotor position sensor signal as a digital test signal and transmitting it directly to the test object. The digital rotor position sensor model unit thus corresponds to a sensor model unit without an associated digital-to-analog converter and can be used for test objects that have a digital test object input for the rotor position sensor signal. In addition, the digital rotor position sensor model unit can be expanded by a suitable digital-to-analog converter in order to be able to supply test items with analog rotor position sensor inputs as test item inputs with analog rotor position sensor signals as test signals.

A current sensor model unit is preferably provided as a sensor model unit which models a current sensor, with the main sub-model unit transmitting phase current information as a sub-model output variable to the current sensor model unit via the signal connection, and with the current sensor model unit emulating a current sensor signal as a digital test signal and transmitting it to the test object. For example, Hall sensors, Rogowski coils, current transformers, shunts, etc. can be provided as the current sensor to be modeled.

A temperature sensor model unit is preferably provided as a sensor model unit which models a temperature sensor, with the main sub-model unit transmitting temperature information as a sub-model output variable to the temperature sensor model unit via the signal connection, and with the temperature sensor model unit emulating a temperature sensor signal as a digital test signal and transmitting it to the test object. This can be converted into an analog test signal using a suitable digital-to-analog converter.

Furthermore, an automation unit can be provided, which is designed for parameterizing and/or controlling the main partial model unit.

The analog emulation circuit and the digital emulation circuit are preferably combined to form a hybrid emulation circuit.

However, a plurality of sensor model units or at least one sensor model unit and the digital emulation circuit can also be combined to form a combination circuit.

Preferably, the digital emulation circuit models at least part of an inverter, calculates output voltages as partial model output variables from the switching states of semiconductor switches of the modeled inverter and transmits these to the main partial model unit, with the analog emulation circuit receiving the analog emulation circuit as a test object signal from the test object, a gate driver signal, semiconductor switch of the inverter is modeled, the switching states of the semiconductor switches are simulated and made available to the main sub-model.

Gate driver signals can thus be output by the test object as a test object signal, which is processed by the analog emulation circuit be killed The emulation of the semiconductor switch of the inverter is therefore carried out in the analog emulation circuit and can therefore be carried out at a higher speed than with digital emulation. Furthermore, in contrast to a digital emulation of semiconductor switches, no digital-to-analog conversion is required for the simulation of the switching states of the semiconductor switches.

The switching states of the simulated semiconductor switches preferably react (e.g. in the form of an impedance) as an analog test signal to the gate driver of the device under test.

If the existing analog-to-digital converter is designed to convert the analog signal under test into a digital signal under test and to transmit it to the digital emulation circuit for modeling the subsystem, the digitized gate driver signals can be processed by the digital emulation circuit to create the associated submodel to emulate and calculate partial model outputs. For example, the digital emulation circuit can emulate an inverter and simulate desired currents, which are transmitted as sub-model output variables to the main sub-model unit. Another analog-to-digital converter can also be used to digitize the test object signals.

Furthermore, the combination of digital (motor model, rotor position, bus system, environment, etc.) and analog emulation (power electronics) allows a test object to be tested without having to make any modifications to the gate driver. In addition, the integration of gate driver security features into the DUT can be tested.

This eliminates the problem of signal integrity and problems of electromagnetic compatibility (EMC) on the digital signal connections. Likewise, the use of fiber optic cables makes the distance between the communicating participants secondary.

The digital emulation circuit preferably parameterizes the analog emulation circuit. The digital emulation circuit can be designed accordingly to parameterize the analog emulation circuit. The analog emulation circuit can thus be used flexibly for emulations of all types and arrangements of semiconductor switches.

• 1 einen Prüfstand nach dem Stand der Technik,
• 2 einen erfindungsgemäßen Prüfstand mit Sensormodelleinheiten und einer Haupt-Teilmodelleinheit,
• 3 einen erfindungsgemäßen Prüfstand mit Sensormodelleinheiten, einer Haupt-Teilmodelleinheit, einer analogen Emulationsschaltung und einer zugehörigen digitalen Emulationsschaltung, wobei die analoge und digitale Emulationsschaltung zu einer Hybridmodelleinheit zusammengefasst sind,
• 4 einen erfindungsgemäßen Prüfstand mit Sensormodelleinheiten, einer Haupt-Teilmodelleinheit, einer analogen Emulationsschaltung und einer zugehörigen digitalen Emulationsschaltung, wobei

The present invention is described below with reference to the 1 until 4 explained in more detail, which show exemplary, schematic and non-limiting advantageous embodiments of the invention. while showing

• 1 a state-of-the-art test bench,
• 2 a test bench according to the invention with sensor model units and a main sub-model unit,
• 3 a test bench according to the invention with sensor model units, a main sub-model unit, an analog emulation circuit and an associated digital emulation circuit, the analog and digital emulation circuit being combined to form a hybrid model unit,
• 4 a test bench according to the invention with sensor model units, a main sub-model unit, an analog emulation circuit and an associated digital emulation circuit, wherein

Sensor model units and the digital emulation circuit are combined into a combination circuit.

1 FIG. 12 shows a test bench 1 according to a hardware-in-the-loop system according to the prior art. A central model unit 10 is provided for modeling an overall system. For example, an electric motor with associated sensors etc. is modeled on the central model unit 10 .

Furthermore, a number of digital-to-analog converters 20 and analog-to-digital converters 21 (here one digital-to-analog converter 20 and one analog-to-digital converter 21) are provided, which are arranged in the immediate vicinity of the central modeling unit 10 and thus are galvanically connected to the central modeling unit 10. The digital-to-analog converters 20 and analog-to-digital converters 21 can be arranged individually or in groups on a number of interface cards, which in turn are arranged on the central modeling unit 10 . The digital-to-analog converter 20 receives a digital test signal 20a from the central processing unit 10 and converts it into an analog test signal, which in turn is specified for a test object signal input of a test object 30 . The test specimen 30 outputs an analog test specimen signal 30a via a test specimen signal output,
which is converted into a digital test specimen signal by the analog-to-digital converter 21 and is specified for the central modeling unit 10 . The central modeling unit 10 uses the digital test sample signal 20a to model the overall system and to emulate the digital test signal, which is fed to the digital-to-analog converter 20 as explained above. Control or regulation hardware, for example an inverter, as is known from electric vehicles, can be provided as test object 30 . The DUT 30 can be a signal domain of the inverter together with an interface to the power domain, with which the test bench 1 emulates the power domain of the inverter.

2 until 4 each represent a test bench 1 according to the invention. No central modeling unit is provided for modeling the overall system, but rather a number of functional sub-model units, each of which models a sub-system of the overall system. A main partial model unit 11, a digital emulation circuit 50 and a number of sensor model units 12, 13, 14 are provided as functional partial model units, with in 3 and 4 analog emulation circuit 51 associated with digital emulation circuit 50 is also provided.

The sensor model units 12, 13, 14 each model a sensor as a subsystem and are connected to the main submodel unit 11 via signal connections 40, 41, 42. It is communicated via the signal connections 40, 41, 42 between the main sub-model unit 11 and the sensor model units 12, 13, 14 and between the main sub-model unit 11 and the digital emulation circuit 50 in order to enable the sub-systems to model the overall system. The digital emulation circuit 50 is configured to model a subsystem in a digital manner.

The number of sensor model units 12, 13, 14 are each designed to emulate a digital test signal 12a, 13a, 14a. In order to make the digital test signal 12a, 13a, 14a available to the test object 30, a number of digital-to-analog converters 22, 23, 24 are provided, each of which is designed to convert the associated digital test signal 12a, 13a, 14a into an analog test signal to walk. The number of digital-to-analog converters 22, 23, 24 can also be an integral part of the associated sensor model unit 12, 13, 14. The analog test signal is transmitted to the signal inputs of the test object 30 in each case. Thus, the sensor model units 12, 13, 14 can be arranged as close as possible to the test specimen inputs of the test specimen 30.

In 3 an analog emulation circuit 51 associated with the digital emulation circuit 50 is also provided as functional partial model units for modeling the overall system. The digital emulation circuit 50 and associated analog emulation circuit 51 are in 3 advantageously combined to form a hybrid emulation circuit 15, whereas in 4 the sensor model units 12, 13, 14 and the digital emulation circuit 50 are combined. The design according to 4 is particularly advantageous if a particularly compact test specimen 30 is present, so that the signal outputs and signal inputs on test specimen 30 are spatially close to one another. The further description is for the execution according to both 3 as well as for execution 4 valid.

The analog emulation circuit 51 is configured to emulate a subsystem in an analog manner and transmit an analog test signal 51a directly to a DUT signal input of the DUT 30 . In this case, the associated digital emulation circuit 50 can also emulate a digital subpart of a subsystem and the analog emulation circuit 51 can emulate an analog subpart of the same subsystem.

In analog emulation circuit 51, in contrast to digital emulation (as in sensor model units 12, 13, 14), digital-to-analog conversion of a digital test signal to an analog test signal (cf. test signal 10a in 1 ) can be waived. Furthermore, an analog emulation is much faster than a digital emulation, which is why time-critical functions are emulated in the analog emulation circuit 51 and comparatively fewer time-critical functions are emulated in the digital emulation circuit 50 .

An analog/digital converter 25 is also provided, which is connected to an analog test item signal output of the test item 30 and is thus configured to receive an analog test item signal 30a from the test item 30 . This analog DUT signal 30a is converted into a digital DUT signal by the analog-to-digital converter 25 and transmitted to the digital emulation circuit 50, which in turn is used by the digital emulation circuit 50 to model the digital part of the associated subsystem. Furthermore, the main partial model unit 11 can transmit partial model output variables and/or parameters for modeling the digital part of the associated partial system to digital emulation circuit 50 via signal connection 43 .

Likewise, the digital emulation circuit 50 can be configured to transmit parameters to the analog emulation circuit 51, with which it can be parameterized, which is shown in 3 and 4 is indicated by the part of the dashed double arrow pointing to the analog emulation circuit 51 .

An analog test signal 51a emulated by the analog emulation circuit 51 can also be converted into a digital test signal by means of an analog/digital converter and transmitted to the digital emulation circuit 50 and used by the latter to model the digital part of the associated subsystem. Transmission of the analog test signal 51a from the analog Emulation circuit 51 to the digital emulation circuit 50 is in 3 and 4 indicated by the part of the dashed double arrow pointing to the digital emulation circuit 50, but no analog-to-digital converter for converting the analog test signal 51a into a digital test signal is shown.

The digital emulation circuit 50 can model an inverter (without semiconductor switches) as a subsystem. The semiconductor switches of the inverter can accordingly be modeled by the analog emulation circuit 51 for emulation as an analog subsystem. This means that the inverter can be partially emulated digitally and partially analogously. In the digital emulation circuit 50, for example, the topology of the inverter itself, a temperature behavior of the inverter, line failures, resulting voltages on the AC side of the inverter, etc. can be emulated, while in the analog emulation circuit 51 the temporal behavior of the individual power switches is emulated. In this perspective, the inverter can be viewed as a subsystem, with the semiconductor switches being one (analog emulated) subsystem and the rest of the inverter being another (digitally emulated) subsystem.

A simulated analog test signal 51a, e.g. an impedance of the semiconductor switches, which switch according to the intended switching states, is thus directly present at the analog emulation circuit 51 and is made available to the test object 30. The emulation of the semiconductor switches is time-critical and can take place far more quickly than in the prior art, since an analog signal output of the analog emulation circuit 51 can be connected directly to an analog signal input of the test object 30 to transmit the analog test signal 51a. Thus, in contrast to the prior art, no digital modeling of the semiconductor switches and subsequent digital-to-analog conversion of the digitally emulated test signals is required.

Gate drive signals as analog DUT signals 51a from DUT 30 can be converted into a digital DUT signal (i.e., a digital gate drive signal) via an analog-to-digital converter 25 and transmitted to the digital emulation circuit 50 . However, gate drive signals can also be transmitted directly from the test specimen 30 to the analog emulation circuit 51 as analog test specimen signals 51a.

The output voltages of the inverter resulting from the switching state of the gate driver can be calculated by the digital emulation circuit 50, which are transmitted via the signal connection 43 to the main model unit 11 as partial model output variables 50a.

The main sub-model unit 11 can, for example, model an electric motor as a sub-system. The main sub-model unit 11 thus calculates sub-model output variables 11a', 11a", 11a'", 11a"" and/or parameters 11p', 11p", 11p'", 11p"" and communicates these via the signal connections 40, 41, 42 to the number of sensor model units 12, 13, 14 and via the signal connection 43 to the digital emulation circuit 50.

Furthermore, a rotor position sensor model unit 12 can be provided as a sensor model unit which models a rotor position sensor. The main partial model unit 11 can thus transmit rotor information as a partial model output variable 11a′ to the rotor position sensor model unit 12 via the signal connection 40 . Furthermore, the rotor position sensor model unit 12 can generate a digital rotor position sensor signal as a digital test signal 12a. The digital rotor position sensor signal is converted by the associated digital-to-analog converter 22 into an analog rotor position sensor signal as an analog test signal and is made available to the test object 30 . Furthermore, partial model parameters 11p′ are preferably transmitted from the main partial model 11 to the rotor position sensor model unit 12 via the signal connection 41 . The test signal 12a (rotor position sensor signal) can also be transmitted from the rotor position sensor model unit 12 to the main part model 11 via the signal connection 42 .

Depending on the configuration of the test object 30, the rotor position sensor signal can also be transmitted directly in digital form from a digital rotor position sensor model unit without the intermediate step via a digital-to-analog converter (not shown in the figures).

Furthermore, an exemplary current sensor model unit 13 can be provided as a sensor model unit which models a current sensor. The main partial model unit 11 can thus transmit phase current information as a partial model output variable to the current sensor model unit 13 via the signal connection 41 .

Furthermore, the current sensor model unit 13 can generate a digital current sensor signal as a digital test signal. The digital current sensor signal is converted by the associated digital-to-analog converter 23 into an analog current sensor signal as an analog test signal and is made available to the test object 30 . In this case, the current sensor model unit 13 is also able to make real currents available to the test object 30 as a test signal 13a. This means that current detection circuits on the device under test 30 do not have to be manipulated. Next will be before preferably sub-model parameters 11p" from the main sub-model 11 via the signal connection 41 to the current sensor model unit 13. The test signal 13a (current sensor signal) can also be transmitted via the signal connection 41 from the current sensor model unit 13 to the main sub-model 11.

In addition, an exemplary temperature sensor model unit 14 can be provided as a sensor model unit which models a temperature sensor.

The main sub-model unit 11 can thus transmit temperature information as sub-model output variables via the signal connection 42 to the temperature sensor model unit 14 . Furthermore, partial model parameters are preferably transmitted from the main partial model 11 to the temperature sensor model unit 14 via the signal connection 42 . The DUT signal 14a can also be transmitted from the temperature sensor model unit 14 to the main part model 11 via the signal connection 42 .

Furthermore, the temperature sensor model unit 14 can generate a digital temperature sensor signal as a digital test signal 14a. The digital temperature sensor signal is converted by the associated digital-to-analog converter 23 into an analog temperature sensor signal as an analog test signal and is made available to the test object 30 . In particular, however, an emulation of the temperature sensor can be dispensed with if no corresponding signal inputs are provided on the test object 30 .

It is assumed that the main sub-model 11 models an electric motor as a sub-model, a rotor position sensor model unit 12 as a sensor model unit models a rotor position sensor, a current sensor model unit 13 as a sensor model unit models a current sensor as a sub-model, and a temperature sensor model unit 14 as a sensor model unit models a temperature sensor. It is further assumed that the digital emulation circuit 50 models an inverter as a partial model, with the analog emulation circuit 51 modeling semiconductor switches of the inverter as a partial model. The device under test 30 provides switching states of the semiconductor switches (e.g. in the form of a PWM signal) as an analog device under test signal 30a. These switching states of the semiconductor switches are transmitted to the digital emulation circuit 50 as a digitally converted test object signal, which can be done, for example, via the analog-to-digital converter 25 or also via an analog-to-digital converter integrated in the analog emulation circuit 51 .

The main sub-model 11 transmits via the signal connection 43 to the digital emulation circuit 50 sub-model parameters, which are used to model the power semiconductors. The partial model parameters can be specified, for example, by a higher-level automation unit 60 or an operator.

The digital emulation circuit 50 emulates an output voltage which are in turn made available to the main partial model 11 via the connecting line 43 as a partial model output variable 50a. The main sub-model 11 in turn determines phase currents of the electric motor from the output voltage, which are transmitted as sub-model output variables 11a" of the main sub-model 11 via the signal connection 41 to the current sensor model unit 13.

The analog emulation circuit 51 emulates power semiconductors of the inverter based on the switching states of the semiconductor switches (test object signal 30a) obtained in analog form, which can react as analog test signals to the test object 30 (represented as a double arrow between the analog emulation circuit 51 and the test object 30). Main sub-model 11 also determines rotor position information from the output voltage and/or the phase currents determined therefrom, which is transmitted as sub-model output variable 11 a ′ of main sub-model 11 via signal connection 40 to rotor position sensor model unit 12 . Furthermore, partial model parameters 11p′ are preferably transmitted from the main partial model 11 to the rotor position sensor model unit 12 via the signal connection 40 . The test signal 12a can also be transmitted from the rotor position sensor model unit 12 to the main part model 11 via the signal connection 40 .

In addition, the main sub-model 11 can transmit the phase currents of the electric motor as sub-model output variables 11a "of the main sub-model 11 via the signal connection 42 to the temperature sensor model unit 14, which calculates temperatures using a suitable loss model. However, temperature data can also be external or from one provided on the test bench 30 Automation system 60, e.g. in the form of temperature curves.

Next is in 2 until 4 the test stand 1 according to the invention is provided with an optional automation unit 60 . The automation unit 60 can take over tasks of parameterization or non-time-critical simulation tasks, such as environmental emulators or the communication of non-time-critical sub-model parameters and is connected to the main sub-model unit 11 . The possibility of placing the main partial model unit 11, which takes over the communication with the automation unit 60, spatially directly next to it is advantageous here. Larger spatial distances between the main sub-model unit 11 and the sensor model units 12, 13, 14 and the digital emulation circuit 50 are not particularly critical if the signal connections 40, 41, 42, 43 are designed as optical waveguides.

The automation unit 60 can take over emulation tasks that are not critical in terms of time. For this purpose, any kind of computer system can be provided, which is connected to the main partial model unit 11 . Automation parameters of the automation unit 60 can also be tunneled via the main sub-model unit 11 directly to the required sub-model unit (i.e. sensor model unit, digital emulation circuit 50, analog emulation circuit 51). From the point of view of signal integrity, the location of the automation unit 60 is therefore irrelevant as long as the partial model unit 11 11 is placed in its immediate vicinity. The same applies to remaining bus simulation modules, which can be integrated independently of the remaining functions.

Basically, the test stand 1 can have a modular design, with which functional sensor model units 12, 13, 14 that are not required can be removed in a simple manner, or additional required sensor model units 12, 13, 14 can be added.

The automation unit 60 and/or digital sub-model units (i.e. main sub-model unit 11 and/or functional sensor model units 12, 13, 14 and/or digital emulation circuit 50) may comprise microprocessor-based hardware, for example a computer or digital signal processor (DSP), on which appropriate software is executed to perform the respective function. The automation unit 60 and/or digital submodel units can also include integrated circuits, for example an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA), or a configurable programmable logic device (CPLD) or and can be monitored in parallel with a microprocessor . It is also possible for different functions to be implemented on the same hardware and/or on different hardware parts. Mixed forms in which individual units are implemented both in hardware and in software are particularly advantageous.

The analog emulation circuit 51 can include an analog circuit (preferably including passive and/or active electrical components) or an analog computer, mixed forms also being conceivable.

Reference List

1

test bench

10

central modeling unit

11

main part model

11a', 11a", 11a''", 11a''''

partial model output

11p', 11p", 11p'", 11p""

parameter

12, 13, 14

sensor model units

12a, 13a, 14a

digital test signal

15

hybrid emulation circuit

20

Digital to analog converter

20a

digital test signal

21

Analog to digital converter

22, 23, 24

Digital to analog converter

25

Analog to digital converter

30

examinee

30a

analog DUT signal

40, 41, 42, 43

signal connection

50

digital emulation circuit

50a

partial model outputs

51

analog emulation circuit

51a

analog test signal

50p

parameter

60

automation unit

QUOTES INCLUDED IN DESCRIPTION

This list of the documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• CN 204086979 U [0003]
• CN 102110010A [0003]
• DE 102010043661 A1 [0003]

Claims (24)

Method for carrying out a test run with a test object (30) on a test stand (1), characterized in that an overall system to be modeled is divided into a number of subsystems on the test stand (1), one subsystem being controlled by a sensor model unit (12, 13, 14 ), one sub-system is modeled by a digital emulation circuit (50) and one sub-system by a main sub-model unit (11), with the main sub-model unit (11) being connected to the sensor model unit (12, 13, 14) and the digital Emulation circuit (50) communicates via signal connections (40, 41, 42, 43), the sensor model unit (12, 13, 14) emulating a digital test signal (12a, 13a, 14a), which is converted into an analog test signal and sent to the test object (30) is transmitted, and that an analog DUT signal (30a) is received by the DUT (30), converted into a digital DUT signal, transmitted to the digital emulation circuit (50) and used for modeling ng of the associated subsystem is used. procedure after claim 1 , characterized in that the main partial model unit (11) sends partial model output variables (11a', 11a", 11a'') and/or parameters (11p', 11p", 11p'') via the associated signal connection (40, 41, 42) ) to the sensor model unit (12, 13, 14). procedure after claim 1 or 2 , characterized in that the main partial model unit (11) transmits partial model output variables (11a"") and/or parameters (11p"") to the digital emulation circuit (50) via the associated signal connection (43). Procedure according to one of Claims 1 until 3 , characterized in that the sensor model unit (12, 13, 14) transmits the digital test signal (12a, 13a, 14a) to the main sub-model unit (11) via the associated signal connection (40, 41, 42). Procedure according to one of Claims 1 until 4 , characterized in that the digital emulation circuit (50) transmits a partial model output variable (50a) to the main partial model unit (11) via the associated signal connection (43). Procedure according to one of Claims 1 until 5 , characterized in that a subsystem is modeled by an analog emulation circuit (51) associated with the digital emulation circuit (50), and in that the analog emulation circuit (51) emulates an analog test signal (51a) and transmits it to the test object (30). procedure after claim 6 , characterized in that the analog test signal (51a) is converted into a digital test signal and made available to the digital emulation circuit (50) for modeling the subsystem associated with the digital emulation circuit (50). procedure after claim 6 or 7 , characterized in that the digital emulation circuit (50) transmits parameters (50p) to the analog emulation circuit (51). Procedure according to one of claims 2 until 8th , characterized in that the digital emulation circuit (50) models at least part of an inverter, calculates target currents as partial model output variables (50a) from the switching states of semiconductor switches of the modeled inverter and transmits these via the signal connection (43) to the main partial model unit (11). , and that the analog emulation circuit (51) receives a gate driver signal as a test object signal (30a) from the test object (30), models semiconductor switches of the inverter, simulates switching states (51a) of the semiconductor switches and makes them available to the main sub-model (11). procedure after claim 9 , characterized in that the switching states of the simulated semiconductor switch acts as a test signal on the gate driver of the test object (30). Procedure according to one of claims 2 until 9 , characterized in that the analogue driver signals of the analogue emulation circuit (51) are converted into digital driver signals and made available to the digital emulation unit (50) for emulation of the digital inverter currents. Procedure according to one of Claims 1 until 11 , characterized in that the main sub-model unit (11) emulates an electric motor. Procedure according to one of Claims 1 until 12 , characterized in that a rotor position sensor model unit (12) is provided as a sensor model unit which models a rotor position sensor, with the main sub-model unit (11) transmitting rotor position information as a sub-model output variable (11a') via the signal connection (40) to the rotor position sensor model unit (12), and wherein the rotor position sensor model unit (12) emulates a rotor position sensor signal as a digital test signal (12a) and transmits it to the test object (30). Procedure according to one of Claims 1 until 13 , characterized in that a digital rotor position sensor model unit (12) is provided as a sensor model unit which a rotor position sensor modeled, with the main sub-model unit (11) transmitting rotor position information as a sub-model output variable (11a') via the signal connection (40) to the rotor position sensor model unit (12), and with the rotor position sensor model unit (12) emulating a rotor position sensor signal as a digital test signal (12a) and directly transmitted to the test object (30). Procedure according to one of Claims 1 until 14 , characterized in that a current sensor model unit (13) is provided as a sensor model unit which models a current sensor, the main partial model unit (11) transmitting phase current information as a partial model output variable (11 a") to the current sensor model unit (13) via the signal connection (41), and wherein the current sensor model unit (13) emulates a current sensor signal as a digital test signal (13a) and transmits it to the device under test (30). Procedure according to one of Claims 1 until 15 , characterized in that a temperature sensor model unit (14) is provided as a sensor model unit which models a temperature sensor, the main partial model unit (11) transmitting temperature information as a partial model output variable (11a"`) to the temperature sensor model unit (14) via the signal connection (42) and wherein the temperature sensor model unit (14) emulates a temperature sensor signal as a digital test signal (14a) and transmits it to the test object (30). Test stand (1) for carrying out a test run with a test specimen (30), characterized in that a number of sensor model units (12, 13, 14), a digital emulation circuit (50) and a main sub-model unit (11) are provided, which are each configured to model a subsystem of an overall system that the main submodel unit (11) and the number of sensor model units (12, 13, 14) are each connected via signal connections (40, 41, 42) and the main submodel unit (11) and the digital emulation circuit (50) are connected via a signal connection (43) in order to communicate in each case for carrying out the test run that the number of sensor model units (12, 13, 14) are each designed to emulate a digital test signal (12a, 13a, 14a), wherein a number of digital-to-analog converters (22, 23, 24) is provided, which are each designed to convert the associated digital test signal (12a, 13a, 14a) into an analog test signal and to the to transmit the test specimen (30), that an analog-to-digital converter (25) is provided, which is designed to receive an analog test specimen signal (30a) from the test specimen (30), to convert it into a digital test specimen signal and to transmit it to the digital emulation circuit (50 ) to transmit, and that the digital emulation circuit (50) is designed to model the associated subsystem using the digital test sample signal (30a). test bench Claim 17 , characterized in that an analog emulation circuit (51) associated with the digital emulation circuit (50) is provided, which is designed to model a subsystem of the overall system, and in that the analog emulation circuit (51) is designed to model the associated subsystem to emulate an analog test signal (51a) and to transmit it to the test object (30). test bench Claim 18 , characterized in that the digital emulation circuit (50) is designed to transmit parameters (50p) to the analog emulation circuit (51). Test stand (1) according to Claim 18 or 19 , characterized in that the analog-to-digital converter (25) is designed to convert the analog test object signal (30a) into a digital test object signal and to transmit it to the digital emulation circuit (50) for modeling the subsystem. Test bench according to one of claims 18 until 20 , characterized in that the analog emulation circuit (51) and the digital emulation circuit (50) are combined to form a hybrid emulation circuit (15). Test bench according to one of claims 17 until 21 , characterized in that the signal connections (40, 41, 42, 43) are designed as optical waveguides. Test bench according to one of claims 17 until 22 , characterized in that at least one sensor model unit (12, 13, 14) and the digital emulation circuit (50) are combined to form a combination circuit. Test bench according to one of claims 17 until 23 , characterized in that an automation unit (60) is provided, which is designed for parameterization and/or control of the main partial model unit (11).

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