DE102022102506A1 - Device and method for switching error states in a simulation environment - Google Patents

Abstract

In a device for switching error states in a simulation environment, the disadvantages of routing via a busbar should be minimized. This is achieved in that a device for switching error states in a simulation environment is specified with an error forwarding device (FRU) and an error introduction unit (FILT), the error introduction unit (FIU) having a connection unit (1) for connecting signal paths (ECU1, ECUn) to an internal busbar (RL1), the signal paths (ECU1, ECUn) being combined to form a common signal path (2) and the connection unit (1) in the common signal path (2) comprising at least one semiconductor switch (C2) in order to switch. The invention also relates to a method for switching error states in a simulation environment, the use of the device and the method for switching error states in a HIL simulator, and a computer program product.

Description

The invention relates to a device and a method for switching error states in a simulation environment. The invention also relates to the use of the device and the method in a HIL simulator. The invention also relates to a computer program product.

Devices for testing, in particular those designed as HIL simulators, are known from the prior art and are used in particular for testing control units. The abbreviation "HII," (derived from the English word group: "hardware in the loop") is an international technical term, used in particular in the German-speaking area, for a test method in which an "embedded system" (abbreviation: "ES") , in particular an electronic control unit (ECU), or a mechatronic module, is connected via its inputs and outputs to a matched counterpart, often referred to as a HIL simulator, used to emulate the real environment of the embedded system. Thus, during the test of the embedded system, at least some of the input signals for the ES are provided by the HIL simulator and at least some of the output signals of the ES are sent to the HII simulator. Fault injection is a testing technique that helps to understand how a (virtual or real) system behaves when it is stressed in an unusual way, by switching different fault states. Many HIL test systems use hardware fault simulation to inject signal faults between the electronic control unit and the rest of the system to verify device behavior under specific conditions. Fault simulation is primarily used when an ECU requires both a known and a tolerated response to fault conditions. The use of Fault Insertion Units (FIUs) between the I/O interfaces and the ECU is suitable for this, which can cause normal and faulty operating conditions, such as short circuit and open circuit.

A central topology offers the possibility to use very simple, inexpensive, mostly relay-based switching units in the numerous channels and, if necessary, to connect them via a busbar to a complex central assembly, which is then able to introduce semiconductor-based fault patterns such as bouncing or loose contacts . However, the disadvantage of this system is that sensitive signals are often unacceptably affected by routing via the busbar. In the present context, a busbar is an electrically conductive rail, preferably with specially designed electrical properties such as, for example, a low parasitic capacitance, a low resistance or a high electrical withstand voltage. In addition to the busbar, further hardware components can be provided, for example further busbars or switch matrices connected to the busbars.

It is therefore the technical task of the present invention to minimize the disadvantages of routing via a busbar.

This object is solved by technical objects according to the independent claims. Technically advantageous embodiments are the subject matter of the dependent claims, the description and the drawings.

• - zumindest eine erste interne Sammelschiene,
• - zumindest einen ersten Signalpfad, wobei der erste Signalpfad von einem ersten Steuergeräteanschluss eines elektronischen Steuergeräts über einen ersten Schalter zu einer ersten Last geführt ist,
• - zumindest einen zweiten Signalpfad, wobei der zweite Signalpfad von einem zweiten Steuergeräteanschluss eines elektronischen Steuergeräts über einen zweiten Schalter zu einer zweiten Last geführt ist,

die Vorrichtung weiter umfassend:

• - eine Fehlerweiterleitungseinrichtung eingerichtet, um zumindest einen der Signalpfade auszuwählen,
• - eine Fehlereinbringungseinheit eingerichtet, um unterschiedliche Fehlerzustände zu schalten, die Fehlereinbringungseinheit umfassend eine Anbindungseinheit zum Anbinden der Signalpfade an die erste interne Sammelschiene, derart eingerichtet, eine schaltbare Verbindung von dem ersten Signalpfad und dem zweiten Signalpfad zu der ersten internen Sammelschiene herzustellen, wobei die Signalpfade zu einem gemeinsamen Signalpfad geführt sind und schaltbar mit dem gemeinsamen Signalpfad verbindbar sind, wobei der gemeinsame Signalpfad einen ersten Halbleiterschalter umfasst, derart eingerichtet die Fehlerzustände zu schalten,

die Fehlerweiterleitungseinrichtung zumindest einen dritten Schalter und einen vierten Schalter umfasst, eingerichtet den ersten Signalpfad an die Anbindungseinheit anzubinden,
die Fehlerweiterleitungseinrichtung zumindest einen fünften Schalter und einen sechsten Schalter umfasst, eingerichtet den zweiten Signalpfad an die Anbindungseinheit anzubinden,
wobei der erste Halbleiterschalter schaltbar mit mindestens dem dritten Schalter oder dem fünften Schalter verbindbar ist,
die Anbindungseinheit zumindest einen siebten Schalter zum Anbinden der internen Sammelschiene an eine externe Sammelschiene umfasst.According to one aspect, the object of the invention is achieved by a device for switching error states in a simulation environment, the device comprising:

• - at least a first internal busbar,
• - at least one first signal path, the first signal path being routed from a first control unit connection of an electronic control unit via a first switch to a first load,
• - at least one second signal path, the second signal path being routed from a second control unit connection of an electronic control unit via a second switch to a second load,

the device further comprising:

• - set up an error forwarding device to select at least one of the signal paths,
• - an error introduction unit set up to switch different error states, the error introduction unit comprising a connection unit for connecting the signal paths to the first internal busbar, set up in such a way as to establish a switchable connection from the first signal path and the second signal path to the first internal busbar, the signal paths are led to a common signal path and can be connected to the common signal path in a switchable manner, the common signal path comprising a first semiconductor switch set up in such a way to switch the error states,

the error forwarding device comprises at least a third switch and a fourth switch, set up to connect the first signal path to the connection unit,
the error forwarding device comprises at least one fifth switch and one sixth switch, set up to connect the second signal path to the connection unit,
wherein the first semiconductor switch can be connected in a switchable manner to at least the third switch or the fifth switch,
the connection unit comprises at least one seventh switch for connecting the internal busbar to an external busbar.

The invention implements the switching of all standard error classes via semiconductor switches without having to accept the disadvantages of signal routing via external busbars and without the high costs of semiconductors on all channels. Semiconductor switches also have the advantage that they can be switched with precise timing and do not bounce. With just one semiconductor switch, individual errors on different ECU signals can be switched with the precision of a semiconductor switch. The seventh switch is advantageous in order to be able to separate an internal busbar from an external busbar, for example. In this way, for example, an error can be switched locally independently of other error introduction units, in order to enable multiple errors, i.e. several errors independently of one another, to be switched at the same time. Furthermore, the advantage can thereby be achieved that any electrical interference that is coupled into the device for switching error states via an external busbar is not passed on. The connection of the semiconductor switch to the ECU channels can be carried out locally and thus electrically optimally, which results in only very low parasitic influences due to the connection to the internal busbar or busbars. A further advantage is that the semiconductor switch is introduced in a cost-efficient manner, since only one semiconductor switch has to be used for a scalable number of locally placed channels. It is also advantageous that the semiconductor switch can be optimized (in terms of current/voltage) for the group of local channels assigned to it. For example, it is possible with little effort to provide a first semiconductor switch with high dielectric strength, e.g. a semiconductor switch suitable for switching electrical voltages above 50 volts, in the common signal path of the error injection unit FIU if the common signal path has the last-mentioned dielectric strength should.

• - ein elektrischer Aktor,
• - ein elektronsicher Sensor,
• - ein elektronischer Signalwandler,
• - ein elektronischer Signalgenerator,
• - eine Nachbildung (simulierte elektrische oder elektronische Baueinheit) eines der in diesem Satz genannten Beispiele,
• - eine Kombinationsbaueinheit, umfassend zumindest zwei der in diesem Satz genannten Beispiele.

The “load” in the context of the present disclosure is an electrical assembly that is provided and set up to be electrically connected to a signal connection or to a signal path emanating from the control device. Some examples of a load are:

• - an electric actuator,
• - an electronic sensor,
• - an electronic signal converter,
• - an electronic signal generator,
• - a replica (simulated electrical or electronic assembly) of one of the examples given in this sentence,
• - a combination assembly comprising at least two of the examples mentioned in this sentence.

In a technically advantageous embodiment, the device comprises a ninth switch, set up to connect the common signal path to the first signal path and a tenth switch, set up to connect the common signal path to the second signal path, the connection unit in the common signal path between the connection to the signal paths via the ninth Switch and the tenth switch and the connection to the signal paths via the fourth switch and the sixth switch comprises a second semiconductor switch for switching error states, wherein the common signal path is branched off before the first internal busbar and includes the first semiconductor switch. The ninth switch is particularly advantageous in the case of cross-short circuits with semiconductor switches, in which case a load may also need to be disconnected. The second semiconductor switch is advantageous in order to also be able to disconnect a corresponding load in the event of short circuits.

In a technically advantageous embodiment, the device comprises a second internal busbar, the second internal busbar being connected to the common signal path, being connected to the first signal path via the ninth switch and being connected to the second signal path via the tenth switch, the connection unit having a twelfth switch, set up to connect the second internal busbar to a second external busbar. For example, two busbars enable the integration of external two-poles (e.g. resistor, voltage source, current sink, measuring device, ...).

In a technically advantageous embodiment, the device comprises a first connection potential and a second connection potential, with the connection unit comprising a thirteenth switch set up to connect the first internal busbar to the second connection potential bind and comprises a fourteenth switch set up to bind the first internal busbar to the first connection potential.

In a preferred embodiment of the invention, the first connection potential is a ground potential and the second connection potential is a supply potential. In a particularly preferred embodiment, the supply potential is a battery voltage, for example. The direct connection of connection potentials enables short circuits against these connection potentials without the integration of external busbars. No additional components are required that place these connection potentials on a corresponding busbar. This allows more different multiple errors.

In a technically advantageous embodiment, the device comprises a third internal busbar, the third internal busbar being connected to the first signal path via a fifteenth switch and to the second signal path via a sixteenth switch, the connection unit comprising a seventeenth switch, set up on the third busbar connect the first connection potential, the connection unit comprises an eighteenth switch, configured to connect the first connection potential to the second internal busbar, the connection unit comprises a twentieth switch, configured to connect the second internal busbar to the second connection potential, and the connection unit comprises an eighth switch in the common signal path , set up in such a way to decouple the first semiconductor switch and optionally to connect the second internal busbar via an eleventh switch or the third internal busbar via a nineteenth switch. A third busbar allows for more multiple faults with different fault states.

In a technically advantageous embodiment, a plurality of devices for switching error states in a simulation environment are connected to one another via at least one external busbar.

In a technically advantageous embodiment, the semiconductor switches are MOSFETs. In one embodiment, the semiconductor switches consist of a circuit with a plurality of MOSFETs. For example, at least 2 MOSFETs are preferably connected in series in order to interrupt the current in both current directions.

• - Bereitstellen einer Vorrichtung zum Schalten von Fehlerzuständen wie zuvor beschrieben,
• - Vorkonfigurieren der Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung in einer Vorkonfigurationsphase,
• - Simulieren von Fehlerzuständen durch Ändern der Schaltzustände der Schalter der Vorrichtung.

According to a further aspect, the object of the invention is achieved by a method for switching error states in a simulation environment, the method comprising the following steps:

• - providing a device for switching error states as previously described,
• - Pre-configuration of the device for switching error states in a simulation environment in a pre-configuration phase,
• - Simulating error states by changing the switching states of the switches of the device.

In a technically advantageous embodiment of the method, the error states are simulated by switching the first and/or the second semiconductor switch.

• - Simulieren eines Kabelbruchs mittels des ersten Halbleiterschalters über den ersten Signalpfad, wobei der Schritt des Vorkonfigurierens die folgenden Schritte umfasst:
• - Schließen des dritten Schalters, des vierten Schalters und des ersten Halbleiterschalters,
• - Öffnen des ersten Schalters,
• - Simulieren des Kabelbruchs durch Ein- und Ausschalten des ersten Halbleiterschalters oder
  • - Simulieren eines Kurzschlusses zu einem Anschlusspotential mittels des ersten Halbleiterschalters über den ersten Signalpfad, wobei der Schritt des Vorkonfigurierens die folgenden Schritte umfasst:
  • - Vorbelegen der ersten internen Sammelschiene mit einem Anschlusspotential,
  • - Schließen des dritten Schalters und des siebten Schalters,
  • - Simulieren eines Kurzschlusses durch Ein- und Ausschalten des ersten Halbleiterschalters oder
  • - Simulieren eines Kreuzkurzschlusses zwischen einer ersten Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung und einer weiteren Vorrichtung zum Schalten
  von Fehlerzuständen in einer Simulationsumgebung mittels des ersten Halbleiterschalters über den ersten Signalpfad, wobei der Schritt des Vorkonfigurierens die folgenden Schritte umfasst:
  • - Schließen des dritten Schalters und des siebten Schalters,
  • - Simulieren eines Kreuzkurzschlusses durch Ein- und Ausschalten des ersten Halbleiterschalters auf der ersten und der weiteren Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung.

In a technically advantageous embodiment, the steps of preconfiguring the device in a preconfiguration phase and simulating error states by switching the semiconductor switches include at least one of the following error states:

• - Simulating a cable break using the first semiconductor switch via the first signal path, the step of pre-configuration comprising the following steps:
• - Closing the third switch, the fourth switch and the first semiconductor switch,
• - opening the first switch,
• - Simulating the cable break by switching the first semiconductor switch on and off or
  • - Simulating a short circuit to a connection potential by means of the first semiconductor switch via the first signal path, the preconfiguration step comprising the following steps:
  • - Preassignment of the first internal busbar with a connection potential,
  • - Closing the third switch and the seventh switch,
  • - Simulating a short circuit by switching the first semiconductor switch on and off, or
  • - Simulating a cross-short circuit between a first device for switching error states in a simulation environment and a further device for switching
  of error states in a simulation environment by means of the first semiconductor switch via the first signal path, the step of pre-configuration comprising the following steps:
  • - Closing the third switch and the seventh switch,
  • - Simulating a cross-short circuit by switching the first semiconductor switch on and off on the first and the further device for switching error states in a simulation environment.

In one embodiment, a short circuit, for example, to a positive battery potential connection (e.g. in a motor vehicle) can be simulated by switching at least one switch, namely a semiconductor switch (e.g. a MOSFET) to the conductive state at another predefined point in the simulator system becomes.

• - Simulieren eines Kabelbruchs mittels des zweiten Halbleiterschalters über den ersten Signalpfad, und der Schritt des Vorkonfigurierens die folgenden Schritte umfasst:
  • - Schließen des neunten Schalters, des elften Schalters und des vierten Schalters,
  • - Öffnen des ersten Schalters,
  • - Simulieren des Kabelbruchs durch Ein- und Ausschalten des zweiten Halbleiterschalters oder
• - Simulieren eines Kurzschlusses zu einem ersten Anschlusspotential oder einem zweiten Anschlusspotential oder zu einer externen Sammelschiene mittels des ersten Halbleiterschalters und des zweiten Halbleiterschalters über den ersten Signalpfad, wobei der Schritt des Vorkonfigurierens die folgenden Schritte umfasst:
  • - Vorbelegen der ersten internen Sammelschiene mit dem ersten Anschlusspotential oder dem zweiten Anschlusspotential oder mit einer externen Sammelschiene,
  • - Schließen des neunten Schalters, des achten Schalters, des siebten Schalters, des elften Schalters und des vierten Schalters,
  • - Öffnen des ersten Schalters,
  • - Simulieren eines Kurzschlusses durch Ein- und Ausschalten des ersten Halbleiterschalters und des zweiten Halbleiterschalters oder
• - Simulieren eines Kreuzkurzschlusses zwischen einer ersten Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung und einer weiteren Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung mittels des ersten Halbleiterschalters über den ersten Signalpfad, wobei der Schritt des Vorkonfigurierens die folgenden Schritte umfasst:
  • - Schließen des neunten Schalters, des achten Schalters, des siebten Schalters, des elften Schalters, des vierten Schalters jeweils in der ersten und der weiteren Vorrichtung zum Schalten von Fehlerzuständen,
  • - Öffnen des ersten Schalters in der ersten und der weiteren Vorrichtung zum Schalten von Fehlerzuständen,
  • - Simulieren eines Kreuzkurzschlusses durch Ein- und Ausschalten des ersten Halbleiterschalters und des zweiten Halbleiterschalters in der ersten und der weiteren Vorrichtung zum Schalten von Fehlerzuständen.

In a technically advantageous embodiment, the device comprises a second semiconductor switch, wherein the second semiconductor switch is initially conductive and the first semiconductor switch is initially non-conductive, the steps of pre-configuring the device in a pre-configuration phase and simulating error states by switching the switches include at least one of the following Error conditions:

• - Simulating a cable break using the second semiconductor switch via the first signal path, and the step of pre-configuration includes the following steps:
  • - Closing the ninth switch, the eleventh switch and the fourth switch,
  • - opening the first switch,
  • - Simulating the cable break by switching the second semiconductor switch on and off or
• - Simulating a short circuit to a first connection potential or a second connection potential or to an external busbar by means of the first semiconductor switch and the second semiconductor switch via the first signal path, the preconfiguration step comprising the following steps:
  • - preassignment of the first internal busbar with the first connection potential or the second connection potential or with an external busbar,
  • - Closing the ninth switch, the eighth switch, the seventh switch, the eleventh switch and the fourth switch,
  • - opening the first switch,
  • - Simulating a short circuit by switching the first semiconductor switch and the second semiconductor switch on and off, or
• - Simulating a cross-short circuit between a first device for switching error states in a simulation environment and a further device for switching error states in a simulation environment by means of the first semiconductor switch via the first signal path, the preconfiguration step comprising the following steps:
  • - Closing the ninth switch, the eighth switch, the seventh switch, the eleventh switch, the fourth switch in each case in the first and the further device for switching error states,
  • - opening the first switch in the first and the further device for switching error states,
  • - Simulating a cross-short circuit by switching on and off the first semiconductor switch and the second semiconductor switch in the first and the further device for switching error states.

• - Schalten zumindest eines zweiten Fehlers über die zweite interne Sammelschiene und/oder

das Verfahren umfasst den folgenden zusätzlichen Schritt:

• - Einbinden einer Vorrichtung zur Widerstands-Simulation über die internen Sammelschienen.

In a technically advantageous embodiment, the device comprises a second internal busbar, the second internal busbar being connected to the common signal path, being connected to the first signal path via the ninth switch, being connected to the second signal path via the tenth switch and comprising the method the following additional steps:

• - Switching at least one second error via the second internal busbar and/or

the procedure includes the following additional step:

• - Inclusion of a resistance simulation device via the internal busbars.

For example, in one embodiment, the resistor may be externally located between the first external busbar and the second external busbar. This allows the following error patterns to be displayed. A series resistor by looping it into the signal path or a bleeder resistor where one busbar is connected to a potential and the other is connected to the ECU signal.

• - Simulieren eines Kurzschlusses zu dem ersten Anschlusspotential durch Schließen des vierzehnten Schalters und/oder
• - Simulieren eines Kurzschlusses zu dem zweiten Anschlusspotential durch Schließen des dreizehnten Schalters.

In a technically advantageous embodiment, the device comprises a first connection potential and a second connection potential, the connection unit comprises a fourteenth switch set up to connect the first internal busbar to the first connection potential and a thirteenth switch set up to connect the first internal busbar to the second connection potential,
wherein the first internal busbar is connected to a first external busbar via the seventh switch and the second internal busbar is connected to a second external busbar via the twelfth switch, and the method comprises the following additional steps:

• - Simulating a short circuit to the first connection potential by closing the fourteenth switch and/or
• - Simulating a short circuit to the second connection potential by closing the thirteenth switch.

In a technically advantageous embodiment, error states are simulated via the second signal path and the device is preconfigured in a preconfiguration phase by means of the switches of the second signal path.

In a technically advantageous embodiment, a single error status or a plurality of error statuses are switched simultaneously.

According to the invention is also the use of the device and the method for switching error states in a simulation environment in a HIL simulator.

Furthermore, a computer program product is specified, comprising instructions that cause the device described above to execute the method steps described above.

Exemplary embodiments of the invention are shown in the drawings and are described in more detail below.

• 1 ein Schaltbild einer Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung gemäß einem ersten Ausführungsbeispiel der Erfindung,
• 2 ein Schaltbild einer Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung gemäß einem weiteren Ausführungsbeispiel der Erfindung,
• 3 ein Schaltbild einer Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung gemäß einem weiteren Ausführungsbeispiel der Erfindung,
• 4 ein Schaltbild einer Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung gemäß einem weiteren Ausführungsbeispiel der Erfindung,
• 5 ein Schaltbild einer Vorrichtung zum Schalten von Fehlerzuständen in einer Simulationsumgebung gemäß einem weiteren Ausführungsbeispiel der Erfindung.

Show it:

• 1 a circuit diagram of a device for switching error states in a simulation environment according to a first embodiment of the invention,
• 2 a circuit diagram of a device for switching error states in a simulation environment according to a further embodiment of the invention,
• 3 a circuit diagram of a device for switching error states in a simulation environment according to a further embodiment of the invention,
• 4 a circuit diagram of a device for switching error states in a simulation environment according to a further embodiment of the invention,
• 5 a circuit diagram of a device for switching error states in a simulation environment according to a further embodiment of the invention.

1 shows a circuit diagram of a device for switching error states in a simulation environment according to a first embodiment of the invention. A simulation environment can be understood to mean, for example, a HIL simulator that is set up to test a wide variety of hardware by switching different error states.

In the 1 For this purpose, the device shown comprises at least one first internal busbar RL1, at least one first signal path ECU1, the first signal path ECU1 being routed from a first control unit connection of an electronic control unit via a first switch S1 to a first load LD1, and at least one second signal path ECUn, wherein the second signal path is routed from a second control unit connection of an electronic control unit via a second switch Sn to a second load LDn. To establish a switchable connection from the at least one control unit connection of a control unit via the signal paths ECU1, ECUn to the busbar RLlist, an error forwarding device FRU is provided, set up to select at least one of the signal paths ECU1, ECUn. The FRU is in 1 shown by the dashed box below. The device also includes an error injection unit FIU. The error recovery unit FIU is in 1 represented by the upper dashed box. The FIU is used to switch different error states. The upper dashed box is present at least once on a device for switching error states. The error introduction unit FIU comprises a connection unit 1 which is set up for connecting the signal paths ECU1, ECUn to the first internal busbar RL1. The connection unit 1 is set up in such a way that a switchable connection is established from the first signal path ECU1 and the second signal path ECUn to the first internal busbar RL1. The first signal path ECU1 is connected to the connection unit 1 by a third switch E1R1 and a fourth switch L1R2. The second signal path ECUn is connected to the connection unit 1 by means of a fifth switch EnR1 and by means of a sixth switch LnR2 to the first internal busbar RL1. In 1 shows that the signal paths ECU1, ECUn are combined to form a common signal path 2. In order to switch different error states, a first semiconductor is in the common signal path 2 switch C2 provided. The semiconductor switch C2 can be implemented as a MOSFET, for example. Semiconductor switches have the advantage that they can be switched more precisely in terms of time and do not bounce. The other switches in 1 can for example be designed as a relay. With just one semiconductor switch C2, individual errors on different ECU signals can thus be switched with the precision of a semiconductor switch. The seventh switch CR1 is advantageous in order to be able to separate an internal busbar RL1 from, for example, an external busbar exRL1. As a result, errors can be switched locally independently of other error introduction units, for example, in order to enable specific multiple errors to be switched. Furthermore, the advantage can hereby be achieved that any electrical interference that is coupled into the device for switching error states via an external busbar exRL1 is not passed on.

with the inside 1 With the topology shown, the most important error states can be switched relay-based as single or multiple errors. Additionally using the first semiconductor switch C2 in each case as a single error. In an exemplary embodiment of the invention, load shedding is switched via a relay, which is sufficient for load protection.

In very general terms, a method for switching error states in a simulation environment consists of the following steps, which is carried out using the device described above. A previously described device for switching error states in a simulation environment is thus provided. In a further step, the device for switching error states is preconfigured in a simulation environment in a preconfiguration phase. The preconfiguration required for switching the error states takes place exclusively locally on the corresponding device for switching error states and can therefore be designed to be minimal in terms of its parasitic influences. In addition, it is possible here to optimally match the semiconductor switch to the boundary conditions intended for the FIU channels. In the next step, the error states are simulated by switching the semiconductor switch C2.

In further exemplary embodiments of the invention, for example, the following error states can be prevented by the in 1 circuit diagram shown can be realized. A cable break can be simulated, for example, by means of the first semiconductor switch C2 via the first signal path ECU1, with the preconfiguration step comprising the following steps. In a first step, the third switch E1R1, the fourth switch L1R2 and the first semiconductor switch C2 are closed. In the next step, the first switch S1 is opened. Finally, a cable break can be simulated by switching the first semiconductor switch C2 on and off.

In 2 1 shows a circuit diagram of a device for switching error states in a simulation environment according to a further exemplary embodiment of the invention. The device includes in addition to the in 1 shown embodiment a ninth switch E1R2, which is set up to connect the common signal path 2 to the first signal path ECU1 and a tenth switch EnR2, set up to connect the common signal path 2 to the second signal path ECUn. A second semiconductor switch C4 for switching error states is provided in the common signal path 2 . In the preconfiguration, the second semiconductor switch C4 is initially conductive and the first semiconductor switch C2 is initially nonconductive. The steps of pre-configuring the device in a pre-configuration phase and simulating error states by switching the switches comprises at least one of the following error states. In addition, an in 2 not shown assumed simple structure central component, which is able to preconfigure different connection potentials, for example by means of a relay on the individual busbars exRL1, exRL2. the inside 2 The eighth switch C1 shown and the eleventh switch C3 shown serve to improve the electrical properties of the device, but are only shown as a further option in this exemplary embodiment.

In a further exemplary embodiment, a short circuit to a second connection potential VBat, for example a supply potential, can be simulated using the first semiconductor switch C2 via the first signal path ECU1 by the following steps. First, in the preconfiguration phase, the first internal busbar RL1 is assigned a connection potential. Then the ninth switch E1R2 and the eighth switch C1 are closed. A short circuit can then be simulated by switching the first semiconductor switch C2 on and off.

A cable break can be simulated, for example, by means of the second semiconductor switch C4 via the first signal path ECU1. The step of pre-configuration includes the following steps. First, the ninth switch E1R2, the eleventh switch C3 and the fourth switch L1R2 are closed. Then the first switch S1 opened. The broken cable can be closed by switching the second semiconductor switch on and off ters C4 can be simulated. A short circuit to a second connection potential VBat, for example a supply potential, can be simulated, for example, by means of the first semiconductor switch C2 and the second semiconductor switch C4 via the first signal path ECU1. The step of pre-configuration includes the following steps. First, the first internal busbar RL1 is assigned the second connection potential. The ninth switch E1R2, the eighth switch C1, the seventh switch CR1, the eleventh switch C3 and the fourth switch L1R2 are then closed. Thereafter, the first switch S1 is opened. Finally, a short circuit can be simulated by switching the first semiconductor switch C2 and the second semiconductor switch C4 on and off.

By adding the second semiconductor switch C4, short circuits/cross-short circuits can now also be switched via an external busbar exRL1, exRL2 with a semiconductor-based load shedding. The first semiconductor switch C2 switches the short circuit and the second semiconductor switch C4 can interrupt the connection to the load LD1, LDn at the same time, if necessary. In addition, a cross-short circuit can also be switched locally with load shedding (one-sided) via semiconductors (E1R1 and EnR1 remain relevant for this).

In a further exemplary embodiment of the invention, a cross-short circuit between a first device for switching error states in a simulation environment and a further device for switching error states in a simulation environment can be simulated as follows using the first semiconductor switch C2 via the first signal path ECU1. The pre-configuration step initially includes the following steps. In a first step, the ninth switch E1R2, the eighth switch C1, the seventh switch CR1, the eleventh switch C3 and the fourth switch L1R2 are each closed in the first and the further device for switching error states. The first switch S 1 in the first and the further device for switching error states is then opened. A cross-short circuit can then be simulated, for example, by switching the first semiconductor switch C2 and the second semiconductor switch C4 on and off in the first and the further device for switching error states.

A first internal busbar RL1 is sufficient for carrying out semiconductor-based one-time errors. This in 3 shown embodiment shows in principle that in 2 shown embodiment, in which embodiment a second internal busbar RL2 is provided. Two universal busbars RL1, RL2 allow, for example, the integration of external two-terminal networks (e.g. resistor, voltage source, current sink, measuring device, ...). The second internal busbar RL2 is connected to the common signal path 2 and connected to the first signal path ECU1 via the ninth switch E1R2 and to the second signal path ECUn via the tenth switch EnR2. The busbar RL2 was provided in this exemplary embodiment in order to also allow multiple faults such as simultaneous short-to-Vbat and short-to-GND on a relay basis. In addition, the second busbar RL2 also offers extended options for the integration of central components such as a device for resistance simulation. This means at least an adjustable electrical resistor whose resistance value can be configured using computer software, for example to simulate a simulated electrical component. With an additional internal busbar (connected via E1R2, ..., EnR2) and a second semiconductor switch C4 (with relay C3), load shedding through a semiconductor switch ( C4) possible.

In 4 1 shows a circuit diagram of a device for switching error states in a simulation environment according to a further exemplary embodiment of the invention. The device includes a first connection potential GND and a second connection potential VBat. In a preferred embodiment of the invention, the first connection potential GND is a ground potential and the second connection potential VBat is a supply potential. In a particularly preferred embodiment, the supply potential is a battery voltage, for example.

The first busbar RL1 is connected to the first connection potential GND by means of the thirteenth switch CR4. In addition, the in 4 The device shown has a fourteenth switch CRS, which is set up to connect the first busbar RL1 to the second connection potential VBat. The first internal busbar RL1 is connected to a first external busbar exRL1 via the seventh switch CR1 and the second internal busbar RL2 is connected to a second external busbar exRL2 via the twelfth switch CR2. The addition of the switches CR1, CR2, CR4 and CRS makes it possible, in addition to connections to the two external busbars exRL1, exRL2, to switch direct short-circuits to, for example, hard-wired connection potentials GND and VBat. The individual devices for switching error states in a simulation environment can can be used directly for error simulation without additional components. In addition, the additional connection potentials can be switched to other busbar-based faults at the same time, so that more faults of different classes can be switched at the same time.

For example, in an embodiment of the invention, a method includes the following steps. A short circuit to the first connection potential GND can be simulated by closing the fourteenth switch CR5 or a short circuit to the second connection potential VBat can be simulated by closing the thirteenth switch CR4.

Further short-circuits to the connection potentials can thus be switched independently of the use of the busbars, so that, for example, triple or even quadruple short-circuits to GND, VBat and two other busbar potentials are possible. The local connection of the GND and VBat connection potentials ultimately simplifies the system complexity from the user's point of view, because he no longer has to ensure that the external busbars are assigned the correct potential if an error is to be switched.

in the in 5 In the exemplary embodiment shown, the flexibility when switching different error states on different channels can be increased by adding a further switch in each case to the fifteenth switch E1R3 and the sixteenth switch EnR3 combined with the introduction of a third internal busbar RL3 with a seventeenth switch CR3. The seventeenth switch CR3 is connected in series with the fifteenth switch E1R3 and the sixteenth switch EnR3 and connects a first connection potential GND to the third busbar RL3. The first connection potential GND is connected to the second busbar RL2 by means of an eighteenth switch CR6. A twentieth switch CR7 is used to connect the second internal busbar RL2 to the first connection potential VBat. The third internal busbar allows increased independence of the faults that are switched locally on a module, so that different fault patterns can be switched independently both locally and globally. A local intelligence, for example in the device for switching error states in a simulation environment, can decide in these cases, for example, to use the additional path in the case of multiple errors. In general, it is thus possible to further increase the number of error classes that can be connected in parallel by adding further internal busbars RL1, RL2, RL3. Furthermore, the in 5 circuit shown a nineteenth switch C5. The nineteenth switch C5 connects the third busbar RL3 to the common signal path 2.

All of the features explained in connection with individual embodiments of the invention can be provided in different combinations in the subject matter according to the invention in order to simultaneously realize their advantageous effects, even if they have been described for different embodiments.

The scope of protection of the present invention is given by the patent claims and is not limited by the features explained in the description or shown in the figures.

Reference List

1

connection unit

2

Common signal path

RL1

first internal busbar

RL2

second internal busbar

RL3

third internal busbar

exRL1

first external busbar

exRL2

second external busbar

ECU1

first signal path

ECUs

second signal path

MRS

error forwarding facility

FIU

fault injection unit

LD1

First load

LDn

second load

S1

first switch

sn

second switch

E1R1

third switch

L1R2

fourth switch

EnR1

fifth switch

LnR2

sixth switch

CR1

seventh switch

C1

eighth switch

C2

first semiconductor switch

E1R2

ninth switch

EnR2

tenth switch

C3

eleventh switch

C4

second semiconductor switch

CR2

twelfth switch

CR4

thirteenth switch

CR5

fourteenth switch

E1R3

fifteenth switch

EnR3

sixteenth switch

CR3

seventeenth switch

CR6

eighteenth switch

C5

nineteenth switch

CR7

twentieth switch

GND

first connection potential

vbat

second connection potential

Claims (17)

Device for switching error states in a simulation environment, the device comprising: - at least a first internal busbar (RL1), - at least one first signal path (ECU1), the first signal path (ECU1) being routed from a first control unit connection of an electronic control unit via a first switch (S1) to a first load (LD1), - At least one second signal path (ECUn), the second signal path being routed from a second control device connection of an electronic control device via a second switch (Sn) to a second load (LDn), the device further comprising: - set up an error forwarding device (FRU) in order to select at least one of the signal paths (ECU1, ECUn), - An error introduction unit (FIU) set up to switch different error states, the error introduction unit (FIU) comprising a connection unit (1) for connecting the signal paths (ECU1, ECUn) to the first internal busbar (RL1), set up in such a way that a switchable connection of the first signal path (ECU1) and the second signal path (ECUn) to the first internal busbar (RL1), wherein the signal paths (ECU1, ECUn) are led to a common signal path (2) and can be connected to the common signal path (2) in a switchable manner are, wherein the common signal path (2) comprises a first semiconductor switch (C2), set up in such a way to switch the error states, the error forwarding device (FRU) comprises at least a third switch (E1R1) and a fourth switch (L1R2), set up the first signal path ( Connect ECU1) to the connection unit (1), the error forwarding device (FRU) comprises at least a fifth switch (EnR1) and a sixth switch (LnR2), set up to connect the second signal path (ECUn) to the connection unit (1), wherein the first semiconductor switch (C2) can be connected in a switchable manner to at least the third switch (E1R1) or the fifth switch (EnR1), the connection unit (1) comprises at least one seventh switch (CR1) for connecting the internal busbar (RL1) to an external busbar (exRL1). device after claim 1 , characterized in that the device comprises a ninth switch (E1R2) set up to connect the common signal path (2) to the first signal path (ECU1) and a tenth switch (EnR2) set up to connect the common signal path (2) to the second signal path (ECUn) to connect, the connection unit (1) in the common signal path (2) between the connection to the signal paths (ECU1, ECUn) via the ninth switch (E1R2) and the tenth switch (EnR2) and the connection to the signal paths (ECU1, ECUn) comprises a second semiconductor switch (C4) via the fourth switch (L1R2) and the sixth switch (LnR2) for switching error states, the common signal path (2) being branched off before the first internal busbar (RL1) and the first semiconductor switch ( C2) includes. device after claim 2 , characterized in that the device comprises a second internal busbar (RL2), wherein the second internal busbar (RL2) is connected to the common signal path (2), via the ninth switch (E1R2) to the first signal path (ECU1) is connected and is connected to the second signal path (ECUn) via the tenth switch (EnR2), the connection unit (1) comprises a twelfth switch (CR2), set up to connect the second internal busbar (RL2) to a second external busbar (exRL2). device after claim 3 , characterized in that the device comprises a first connection potential (GND) and a second connection potential (VBat), the connection unit (1) comprises a thirteenth switch (CR4), set up the first internal busbar (RL1) to the second connection potential (VBat) to connect and a fourteenth switch (CR5), set up to connect the first internal busbar (RL1) to the first connection potential (GND). device after claim 4 , characterized in that the device comprises a third internal busbar (RL3), the third internal busbar (RL3) via a fifteenth switch (E1R3) to the first signal path (ECU1) and via a sixteenth switch (EnR3) is connected to the second signal path (ECUn), the connection unit (1) comprises a seventeenth switch (CR3), set up to connect the third busbar (RL3) to the first connection potential (GND), the connection unit (1) has an eighteenth switch (CR6), configured to connect the first connection potential (GND) to the second internal busbar (RL2), the connection unit (1) includes a twentieth switch (CR7), configured to connect the second internal busbar (RL2) to the second connection potential (VBat) and the connection unit (1) comprises an eighth switch (C1) in the common signal path (2), set up in such a way to decouple the first semiconductor switch (C2) and optionally the second internal busbar (RL2) via an eleventh switch (C3) or via a nineteenth switch (C5) to connect the third internal busbar (RL3). Device according to one of the preceding claims, characterized in that a plurality of devices for switching error states in a simulation environment are connected to one another via at least one external busbar (exRL1, exRL2). Device according to one of the preceding claims, characterized in that the semiconductor switches are MOSFETs. Method for switching error states in a simulation environment, the method comprising the following steps: - Providing a device for switching error states in a simulation environment according to one of the preceding claims, - Pre-configuration of the device for switching error states in a simulation environment in a pre-configuration phase, - Simulating error states by changing the switching states of the switches of the device. procedure after claim 8 , characterized in that the error states are simulated by switching the first and/or the second semiconductor switch (C2, C4). procedure after claim 9 , characterized in that the steps of preconfiguring the device in a preconfiguration phase and simulating error states by switching the semiconductor switches comprises at least one of the following error states: - simulating a cable break using the first semiconductor switch (C2) via the first signal path (ECU1), wherein the pre-configuration step comprises the following steps: - closing the third switch (E1R1), the fourth switch (L1R2) and the first semiconductor switch (C2), - opening the first switch (S1), - simulating the cable break by switching on and off Turning off the first semiconductor switch (C2) or - simulating a short circuit to a connection potential by means of the first semiconductor switch (C2) via the first signal path (ECU1), the step of preconfiguration comprising the following steps: - preassigning the first internal busbar (RL1) with a connection potential, - closing the third switch (E1R1) and the seventh switch (CR1), - simulating a short circuit by switching the first semiconductor switch (C2) on and off, or - simulating a cross short circuit between a first device for switching error states in a simulation environment and a further device for switching error states in a simulation environment by means of the first semiconductor switch (C2) via the first signal path (ECU1), wherein the step of preconfiguration comprises the following steps: - closing the third switch (E1R1) and the seventh switch (CR1 ), - simulating a cross-short circuit by switching the first semiconductor switch (C2) on and off on the first and the further device for switching error states in a simulation environment. Procedure according to one of Claims 8 until 10 , characterized in that the device comprises a second semiconductor switch (C4), wherein the second semiconductor switch (C4) is initially conductive and the first semiconductor switch (C2) is initially non-conductive, the steps of pre-configuring the device in a pre-configuration phase and simulating error states by switching the switches includes at least one of the following error states: - simulating a cable break using the second semiconductor switch (C4) via the first signal path (ECU1), and the step of preconfiguration includes the following steps: - closing the ninth switch (E1R2), the eleventh switch (C3) and the fourth switch (L1R2), - opening the first switch (S1), - simulating the cable break by switching the second semiconductor switch (C4) on and off, or - simulating a short circuit to a first connection potential (GND) or a second connection potential (VBat) or to an external busbar (extRL1, ext RL2) by means of the first semiconductor switch (C2) and the second semiconductor switch (C4) via the first signal path (ECU1), the step of pre-configuration comprising the following steps: - Pre-assignment of the first internal busbar (RL1) with the first connection potential (GND) or the second connection potential (VBat) or with an external busbar (extRL1, extRL2), - Closing the ninth switch (E1R2), the eighth switch (C1), the seventh switch (CR1) , the eleventh switch (C3) and the fourth switch (L1R2), - opening the first switch (S1), - simulating a short circuit by switching the first semiconductor switch (C2) and the second semiconductor switch (C4) on and off, or - simulating a Cross-short circuit between a first device for switching error states in a simulation environment and a further device for switching error states in a simulation environment by means of the first semiconductor switch (C2) via the first signal path (ECU1), the step of preconfiguration comprising the following steps: - closing the ninth switch (E1R2), the eighth switch (C1), the seventh switch (CR1), the eleventh switch (C3), the fourth switch (L1R2) respectively in the first and the further device for switching fault conditions, - opening the first switch (S1) in the first and the further device for switching error states, - simulating a cross-short circuit by switching on and off the first semiconductor switch (C2) and the second semiconductor switch (C4) in the first and the further device for switching error conditions. procedure after claim 11 , characterized in that the device comprises a second internal busbar (RL2), wherein the second internal busbar (RL2) is connected to the common signal path (2), via the ninth switch (E1R2) to the first signal path (ECU1) is connected , is connected to the second signal path (ECUn) via the tenth switch (EnR2) and the method comprises the following additional steps: - Switching at least one second fault via the second internal busbar (RL2) and/or the method comprises the following additional step : - Integration of a resistance simulation device via the internal busbars (RL1, RL2). procedure after claim 12 , characterized in that the device comprises a first connection potential (GND), the device comprises a second connection potential (VBat), the connection unit (1) comprises a fourteenth switch (CR5), the first internal busbar (RL1) is set up at the first connection potential (GND) and a thirteenth switch (CR4), set up to connect the first internal busbar (RL1) to the second connection potential (VBat), the first internal busbar (RL1) via the seventh switch (CR1) to a first external busbar (exRL1) and the second internal busbar (RL2) is connected to a second external busbar (exRL2) via the twelfth switch (CR2), and the method comprises the following additional steps: - simulating a short circuit to the first connection potential (GND ) by closing the fourteenth switch (CR5) and/or - simulating a short circuit to the second connection potential (VBat) by closing the thirteenth switch (CR4). Procedure according to one of Claims 8 until 13 , characterized in that error states are simulated via the second signal path (ECUn) and the device is preconfigured in a preconfiguration phase by means of the switches of the second signal path (ECUn). Procedure according to one of Claims 8 until 13 , characterized in that a single error condition or a plurality of error conditions are switched simultaneously. Use of the device and the method for switching error states in a simulation environment in a HIL simulator. Computer program product comprising instructions that cause the device of Claims 1 until 7 the process steps according to one of Claims 8 until 15 executes

Images