DE102016224747A1 - control unit - Google Patents

Abstract

The invention relates to a control unit (10), in particular for an internal combustion engine, having a first arithmetic unit (12), characterized in that at least one further arithmetic unit (14), in particular for expanding the computing power of the first arithmetic unit (12), in the control unit (12). 10) is arranged, wherein the first and the at least one further computing unit (12, 14) via at least one bus system (16) are interconnected.

Description

State of the art

The invention relates to a control unit, in particular for an internal combustion engine, having a first arithmetic unit.

Currently known control devices typically include an electronic processing unit, e.g. exists in the form of an embedded system. The size of the electronic processing unit varies depending on the complexity of the tasks.

Disclosure of the invention

The problem underlying the invention is solved by a control device according to claim 1. Advantageous developments are specified in the subclaims. Features which are important for the invention can also be found in the following description and in the drawings, wherein the features, both alone and in different combinations, can be important for the invention, without being explicitly referred to again.

The invention relates to a control unit, in particular for an internal combustion engine, having a first arithmetic unit, wherein at least one further arithmetic unit, in particular for expanding the computing power of the first arithmetic unit, is arranged in the control unit. In this case, the first and the at least one further arithmetic unit are connected to one another via at least one bus system.

The first and the at least one further arithmetic unit are preferably designed to process data. The further arithmetic unit can be designed, for example, to read and / or process substantially similar information and data in a comparable manner and / or output as the first arithmetic unit. The processing of the data (or at least part of it) by the further arithmetic unit takes place, for example, when an application, in particular a safety-critical application, is to be executed in the primary arithmetic unit. In this case, the further arithmetic unit can perform a substantially similar processing of the first data. When this application is finished, output data (in particular the processed data) of the respective primary and further computing units can be compared with one another in a manner known per se.

The further arithmetic unit is preferably designed to expand the computing power of the first arithmetic unit. In this case, the further arithmetic unit can be designed, for example, to execute a further application, in particular an application executed solely on the further arithmetic unit.

In particular for exchanging data, the first and the further arithmetic units are connected to one another via a bus system, which comprises, for example, an address bus and a data bus. Alternatively or additionally, other connection means may also be present, which allow a data exchange between the first processing unit and the further processing unit, for example at least one switching network.

In a further refinement, the first computing unit is a microcontroller comprising at least one processor, at least one random access memory (RAM, random access memory, also referred to as "main memory") and / or at least one read-only memory (for example ROM, read only memory). In this case, the at least one further arithmetic unit is preferably a microprocessor or a microcontroller or a digital signal processor or an FPGA or an ASIC. In a preferred variant, the at least one further arithmetic unit can also comprise a plurality of the abovementioned components or combinations thereof.

In preferred embodiments, the first arithmetic unit designed as a microcontroller can perform comparatively complex functions and, for example, control other components of the control device, in particular other integrated circuits, ICs, or their operation. In the microcontroller or a memory associated with the microcontroller are usually also necessary for the operation of data, maps and / or programs, preferably for other components stored.

The further arithmetic unit, by means of which advantageously a computing power expansion of the first arithmetic unit can be realized, can also be, for example, a microcontroller or preferably a microprocessor or a digital signal processor or an FPGA or an ASIC. ASICs are application-specific integrated circuits (application-specific integrated circuits). An FPGA refers to a Field Programmable Gate Array.

In a preferred embodiment, the read-only memory of the first processing unit for the transmission of data to the further processing unit, which is for example a microprocessor is formed. For example, it is conceivable that the program required for the operation of the further arithmetic unit in the read-only memory of the first Arithmetic unit is stored. For example, the first arithmetic unit can read the required program from the read-only memory and make it available to the further arithmetic unit.

Preferably, the second arithmetic unit has a computing power in the range of at least about 6 DMips per megahertz, Dhrystone MIPS, millions of instructions per second, more preferably about 8 DMips per megahertz, thereby providing efficient computational power expansion for the first arithmetic unit.

In a preferred embodiment, the first and the at least one further computing unit are on a first semiconductor substrate, i. on the same semiconductor substrate. A semiconductor substrate is understood, for example, as meaning a chip, that is to say an unhoused piece of semiconductor wafer, "the". The integration of the first and the further arithmetic unit on a common semiconductor substrate enables communication and data exchange between the first and the further arithmetic unit directly on the semiconductor substrate. In this way, the first and the further arithmetic unit are already integrated in a common semiconductor substrate during production, and in particular the fabrication of the first and the at least one further arithmetic unit takes place using the same semiconductor manufacturing technology or semiconductor manufacturing processes.

In a further particularly preferred embodiment, the production of the first semiconductor substrate with the first and the at least one further processing unit using "automotive design rules" done, ie manufacturing rules for semiconductor manufacturing, which are suitable for applications in the automotive sector, which advantageously better properties Electromigration, irradiation, radiation, failure rate and the like can be achieved compared to semiconductor circuits for consumer (consumer) applications. As a result, the semiconductor substrate manufactured according to the present embodiment or the computing units contained therein has a particularly low failure rate, a comparatively large operating temperature range, a comparatively low power consumption, and a high long-term availability, so that they are particularly well suited for safety-critical applications.

In a further advantageous embodiment, the first arithmetic unit is arranged on a first semiconductor substrate, and the at least one further arithmetic unit is arranged on a further, different from the first semiconductor substrate, the semiconductor substrate. In this case, it is conceivable that the further semiconductor substrate is mounted on the first semiconductor substrate by means of "flip-chip mounting" (German: reversal mounting) without further connecting wires with an active contacting side to the first semiconductor substrate. The flip-chip mounting advantageously enables the electrical contacting with the first semiconductor substrate simultaneously with the placement of the further semiconductor substrate.

In one embodiment, the first and / or the at least one further computing unit is assigned at least one cache memory. The cache memory, which is a fast buffer, ensures fast access to data for the first or the next processor. In further advantageous embodiments, both a first-level cache and a second-level cache can be provided. According to one embodiment, the cache memory (s) may also be arranged in the region of the second arithmetic unit, which is embodied, for example, as a microprocessor. It is also conceivable that the cache memory (s) can be used in the execution of applications on the first computing unit and / or the second or further computing unit.

In a further refinement, the at least one further arithmetic unit is assigned a read-only memory (ROM). The read-only memory is designed in particular as a flash memory with a serial data interface. In the read-only memory, for example, at least one program or the software for the at least one further arithmetic unit is stored. As an alternative or in addition, the further arithmetic unit may also be provided with a program provided for execution by the first arithmetic unit, for example from a read-only memory assigned to the first arithmetic unit.

In a further embodiment, at least one means, in particular contacting means, for electrical contacting exhibiting substrate element (English: "interposer") is provided, wherein at least the first semiconductor substrate is disposed on a first surface of the substrate element. Furthermore, the substrate element comprises a second surface opposite the first surface, which is preferably provided for contacting with a carrier plate, for example a circuit board (board).

By means of the substrate element, for example comparatively finely structured connections of the semiconductor substrate are converted to comparatively large structures, which are required in particular for the connection to a carrier plate or circuit board. As mentioned above, this connection technique is also called "Interposer" called. The substrate element, which serves as an interposer, usually consists of glass or silicon and comprises, for example, contact surfaces, rewiring, plated-through holes and possibly active and / or non-active components.

The semiconductor substrate may for example be mounted on the surface of the substrate element by means of the above-described flip-chip mounting or by means of the known bonding technology. In the bonding technology, the contacting is usually done with a thin bonding wire (bonding wire), which is pulled from the semiconductor substrate directly to the substrate element, or vice versa. The permanent contacting of the wire, for example, by a welding process.

In a further embodiment, at least one random access memory (RAM, main memory) is arranged on at least one substrate element for connection to the first and / or the further arithmetic unit, whereby short line lengths and correspondingly good connection conditions are created. In this way, comparatively large main memories for the control device according to the invention can be provided.

In a further refinement, a memory interface is provided for connecting the at least one further arithmetic unit to a random access memory. Via the memory interface, the further arithmetic unit can preferably be connected to an external memory, preferably a random access memory (RAM).

Furthermore, it can be provided that the memory interface for connection of the at least one further arithmetic unit with a random access memory on the upper side of the substrate element is guided to the outside and in particular is a DDR memory interface.

The memory interface is preferably a DDR interface, double data rate interface. DDR refers to a method by which data can be transmitted on a data bus at a higher, in particular double, data rate than in a conventional data bus. The random access memory is preferably a DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory). It is also conceivable that the interface is a DDR2, DDR3 or DDR4 interface and the random access memory is a DDR2 SDRAM, DDR3 SDRAM or DDR4 SDRAM.

In a further embodiment, a heat-conducting device, in particular a heat-conducting sheet or heat-conducting pad, is provided for deriving the heat-dissipating power of at least one of the computing units.

The heat-conducting device serves to dissipate the heat loss power arising during operation of the arithmetic unit (s). Since the waste heat in the control unit is not uniform but depending on the load, in particular punctually and locally e.g. At the computing units, the heat-conducting device has the task of distributing the waste heat over a larger area in order to be able to more efficiently couple it into a heat sink.

Furthermore, it can be provided that the heat-conducting device is in thermal contact with at least one of the computing units and a housing part, so that the heat dissipation capacity of the at least one arithmetic unit can be derived via the housing part, ie advantageously directly to an outside of the housing of the control unit.

In one preferred embodiment, for example, the heat-conducting device can be placed directly on the semiconductor substrate so that it is in thermal contact with one of the arithmetic units. For better contacting of the arithmetic unit with the heat-conducting device, for example, a thermal compound or liquid metal may be provided between the arithmetic unit and the heat-conducting device.

• 1 eine schematische Darstellung eines erfindungsgemäßen Steuergeräts mit einer ersten und einer weiteren Recheneinheit;
• 2A eine schematische Anordnung von zwei Recheneinheiten gemäß einer ersten Ausführungsform;
• 2B eine schematische Anordnung von zwei Recheneinheiten gemäß einer zweiten Ausführungsform;
• 2C eine schematische Anordnung von zwei Recheneinheiten gemäß einer dritten Ausführungsform;
• 3 eine schematische Anordnung von zwei Recheneinheiten auf einem Substratelement, und
• 4 eine schematische Anordnung mit einer Wärmeleitvorrichtung.

Hereinafter, exemplary embodiments of the invention will be explained with reference to the drawings. In the drawing show:

• 1 a schematic representation of a control device according to the invention with a first and a further processing unit;
• 2A a schematic arrangement of two computing units according to a first embodiment;
• 2 B a schematic arrangement of two arithmetic units according to a second embodiment;
• 2C a schematic arrangement of two arithmetic units according to a third embodiment;
• 3 a schematic arrangement of two computing units on a substrate element, and
• 4 a schematic arrangement with a heat conducting device.

The same reference numerals are used for functionally equivalent elements and sizes in all figures, even in different embodiments.

The 1 shows a highly simplified schematic representation of a control device according to the invention 10 which is a first arithmetic unit 12 and another arithmetic unit 14 includes. The first arithmetic unit 12 is present as a microcontroller 12 and preferably comprises at least one processor, at least one random access memory (RAM) and / or at least one read-only memory (ROM and / or (flash) EEPROM). The further arithmetic unit 14 is present as a microprocessor 14 executed and preferably serves as a computing power extension for the first processing unit 12 ,

Alternatively, it is also conceivable that the further arithmetic unit 14 as a microcontroller or digital signal processor or as a programmable logic device (FPGA) or ASIC (application specific integrated circuit) is realized. The first arithmetic unit 12 and the further arithmetic unit 14 are, in particular for the exchange of data, via a bus system 16 connected with each other.

In a preferred embodiment, the bus system 16 a parallel bus system, in particular a high-speed bus system, with a plurality of data lines and address lines.

In one embodiment, the read only memory is the first arithmetic unit 12 for transferring data to the further processing unit 14 educated. It is conceivable, for example, that this is for the operation of the further arithmetic unit 14 required program in the read only memory of the first processing unit 12 is stored.

According to a first in 2A greatly simplified and schematically illustrated embodiment is the further processing unit 14 on the first semiconductor substrate 18 the first arithmetic unit 12 integrated. Advantageously, the further arithmetic unit 14 in a common manufacturing process with the first processor 12 on the semiconductor substrate 18 integrated. Preferably, the controller 10 , in particular the computing units 12 14 developed and designed in accordance with the design rules prevailing in the automotive industry and in compliance with and taking into account standards for safety-relevant electrical systems and thus meets the requirements of ASILD (Automotive Safety Integrity Level D).

On the first semiconductor substrate 18 there is an internal bus system 16 for connecting the first arithmetic unit 12 with the further arithmetic unit 14 , By the arrangement on a common semiconductor substrate 18 result in short latencies between the first and the other arithmetic unit 12 , 14 and a high bus bandwidth of the bus system 16 ,

In addition to the first and the further arithmetic unit 12 . 14 are preferably memory elements 20 such as random access memory (RAM, Random Access Memory), read-only memory (ROM, PROM, (Flash) EEPROM, non-volatile memory), cache memory and possibly other peripherals 22 such as CAN (Controller Area Network), LIN (Local Interconnect Network), I ² C (Inter-Integrated Circuit), USB, SPI (Serial Peripheral Interface), serial or Ethernet interfaces, PWM outputs, LCD controllers and drivers as well as analog-to-digital converters, programmable digital and / or analogue or hybrid function blocks on the semiconductor substrate 18 integrated.

According to an advantageous embodiment, an E / D element 24 (emulator / debugging element) is on the semiconductor substrate 18 integrated. The use of E / D elements in the area of the microcontroller as an extension on the semiconductor element of the microcontroller is advantageous because it provides an emulation / debugging application for the microcontroller. Preferably, the E / D element 24 comprises a random access memory. In one embodiment, the random access memory of the E / D element is a cache extension for the further processing unit 14 educated.

Advantageously, in this way the analysis and diagnostic functions provided by the E / D element 24, for example, the setting of breakpoints, even for the further processing unit 14 be implemented.

In a further advantageous embodiment it can be provided that the inventive at least one further computing unit 14 is also provided for the execution of emulation or debugging applications or together with a dedicated E / D element 24 of the first arithmetic unit 12 assigned. In other words, in one embodiment, the at least one further computing unit 14 also on an optionally existing E / D unit 24 of the first arithmetic unit 12 be provided or arranged.

According to a second in 2 B greatly simplified and schematically illustrated embodiment is the further processing unit 14 on another, from the first semiconductor substrate 18 different, semiconductor substrate 26 ,

The further semiconductor substrate 26 can be in addition to the further processing unit 14 an E / D element 24 include. In this case, the further semiconductor substrate 26 may be used as an E / D extension of the microcontroller 12 serve. In this case, the advantages already described above result in the implementation of the further computing unit 14 ,

Furthermore, the first and the further semiconductor elements comprise 18 . 26 next to the first and the further processing unit 12 . 14 preferably memory elements 20, such as random access memory (RAM, Random Access Memory), read-only memory (ROM, PROM, (Flash) EEPROM, non-volatile memory), cache memory and possibly other peripheral elements 22 such as CAN (Controller Area Network), LIN (Local Interconnect Network), I ² C (Inter-Integrated Circuit), USB, SPI (Serial Peripheral Interface), serial or Ethernet interfaces, PWM outputs, LCD controllers and drivers as well as analog-to-digital converters, programmable digital and / or analogue or hybrid function blocks.

According to a third in 2C greatly simplified and schematically illustrated embodiment is the further processing unit 14 on another semiconductor substrate 26 , wherein the further semiconductor substrate 26 on the first semiconductor substrate 18 is arranged.

The first semiconductor substrate 18 and the other semiconductor substrate 26 according to 2C are preferably functionally equivalent to the semiconductor substrates 18 . 26 out 2 B built up.

The further semiconductor substrate 26 can by means of conventional bonding methods on the first semiconductor substrate 18 to be assembled. Preferably, the further semiconductor substrate 26 by means of "flip-chip mounting" (dt. Wende mounting) without further connecting wires with an active contacting side to the first semiconductor substrate 18 toward the first semiconductor substrate 18 assembled. The flip-chip assembly allows the placement of the same time the electrical contacting of the semiconductor substrate 26 to his surroundings.

The computing units 12 . 14 are also via a bus system 16 connected. By the arrangement of the further semiconductor substrate 26 on the semiconductor substrate 18 result in short latencies between the first and the other arithmetic unit 12 . 14 and a high bus bandwidth of the bus system 16 ,

According to a in 3 shown further embodiment, the first semiconductor substrate 18 on which the first arithmetic unit 12 is arranged on a substrate element 28 arranged. The assembly can be done, for example, by means of the previously described "flip-chip assembly". In the in 3 The illustrated embodiment is the first semiconductor substrate 18 by means of the bonding technology on the surface of the substrate element 28 assembled. The contacting of semiconductor substrate 18 to substrate element 28 done with thin connecting wires 30 ,

On the first semiconductor substrate 18 is the further semiconductor substrate by means of flip-chip mounting 26 assembled. The semiconductor substrate 26 includes, for example, the E / D element 24, the further processing unit 14 , a random access memory 32 , eg RAM; and a memory interface 34 , preferably a DDR interface, for connecting the further processing unit 14 with an external memory, and other memory elements, such as cache memory and other peripheral elements 22 ,

On a first surface 36 of the substrate element 28 is a memory interface 38 led to the outside to connect to an external memory. The interface can, for example, be connected to an external RAM, preferably a DDR SDRAM. It is also conceivable to mount the external RAM directly on the substrate element. For example, the memory interface 38 mechanically formed by the BGA (English: ball grid array) type.

On a second surface 40 of the substrate element 28 that the first surface 36 in a preferred embodiment are solder balls 42 (English solder balls) arranged. These solder balls 42 can be connected by soldering, for example. With a support plate (not shown).

Further, the substrate element 28 in the embodiment shown with a read-only memory 44 , in particular a flash memory connected to a serial data interface (eg SPI). In the read-only memory 44 can, for example, data for the further processing unit 14 be deposited. In this case, the read-only memory is 44 for transferring data to the further processing unit 14 formed or over the substrate element 28 connected to this or connected.

According to a in 4 Shown embodiment, a heat conducting device 46 for deriving the heat loss performance of at least one of the computing units 12 . 14 intended. The heat conducting device 46 stands with one of the arithmetic units, preferably with both arithmetic units 12 . 14 in thermal contact. The computing units 12 . 14 are on the semiconductor substrates 18 . 26 arranged and are in the in 4 embodiment shown covered by the heat conducting device. For better contacting of the computing units 12 . 14 with the heat-conducting device 46 can, for example, a thermal paste or liquid metal between the computing units 12, 14 and the heat conducting device 46 be provided. The heat conducting device 46 realizes a thermal connection to a housing of the control unit 10 , A housing part 48 is in 4 indicated schematically. Consequently, by the in 4 illustrated embodiment a cooling of the computing units in 4 Realized "upwards".

The thermal resistance of the R _{th of} the heat conducting device 46 in a preferred embodiment is between about 4-6 K / W (Kelvin per watt).

In a further preferred embodiment, the first arithmetic unit 12 (FIG. 2A ) more than one additional arithmetic unit 14 assigned. For example, a first arithmetic unit designed as a microcontroller 12 be associated with two or four microprocessors, which are the other arithmetic units 14 in the sense of the above description. Particularly preferred may be any of the computing units 12 . 14 have their own, local cache memory, in particular a first-level cache.

In a particularly preferred embodiment, it is possible for the at least one further arithmetic unit 14 on an E / D extension 24 ( 2A ), ie with an optional E / D extension 24 for the first processing unit 12 to combine. This makes it possible to increase the computing power of the first processor 12 realizing further computing units 14 for example, in the same semiconductor manufacturing process as the first computing unit 12 manufacture.

Claims (13)

Control unit (10), in particular for an internal combustion engine, with a first arithmetic unit (12), characterized in that at least one further arithmetic unit (14), in particular for expanding the computing power of the first arithmetic unit (12), in the control unit (10) is arranged wherein the first and the at least one further computing unit (12, 14) are interconnected via at least one bus system (16). Control unit (10) after Claim 1 wherein the first arithmetic unit (12) is a microcontroller comprising at least one processor, at least one random access memory and / or at least one read only memory, and wherein the at least one further arithmetic unit (14) is a microcontroller or a microprocessor or a digital signal processor or an FPGA or ASIC is. Control unit (10) after Claim 1 or 2 wherein the further computing unit (14) has a computing power in the range of at least about 6 Dips, Dhrystone MIPS, millions of instructions per second, per megahertz, preferably at least about 8 DMips per megahertz. Control unit (10) according to one of the preceding claims, wherein the first and the at least one further computing unit (12, 14) on a first semiconductor substrate (18) is arranged. Control unit (10) according to one of Claims 1 to 3 wherein the first arithmetic unit (12) is arranged on a first semiconductor substrate (18) and wherein the further arithmetic unit (14) is arranged on a further semiconductor substrate (26) different from the first semiconductor substrate (18). Control unit (10) according to one of the preceding claims, wherein the first arithmetic unit (12) and / or the at least one further arithmetic unit (14) is assigned at least one cache memory. Control unit (10) according to one of the preceding claims, wherein the at least one further computing unit (14) is associated with a read only memory (44), wherein the read only memory is designed in particular as a flash memory with a serial data interface. Control unit (10) according to one of the preceding Claims 4 to 7 in which at least one substrate element (28) is provided for electrically contacting, and at least the first semiconductor substrate (18) are arranged on a first surface (36) of the substrate element (28), wherein the substrate element (28) forms one of the first surface (36 ) comprises opposing second surface (40) which is provided for contacting with a carrier plate. Control unit (10) after Claim 8 wherein at least one random access memory (32) is arranged on the substrate element (28) for connection to the first and / or the further computing unit. Control unit (10) according to one of the preceding claims, wherein a memory interface (34, 38) is provided for connecting the at least one further computing unit (14) with a random access memory. Control unit (10) after Claim 10 wherein the memory interface for connecting the at least one further arithmetic unit (14) with a random access memory on the first surface (36) of the substrate element (28) is led to the outside and in particular a DDR memory interface. Control unit (10) according to one of the preceding claims, wherein a heat conducting device (46), in particular a heat conducting sheet or heat conducting pad, for deriving the heat loss performance of at least one of the computing units (12, 14) is provided. Control unit (10) after Claim 12 in that the heat-conducting device (46) is in thermal contact with at least one of the arithmetic units (12, 14) and a housing part (48) so that the heat dissipation power of the at least one arithmetic unit (12, 14) can be dissipated via the housing part (48).

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