DE10197113T1 - Verbesserter spezieller Programmiermodus - Google Patents

Verbesserter spezieller Programmiermodus

Info

Publication number
DE10197113T1
DE10197113T1 DE10197113T DE10197113T DE10197113T1 DE 10197113 T1 DE10197113 T1 DE 10197113T1 DE 10197113 T DE10197113 T DE 10197113T DE 10197113 T DE10197113 T DE 10197113T DE 10197113 T1 DE10197113 T1 DE 10197113T1
Authority
DE
Germany
Prior art keywords
programming mode
special programming
improved special
improved
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10197113T
Other languages
English (en)
Other versions
DE10197113B3 (de
Inventor
Sundeep M Bajikar
Paul D Ruby
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE10197113T1 publication Critical patent/DE10197113T1/de
Application granted granted Critical
Publication of DE10197113B3 publication Critical patent/DE10197113B3/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
DE10197113T 2000-12-27 2001-11-28 Verfahren zum Aktivieren eines speziellen Programmiermodus eines Speichers und Einrichtung mit einem Speicher mit speziellem Programmiermodus Expired - Fee Related DE10197113B3 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/752,594 US7007131B2 (en) 2000-12-27 2000-12-27 Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory
US09/752,594 2000-12-27
PCT/US2001/044877 WO2002052576A1 (en) 2000-12-27 2001-11-28 Enhanced special programming mode

Publications (2)

Publication Number Publication Date
DE10197113T1 true DE10197113T1 (de) 2003-12-04
DE10197113B3 DE10197113B3 (de) 2013-09-12

Family

ID=25026964

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10197113T Expired - Fee Related DE10197113B3 (de) 2000-12-27 2001-11-28 Verfahren zum Aktivieren eines speziellen Programmiermodus eines Speichers und Einrichtung mit einem Speicher mit speziellem Programmiermodus

Country Status (6)

Country Link
US (1) US7007131B2 (de)
CN (1) CN100431055C (de)
DE (1) DE10197113B3 (de)
GB (1) GB2388227B (de)
TW (1) TWI250529B (de)
WO (1) WO2002052576A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6859399B1 (en) 2000-05-17 2005-02-22 Marvell International, Ltd. Memory architecture and system and multiport interface protocol
EP1318440B1 (de) * 2001-12-04 2005-08-17 STMicroelectronics S.r.l. Architektur und Verfahren zur Verwaltung einer Schnittstelle, basierend auf einem endlichen Automaten
US20040049617A1 (en) * 2002-09-05 2004-03-11 Integrated Circuit Solution Inc. Method of firmware update by USB interface
JP5055971B2 (ja) * 2006-11-16 2012-10-24 株式会社ニコン 表面処理方法及び表面処理装置、露光方法及び露光装置、並びにデバイス製造方法
US9727277B2 (en) * 2012-12-21 2017-08-08 Sandisk Technologies Llc Storage device and method for enabling hidden functionality
JP2014225309A (ja) * 2013-05-16 2014-12-04 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
CN104217757B (zh) * 2013-05-31 2018-01-05 华邦电子股份有限公司 非易失性存储器的编程方法
US9798493B2 (en) * 2013-12-16 2017-10-24 International Business Machines Corporation Firmware bypass for medium-access commands

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GB2172127B (en) * 1985-03-06 1988-10-12 Ferranti Plc Data compression system
ATE65632T1 (de) * 1985-07-08 1991-08-15 Siemens Ag Verfahren zum kontrollieren eines speicherzugriffs auf einer chipkarte und anordnung zur durchfuehrung des verfahrens.
JPH081760B2 (ja) * 1987-11-17 1996-01-10 三菱電機株式会社 半導体記憶装置
US4873705A (en) * 1988-01-27 1989-10-10 John Fluke Mfg. Co., Inc. Method of and system for high-speed, high-accuracy functional testing of memories in microprocessor-based units
US5053990A (en) * 1988-02-17 1991-10-01 Intel Corporation Program/erase selection for flash memory
JP2648840B2 (ja) * 1988-11-22 1997-09-03 株式会社日立製作所 半導体記憶装置
US5016009A (en) * 1989-01-13 1991-05-14 Stac, Inc. Data compression apparatus and method
JP3408552B2 (ja) * 1991-02-11 2003-05-19 インテル・コーポレーション 不揮発性半導体メモリをプログラム及び消去する回路とその方法
US5333300A (en) * 1991-02-11 1994-07-26 Intel Corporation Timing circuitry and method for controlling automated programming and erasing of a non-volatile semiconductor memory
US5559971A (en) * 1991-10-30 1996-09-24 I-Cube, Inc. Folded hierarchical crosspoint array
US5412793A (en) * 1991-12-03 1995-05-02 Intel Corporation Method for testing erase characteristics of a flash memory array
US5506803A (en) * 1992-04-01 1996-04-09 Intel Corporation Apparatus and method for minimizing verify time in a semiconductor memory by constantly charging n-well capacitance
US5509134A (en) * 1993-06-30 1996-04-16 Intel Corporation Method and apparatus for execution of operations in a flash memory array
FR2708763B1 (fr) * 1993-06-30 2002-04-05 Intel Corp Dispositif de mémoire flash, procédé et circuit de traitement d'un ordre d'utilisateur dans un dispositif de mémoire flash et système d'ordinateur comprenant un dispositif de mémoire flash.
US5526311A (en) * 1993-12-30 1996-06-11 Intel Corporation Method and circuitry for enabling and permanently disabling test mode access in a flash memory device
DE69427277T2 (de) * 1994-01-31 2001-09-13 St Microelectronics Srl Verfahren zur Programmierung und Prüfung eines nichtflüchtigen Speichers
JP3015661B2 (ja) * 1994-04-27 2000-03-06 株式会社東芝 不揮発性半導体メモリ
US5701266A (en) * 1995-12-14 1997-12-23 Intel Corporation Programming flash memory using distributed learning methods
US5729489A (en) * 1995-12-14 1998-03-17 Intel Corporation Programming flash memory using predictive learning methods
US5796746A (en) * 1995-12-22 1998-08-18 Micron Technology, Inc. Device and method for testing integrated circuit dice in an integrated circuit module
US5873113A (en) * 1996-09-24 1999-02-16 Altera Corporation System and method for programming eprom cells using shorter duration pulse(s) in repeating the programming process of a particular cell
US5974499A (en) * 1997-04-23 1999-10-26 Micron Technology, Inc. Memory system having read modify write function and method
US5959911A (en) * 1997-09-29 1999-09-28 Siemens Aktiengesellschaft Apparatus and method for implementing a bank interlock scheme and related test mode for multibank memory devices
JPH11203266A (ja) * 1998-01-07 1999-07-30 Mitsubishi Electric Corp マイクロコンピュータ
US6834323B2 (en) * 2000-12-26 2004-12-21 Intel Corporation Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory

Also Published As

Publication number Publication date
DE10197113B3 (de) 2013-09-12
TWI250529B (en) 2006-03-01
US20020080652A1 (en) 2002-06-27
WO2002052576A1 (en) 2002-07-04
GB2388227A (en) 2003-11-05
CN1502111A (zh) 2004-06-02
CN100431055C (zh) 2008-11-05
GB2388227B (en) 2005-04-20
GB0315744D0 (en) 2003-08-13
US7007131B2 (en) 2006-02-28

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