FR2708763B1 - Dispositif de mémoire flash, procédé et circuit de traitement d'un ordre d'utilisateur dans un dispositif de mémoire flash et système d'ordinateur comprenant un dispositif de mémoire flash. - Google Patents

Dispositif de mémoire flash, procédé et circuit de traitement d'un ordre d'utilisateur dans un dispositif de mémoire flash et système d'ordinateur comprenant un dispositif de mémoire flash.

Info

Publication number
FR2708763B1
FR2708763B1 FR9407936A FR9407936A FR2708763B1 FR 2708763 B1 FR2708763 B1 FR 2708763B1 FR 9407936 A FR9407936 A FR 9407936A FR 9407936 A FR9407936 A FR 9407936A FR 2708763 B1 FR2708763 B1 FR 2708763B1
Authority
FR
France
Prior art keywords
memory device
flash memory
circuit
computer system
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9407936A
Other languages
English (en)
Other versions
FR2708763A1 (fr
Inventor
Mickey Lee Fandrich
Richard J Durante
Rodney R Rozman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of FR2708763A1 publication Critical patent/FR2708763A1/fr
Application granted granted Critical
Publication of FR2708763B1 publication Critical patent/FR2708763B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
FR9407936A 1993-06-30 1994-06-28 Dispositif de mémoire flash, procédé et circuit de traitement d'un ordre d'utilisateur dans un dispositif de mémoire flash et système d'ordinateur comprenant un dispositif de mémoire flash. Expired - Fee Related FR2708763B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US8558793A 1993-06-30 1993-06-30

Publications (2)

Publication Number Publication Date
FR2708763A1 FR2708763A1 (fr) 1995-02-10
FR2708763B1 true FR2708763B1 (fr) 2002-04-05

Family

ID=22192627

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9407936A Expired - Fee Related FR2708763B1 (fr) 1993-06-30 1994-06-28 Dispositif de mémoire flash, procédé et circuit de traitement d'un ordre d'utilisateur dans un dispositif de mémoire flash et système d'ordinateur comprenant un dispositif de mémoire flash.

Country Status (2)

Country Link
US (1) US5692138A (fr)
FR (1) FR2708763B1 (fr)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69724318T2 (de) * 1996-04-02 2004-05-27 STMicroelectronics, Inc., Carrollton Prüfung und Reparatur einer eingebetteten Speicherschaltung
US6275911B1 (en) * 1996-09-20 2001-08-14 Denso Corporation Memory writing device for an electronic device
US5973967A (en) * 1997-01-03 1999-10-26 Programmable Microelectronics Corporation Page buffer having negative voltage level shifter
JP4111472B2 (ja) * 1998-05-15 2008-07-02 キヤノン株式会社 通信制御方法及び装置及び通信システム
US6640267B1 (en) * 1999-09-27 2003-10-28 Cypress Semiconductor Corp. Architecture for multi-queue storage element
US6640300B1 (en) * 1999-09-27 2003-10-28 Cypress Semiconductor Corp. Method and apparatus for width and depth expansion in a multi-queue system
KR20020029760A (ko) * 2000-06-27 2002-04-19 롤페스 요하네스 게라투스 알베르투스 집적 회로 시스템
US6834323B2 (en) 2000-12-26 2004-12-21 Intel Corporation Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory
US6732306B2 (en) 2000-12-26 2004-05-04 Intel Corporation Special programming mode with hashing
US7007131B2 (en) * 2000-12-27 2006-02-28 Intel Corporation Method and apparatus including special programming mode circuitry which disables internal program verification operations by a memory
US7042770B2 (en) * 2001-07-23 2006-05-09 Samsung Electronics Co., Ltd. Memory devices with page buffer having dual registers and method of using the same
US6961796B2 (en) * 2001-07-26 2005-11-01 Hewlett-Packard Development Company, L.P. Extendable bus interface
JP2004348817A (ja) * 2003-05-20 2004-12-09 Sharp Corp 半導体記憶装置、そのページバッファリソース割当方法及び回路、コンピュータシステム並びに携帯電子機器
JP2004348790A (ja) * 2003-05-20 2004-12-09 Sharp Corp 半導体記憶装置及び携帯電子機器
ITRM20030354A1 (it) * 2003-07-17 2005-01-18 Micron Technology Inc Unita' di controllo per dispositivo di memoria.
TW200743957A (en) * 2006-05-16 2007-12-01 Ite Tech Inc Control device and control method for memory
US8213229B2 (en) * 2008-08-22 2012-07-03 HGST Netherlands, B.V. Error control in a flash memory device
KR20110013868A (ko) * 2009-08-04 2011-02-10 삼성전자주식회사 멀티 코멘드 셋 동작 및 우선처리 동작 기능을 갖는 멀티 프로세서 시스템
US8645618B2 (en) * 2011-07-14 2014-02-04 Lsi Corporation Flexible flash commands
US8806112B2 (en) 2011-07-14 2014-08-12 Lsi Corporation Meta data handling within a flash media controller
US10310923B1 (en) 2014-08-28 2019-06-04 Seagate Technology Llc Probabilistic aging command sorting
US9921763B1 (en) 2015-06-25 2018-03-20 Crossbar, Inc. Multi-bank non-volatile memory apparatus with high-speed bus
US10141034B1 (en) 2015-06-25 2018-11-27 Crossbar, Inc. Memory apparatus with non-volatile two-terminal memory and expanded, high-speed bus
US10222989B1 (en) * 2015-06-25 2019-03-05 Crossbar, Inc. Multiple-bank memory device with status feedback for subsets of memory banks
US10095617B2 (en) * 2015-09-22 2018-10-09 Macronix International Co., Ltd. Memory device with flexible data transfer rate interface and method thereof
US10831403B2 (en) 2017-05-19 2020-11-10 Seagate Technology Llc Probabalistic command aging and selection

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680701A (en) * 1984-04-11 1987-07-14 Texas Instruments Incorporated Asynchronous high speed processor having high speed memories with domino circuits contained therein
JPH0688427B2 (ja) * 1987-04-15 1994-11-09 キヤノン株式会社 出力装置
US4905184A (en) * 1987-09-21 1990-02-27 Unisys Corporation Address control system for segmented buffer memory
US5222046A (en) * 1988-02-17 1993-06-22 Intel Corporation Processor controlled command port architecture for flash memory
US5053990A (en) * 1988-02-17 1991-10-01 Intel Corporation Program/erase selection for flash memory
US4992958A (en) * 1988-06-27 1991-02-12 Hitachi, Ltd. Method and apparatus for controlling printer
DE69033438T2 (de) * 1989-04-13 2000-07-06 Sandisk Corp Austausch von fehlerhaften Speicherzellen einer EEprommatritze
US5065364A (en) * 1989-09-15 1991-11-12 Intel Corporation Apparatus for providing block erasing in a flash EPROM
US5159672A (en) * 1989-12-28 1992-10-27 Intel Corporation Burst EPROM architecture
US5177745A (en) * 1990-09-26 1993-01-05 Intel Corporation Memory device with a test mode
US5249158A (en) * 1991-02-11 1993-09-28 Intel Corporation Flash memory blocking architecture
US5233559A (en) * 1991-02-11 1993-08-03 Intel Corporation Row redundancy for flash memories
US5265059A (en) * 1991-05-10 1993-11-23 Intel Corporation Circuitry and method for discharging a drain of a cell of a non-volatile semiconductor memory
US5245572A (en) * 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
US5224070A (en) * 1991-12-11 1993-06-29 Intel Corporation Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory

Also Published As

Publication number Publication date
FR2708763A1 (fr) 1995-02-10
US5692138A (en) 1997-11-25

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Effective date: 20090228