FR2675921B1 - Procede et dispositif de test d'une carte d'un systeme informatique. - Google Patents

Procede et dispositif de test d'une carte d'un systeme informatique.

Info

Publication number
FR2675921B1
FR2675921B1 FR9105430A FR9105430A FR2675921B1 FR 2675921 B1 FR2675921 B1 FR 2675921B1 FR 9105430 A FR9105430 A FR 9105430A FR 9105430 A FR9105430 A FR 9105430A FR 2675921 B1 FR2675921 B1 FR 2675921B1
Authority
FR
France
Prior art keywords
testing
card
computer system
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9105430A
Other languages
English (en)
Other versions
FR2675921A1 (fr
Inventor
Sauvage Pierre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Priority to FR9105430A priority Critical patent/FR2675921B1/fr
Priority to EP92420135A priority patent/EP0515290A1/fr
Priority to JP4106567A priority patent/JPH06180657A/ja
Publication of FR2675921A1 publication Critical patent/FR2675921A1/fr
Application granted granted Critical
Publication of FR2675921B1 publication Critical patent/FR2675921B1/fr
Priority to US08/151,683 priority patent/US5436856A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/273Tester hardware, i.e. output processing circuits
    • G06F11/2733Test interface between tester and unit under test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
FR9105430A 1991-04-24 1991-04-24 Procede et dispositif de test d'une carte d'un systeme informatique. Expired - Fee Related FR2675921B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR9105430A FR2675921B1 (fr) 1991-04-24 1991-04-24 Procede et dispositif de test d'une carte d'un systeme informatique.
EP92420135A EP0515290A1 (fr) 1991-04-24 1992-04-22 Procédé et dispositif pour tester une carte de système d'ordinateur
JP4106567A JPH06180657A (ja) 1991-04-24 1992-04-24 コンピュータシステムボードの試験方法及び装置
US08/151,683 US5436856A (en) 1991-04-24 1993-11-15 Self testing computer system with circuits including test registers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9105430A FR2675921B1 (fr) 1991-04-24 1991-04-24 Procede et dispositif de test d'une carte d'un systeme informatique.

Publications (2)

Publication Number Publication Date
FR2675921A1 FR2675921A1 (fr) 1992-10-30
FR2675921B1 true FR2675921B1 (fr) 1993-08-20

Family

ID=9412478

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9105430A Expired - Fee Related FR2675921B1 (fr) 1991-04-24 1991-04-24 Procede et dispositif de test d'une carte d'un systeme informatique.

Country Status (4)

Country Link
US (1) US5436856A (fr)
EP (1) EP0515290A1 (fr)
JP (1) JPH06180657A (fr)
FR (1) FR2675921B1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872669A (en) * 1988-03-01 1999-02-16 Seagate Technology, Inc. Disk drive apparatus with power conservation capability
US5623674A (en) * 1995-05-08 1997-04-22 Microsoft Corporation Method for determining steerable interrupt request lines used by PCMCIA controllers
US5936976A (en) * 1997-07-25 1999-08-10 Vlsi Technology, Inc. Selecting a test data input bus to supply test data to logical blocks within an integrated circuit
GB2381890B (en) * 2001-11-12 2003-10-29 Mentor Graphics Testing the interrupt sources of a microprocessor
GB2381891B (en) * 2001-11-12 2003-10-29 Mentor Graphics Testing the interrupt priority levels in a microprocessor
US7155370B2 (en) * 2003-03-20 2006-12-26 Intel Corporation Reusable, built-in self-test methodology for computer systems
US20050080581A1 (en) * 2003-09-22 2005-04-14 David Zimmerman Built-in self test for memory interconnect testing
DE102007049354A1 (de) * 2007-10-15 2009-04-16 Robert Bosch Gmbh Verfahren zum Testen eines Adressbusses in einem logischen Baustein
JP6367173B2 (ja) * 2015-11-17 2018-08-01 株式会社京三製作所 制御出力回路、演算装置、電子端末装置及び接点入力回路
US10318903B2 (en) 2016-05-06 2019-06-11 General Electric Company Constrained cash computing system to optimally schedule aircraft repair capacity with closed loop dynamic physical state and asset utilization attainment control

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2290708A1 (fr) * 1974-11-06 1976-06-04 Honeywell Bull Soc Ind Dispositif de test d'adaptateurs logiques d'appareils peripheriques connectes a une unite de traitement de l'information
US4012625A (en) * 1975-09-05 1977-03-15 Honeywell Information Systems, Inc. Non-logic printed wiring board test system
US4471484A (en) * 1979-10-18 1984-09-11 Sperry Corporation Self verifying logic system
JPS59105109A (ja) * 1982-12-09 1984-06-18 Mitsubishi Electric Corp プログラマブルコントロ−ラの入出力ユニツト
JPS59185097A (ja) * 1983-04-04 1984-10-20 Oki Electric Ind Co Ltd 自己診断機能付メモリ装置
US4563736A (en) * 1983-06-29 1986-01-07 Honeywell Information Systems Inc. Memory architecture for facilitating optimum replaceable unit (ORU) detection and diagnosis
JPS60144851A (ja) * 1983-12-30 1985-07-31 Fujitsu Ltd チヤネル制御装置
US4625313A (en) * 1984-07-06 1986-11-25 Tektronix, Inc. Method and apparatus for testing electronic equipment
GB8432458D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
ATE53261T1 (de) * 1985-03-26 1990-06-15 Siemens Ag Verfahren zum betreiben eines halbleiterspeichers mit integrierter paralleltestmoeglichkeit und auswerteschaltung zur durchfuehrung des verfahrens.
US4961067A (en) * 1986-07-28 1990-10-02 Motorola, Inc. Pattern driven interrupt in a digital data processor
US4926363A (en) * 1988-09-30 1990-05-15 Advanced Micro Devices, Inc. Modular test structure for single chip digital exchange controller
US5157782A (en) * 1990-01-31 1992-10-20 Hewlett-Packard Company System and method for testing computer hardware and software

Also Published As

Publication number Publication date
FR2675921A1 (fr) 1992-10-30
JPH06180657A (ja) 1994-06-28
EP0515290A1 (fr) 1992-11-25
US5436856A (en) 1995-07-25

Similar Documents

Publication Publication Date Title
FR2675602B1 (fr) Procede et dispositif de protection d'un systeme informatique.
FR2685785B1 (fr) Dispositif et procede d'identification d'une personne ou d'un objet.
FR2649820B1 (fr) Procede et dispositif pour afficher une image
FR2714747B1 (fr) Dispositif de commande de l'accès partagé à une mémoire de données dans un système multiprocesseur.
FR2661585B1 (fr) Procede et dispositif d'embrouillage-desembrouillage de donnees d'images numeriques.
FR2697362B1 (fr) Appareil de traitement de données et dispositif d'introduction de carte associé.
FR2639739B1 (fr) Procede et dispositif de compression de donnees d'image utilisant un reseau de neurones
FR2710757B1 (fr) Méthode et dispositif d'acquisition de signaux sismiques.
FR2657173B1 (fr) Procede et dispositif de separation de signaux en temps reel.
FR2628539B1 (fr) Sonde, dispositif d'imagerie utilisant une telle sonde et procede mettant en oeuvre un tel dispositif
FR2702857B1 (fr) Procédé et dispositif d'autorisation d'accès à un appareil comportant un système informatique d'exploitation.
FR2499281B1 (fr) Procede et dispositif d'evaluation d'un systeme d'enregistrement
FR2675921B1 (fr) Procede et dispositif de test d'une carte d'un systeme informatique.
FR2665256B1 (fr) Dispositif et procede pour mesurer un angle.
FR2455319B1 (fr) Procede et dispositif d'enregistrement de donnees sur une carte magnetique
FR2646540B1 (fr) Dispositif perfectionne d'effacement rapide de l'afficheur de sortie d'un systeme informatique
FR2726416B1 (fr) Dispositif de communication de donnees et procede d'utilisation d'une carte intelligente
FR2615638B1 (fr) Dispositif et procede d'habilitation informatique ou telematique
FR2642244B1 (fr) Procede et dispositif d'acces hierarchise a un reseau de transmission d'informations
FR2743230B1 (fr) Systeme de transmission de donnees comprenant un transmetteur de donnees et un dispositif de detection d'informations portatif destine a recevoir ces donnees
FR2555788B1 (fr) Procede de commande d'un dispositif de visualisation a acces matriciel et dispositif de visualisation utilisant ce procede
FR2675603B1 (fr) Procede et dispositif de test d'un circuit d'un systeme informatique.
FR2675922B1 (fr) Procede et dispositif de test d'un ensemble multi-cartes d'un systeme informatique.
FR2513778B1 (fr) Dispositif et procede d'informatique
FR2652647B1 (fr) Procede de test d'etancheite d'un boitier et dispositif de test d'etancheite.

Legal Events

Date Code Title Description
ST Notification of lapse