CS209399B1 - Wiring to detect the wrong address - Google Patents

Abstract

The invention relates to the field of automatic computers — fault detection. The circuit solves the detection of a fault in a small computer system, which is manifested by addressing a non-existent memory cell. The basis is the fact that there is no software available that would be able to handle this condition. The solution is achieved by a hardware detector located in the processor of the small computer, which informs the operator via a panel signaling about the fault that has occurred. The possibility of use is only in the specified field. The given invention is characterized by a single point of the subject matter.

Description

(54) Connection for incorrect address detection

The invention relates to the field of automatic computers — fault detection. The circuit solves the problem of detecting a fault in a small computer system, which is manifested by addressing a non-existent memory cell. The basis for this is the fact that there is no software available that would be able to handle this condition. The solution is achieved by a hardware detector located in the processor of the small computer, which informs the operator about the fault via a panel signaling.

It can only be used in the specified field.

The invention is characterized by a single subject matter.

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The subject of the invention is a circuit for detecting an incorrect address in a small computer system.

When operating a system controlled by a small computer based on a program and data stored in the main memory, a situation may arise due to a fault where the processor addresses a non-existent memory cell. When addressing, the processor refers to both the programmatically accessible registers of additional devices and the main memory registers. In practice, the problem of detecting and signaling the above situation is solved by software means. For example, in a device that operates under an operating system, this case leads to the processor switching to a trap subroutine and to a message about the type of fault on the operator display. In a small computer system that functions as a programmable controller of an additional device, and where the appropriate programs for the above signaling method are not available, it is necessary to choose another solution that corresponds to the complexity of the processor and the given application.

’ This solution provides a circuit according to the invention. Signaling to the operator that the processor of a small computer addresses a non-existent address is solved by a circuit for detecting an incorrect address according to the invention, the essence of which is that the first input of the processor is connected to the first input of the integrator and the second input of the processor is connected to the second input of the integrator, the output of which is connected to the clock input of the signaling flip-flop, which is connected by a data input to the third input of the processor and by an output is connected to the output of the processor, which is connected to the error wire of the bus, which is further connected to the input of the signaling block.

The advantage of this connection is the possibility of signaling a fault in the additional device, which will be reflected by a query for a non-existent address or a fault in the circuits of the input synchronization signal generation itself as a response to the output synchronization signal. In this case, it is not necessary for the control computer to run under an operating system.

The attached drawing shows the circuit according to the invention, where the interconnection of the individual blocks is shown together with their designation.

The address bus 1 is connected to the input 50 of the decoder 5, the output 51 of which is connected to the first input 60 of the input synchronization signal generator 6. Its output 62 is connected to the input synchronization line 3, while its second input 61 is connected to the output synchronization line 2. The first input 70 of the processor 7 is further connected to this line, and the input synchronization line 3 is connected to

Claims (4)

SUBJECT Wrong address detection circuitry with an address decoder, a bus and a processor, characterized in that the first input (70) of the processor (7) is coupled to the first input (80) of the integrator (8) and the second input (71) of the processor (7) is connected to the second input (81) of the integrator (8), the output of which (82) is connected to the clock input (90) of the signaling flip-flop (9) which is the data input (92) of the second input 71 of the processor 7. the second input 81 of the integrator 8 is connected to the second input 71 and the output 82 is connected to the clock input 90 of the flip-flop 9 of the signaling circuit. The data input 92 of this circuit is connected to the third input 73 of the processor 7, which is controlled by the signal 11. The output 91 of the signaling flip-flop 9 is connected to the output 72 of the processor 7, which is further connected to the bus fault 4 to which block 10 of the signaling. The function is as follows: Decoder 5 reads the instantaneous address values on address bus 1. When the address matches the encoded, an active signal appears at the output 51 of the decoder 5, which is further propagated to the first input 60 of the input sync signal generator 6. Upon arrival of the active level of the output sync signal at the second input 61, a signal is output from the output 62 to the input sync line 3. Meanwhile, the presence of the signal at the first input 80 and the absence of the signal at the second input 81 of the integrator 8 causes the capacitor to charge, thereby increasing the level at output 82. The capacitor capacitance is dimensioned such that if the input synchronization signal is sent by the addressed cell from output 62 at a defined time, the output 82 of the integrator 8 does not reach the logic level. If the decoder 5, in the case of a non-existent address, no active signal is sent to the first input 60, the input synchronization signal generator 6 is blocked, and the output 82 of the integrator 8 ramps up to the logic one level. A similar situation occurs when a fault occurs in the decoder or in the generator itself 6 of the input sync signal. Positive edge at clock input 90 of flip-flop 9, the signaling causes the signal level to be written to the data input 92. If the computer's manual mode is selected, the signal 11 is set at the third input 73 of the processor 7 to a level which does not cause a change of the flip-flop 9 signaling state. In normal operation, the state of this circuit changes, which is further transmitted via the output 72 of the processor 7 to the bus fault wire 4 and from there through the input 100 to the signaling block 10 as information to the operator about the cause of the failure. The possibility of using this connection is for a small computer that works as a controller in an attachment and uses the type of connection system described. ...... · ... ..... OF THE INVENTION connected to the third input (73) of the processor (7) and the output (91) is connected to the output (72) of the processor (7), which is connected to a bus fault wire (4) which is further coupled to the input (100) (10) 'signaling.