CN2906922Y - 薄型塑料封装结构 - Google Patents

薄型塑料封装结构 Download PDF

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CN2906922Y
CN2906922Y CN 200520141870 CN200520141870U CN2906922Y CN 2906922 Y CN2906922 Y CN 2906922Y CN 200520141870 CN200520141870 CN 200520141870 CN 200520141870 U CN200520141870 U CN 200520141870U CN 2906922 Y CN2906922 Y CN 2906922Y
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lead frame
plastic package
package structure
utility
model
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吴万华
林永梃
庞思全
彭作明
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SIGURD CO Ltd
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SIGURD CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型是揭露一种薄型塑料封装结构，其是将芯片安装在一导线架上，再以封装胶体包覆之，其中位于导线架上方的上层胶体与导线架下方的下层胶体厚度可依实际操作需求变更，但仍维持本实用新型整体厚度不超过0.70毫米，此外，更可适用于不同的I/O脚数，故本实用新型是提供一种具有小体积且生产成本低、制造过程简单的薄型塑料封装结构。

Description

薄型塑料封装结构
技术领域
本实用新型是有关一种塑料封装改良结构，特别是关于一种可缩小体积的薄型塑料封装结构。
背景技术
随着电路板上组件数目的飞快增加，封装结构的作用也从加固与支撑提升到影响器械性能的主要部分，已知的封装技术主要分成塑料封装与陶瓷封装，其中塑料封装因具备重量轻、尺寸小、成本低、应用广泛的优点，在产业界被大量使用。
如图1所示，已知的塑料封装结构是采用金属导线架10作为封装基板，将一芯片12安装其上，再焊上引线16连接芯片12的焊垫与导线架10的引脚14，使其成为一电性导通，再以上层胶体18、下层胶体20包覆芯片12及引线16，以保护精细的电路结构，但既有的封装型态中上层胶体与下层胶体的厚度分别为0.30毫米与0.65毫米，含导线架的总厚度达到1.1毫米，实不符合现今产品要求轻薄短小的设计趋势。
故基于上述已知技术的缺点，本实用新型即在不影响电路组件功能的前提下，针对塑料封装结构的尺寸作进一步的改良。
实用新型内容
本实用新型的主要目的是在提供一种塑料封装结构的改良，使封装胶体整体厚度降低。
本实用新型的另一目的是在提供一种可运用现有封装厂线上成熟制程与设备的薄型塑料封装结构，同时使成本降低并可供大量生产。
为达到上述目的，本实用新型一种薄型塑料封装结构，其特征在于，包括：
一导线架，其周围是有数引脚以供电连结至外部电路；
至少一芯片，是安装于该导线架上且与该引脚形成电性连接；以及
一封装胶体，包覆该芯片、该导线架的一部份以露出该引脚，且该封装胶体总厚度小于0.70毫米。
其中该封装胶体包含一覆盖于该导线架上方的上层胶体，及一包覆该导线架下方的下层胶体。
其中，该导线架是金属材质。
其中，该芯片是以数引线连结至该引脚。
其中，该引线是选自金线及铝线其中的一种。
其中，该封装胶体是由热固性材质所构成。
本实用新型的有益效果是：使封装胶体整体厚度降低，同时使成本降低并可供大量生产。
附图说明
底下由具体实施例配合附图详加说明，当更容易了解本实用新型的目的、技术内容、特点及其所达成的功效，其中：
图1为已知塑料封装的结构示意图。
图2为本实用新型的结构示意图。
具体实施方式
塑料封装结构的应用范围甚为广泛，其是利用导线架的引脚作为对外的接点，而芯片则与引脚形成电性连接，以便透过引脚与外界沟通，当然为保护各组件最外层是会再包覆一封装胶体，而为了使封装结构符合轻薄短小的趋势，本实用新型即再提出一种薄型塑料封装结构，并详细说明如下。
如图2所示，一薄型塑料封装结构是包含一导线架30，用来承载具有设计电路的芯片32，并利用接合技术将芯片32固定在导线架30上方，其中该导线架30是为金属材质并有数引脚34在其周围作为封装结构与外部连结的管道，再将数引线36，通常是选自金线或铝线其中的一种，连接至芯片32的接点与引脚34，以供芯片电路作电连接至外部其它装置，之后再以封装胶体38覆盖整个芯片32、引线36以及导线架30的一部份以露出引脚34，其功用在于提供保护作用，避免芯片受到如碰撞、灰尘、或水气等的伤害，如图所示，该封装胶体38可分为一覆盖于导线架上方的上层胶体40，以及一包覆导线架30下方的下层胶体42，为达到缩小体积尺寸的目的，该上层胶体40与下层胶体42的厚度依实际操作需要变更，但仍使封装胶体38的总厚度缩减至0.70毫米以内者为限。其中封装胶体38是以热固性材质所构成者，并以压模成型或液态封装方式成型。
是以本实用新型所揭示的薄型塑料封装结构具有体积轻薄短小的特性，并可同时适用于不同的I/O脚数，故可沿用原有封装生产流程与设备，不需另外增加成本支出即可供大量生产。
以上所述实施例仅是为说明本实用新型的技术思想及特点，其目的在使熟习此项技术的人士能够了解本实用新型的内容并据以实施，当不能以的限定本实用新型的专利范围，即凡是依本实用新型所揭示的精神所作的均等变化或修饰，仍应涵盖在本实用新型的专利范围内。

Claims (6)

1.一种薄型塑料封装结构，其特征在于，包括：
一导线架，其周围是有数引脚以供电连结至外部电路；
至少一芯片，是安装于该导线架上且与该引脚形成电性连接；以及
一封装胶体，包覆该芯片、该导线架的一部份以露出该引脚，且该封装胶体总厚度小于0.70毫米。
2.如权利要求1所述的薄型塑料封装结构，其特征在于，其中该封装胶体包含一覆盖于该导线架上方的上层胶体，及一包覆该导线架下方的下层胶体。
3.如权利要求1所述的薄型塑料封装结构，其特征在于，其中，该导线架是金属材质。
4.如权利要求1所述的薄型塑料封装结构，其特征在于，其中，该芯片是以数引线连结至该引脚。
5.如权利要求4所述的薄型塑料封装结构，其特征在于，其中，该引线是选自金线及铝线其中的一种。
6.如权利要求1所述的薄型塑料封装结构，其特征在于，其中，该封装胶体是由热固性材质所构成。
CN 200520141870 2005-11-24 2005-11-24 薄型塑料封装结构 Expired - Fee Related CN2906922Y (zh)

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Termination date: 20111124