CN220510029U

CN220510029U - Double-base island series internal insulation packaging structure of high-power semiconductor

Info

Publication number: CN220510029U
Application number: CN202321393596.7U
Authority: CN
Inventors: 孙俊宝
Original assignee: Hangzhou Junai Technology Co ltd
Current assignee: Hangzhou Junai Technology Co ltd
Priority date: 2023-06-02
Filing date: 2023-06-02
Publication date: 2024-02-20
Anticipated expiration: 2033-06-02

Abstract

The utility model discloses a double-base island series internal insulation packaging structure of a high-power semiconductor, which comprises a plastic package body, a base island carrier sheet, an insulating ceramic sheet and a radiating fin, wherein the insulating ceramic sheet is welded on the radiating fin, the base island carrier sheet is welded on the insulating ceramic sheet, the base island carrier sheet, the insulating ceramic sheet and the radiating fin are packaged together by the plastic package body, the base island carrier sheet comprises double base islands, aluminum wires and a plurality of pins, and the double base islands are electrically connected with the plurality of pins through the aluminum wires. The utility model has wider application range, and the heat of the chip can be fully led out due to the design of the internal ceramic, the area of the radiating fin and the area of the copper foil of the PCB can be reduced, the cost is reduced, and the radiating effect is good.

Description

Double-base island series internal insulation packaging structure of high-power semiconductor

Technical Field

The utility model relates to a double-base island series internal insulation packaging structure of a high-power semiconductor.

Background

The current motor driving application circuit is that more than 6 field effect transistors are used as single machine, every 2 field effect transistors are connected in series to form a group, and the group is divided into 3 groups and more, so that the PCB area occupied by the single machine with more consumption is large, and some products with requirements on the PCB size can not be realized. The biggest problem of power devices is heat dissipation, most of the prior art adopts a patch field effect tube on a PCB, the PCB enlarges the area of copper foil to lead the field effect tube to conduct heat, and a heat dissipation fin is additionally arranged on the front plastic package material of the field effect tube to increase heat dissipation. The defects are 1, the heat conduction of the PCB is very limited, and the heat of the device cannot be sufficiently conducted out; 2. the heat dissipation plate on the front plastic package material is limited due to the heat conductivity coefficient of the plastic package material, and the heat of the chip cannot be sufficiently conducted out. If the generated heat of the power device cannot be timely led out, the power device can fail and crash. In order to solve the problem, application engineers are required to reduce the internal resistance value of the field effect transistor, the chip size is increased when the internal resistance is reduced, the packaging size is increased, and the cost is greatly increased. If the application line size is small, some limitations in size have not solved the problem.

Disclosure of Invention

The utility model aims to overcome the defects in the existing products and provides a double-base island series internal insulation packaging structure of a high-power semiconductor.

In order to achieve the above purpose, the utility model is realized by the following technical scheme:

the utility model provides a high-power semiconductor's double-base island series connection internal insulation packaging structure, includes plastic envelope body, base island slide glass, insulating ceramic piece, fin, welding above the fin insulating ceramic piece, welding above the insulating ceramic piece the base island slide glass, the plastic envelope body encapsulates base island slide glass, insulating ceramic piece, fin together, the base island slide glass includes double-base island, aluminium wire, a plurality of pin, double-base island passes through aluminium wire and a plurality of pin electric connection.

Preferably, the plurality of pins is five pins.

Preferably, the double-base island comprises a first field effect transistor chip M1 and a second field effect transistor chip M2, wherein a source electrode S1 of the first field effect transistor chip M1 is connected with a drain electrode D2 of the second field effect transistor chip M2.

Preferably, the five pins are a first pin, a second pin, a third pin, a fourth pin and a fifth pin, the drain electrode D1 of the first field effect transistor chip M1 is connected with the first pin, the gate electrode G1 of the first field effect transistor chip M1 is connected with the second pin through an aluminum wire, the source electrode S1 of the first field effect transistor chip M1 is connected with the third pin, the gate electrode G2 of the second field effect transistor chip M2 is connected with the fourth pin through an aluminum wire, the source electrode S2 of the second field effect transistor chip M2 is connected with the fifth pin, and the drain electrode D2 of the first field effect transistor chip M2 is connected with the third pin.

Preferably, the plastic package body, the insulating ceramic sheet and the radiating fin are all positioned at the top end of the island carrier sheet.

Preferably, the heat sink is provided with heat radiation holes.

Preferably, the five pins are uniformly arranged.

The beneficial effects of the utility model are as follows:

the utility model adopts 2 field effect transistors to be packaged in series, thus the original application circuit driven by the motor adopts the single machine consumption of 6 to be reduced to 3 single machine consumption, the original consumption is divided by 2, the size of the PCB is greatly reduced, and the original products which cannot be realized due to the large PCB are realized by the utility model, so the utility model has wider application range;

the utility model is designed by internal ceramics, the heat of the chip can be fully led out, the area of the radiating fin and the area of the copper foil of the PCB can be reduced, the cost is reduced, and the radiating effect is good.

Drawings

FIG. 1 is a schematic diagram of an exploded construction of the present utility model;

FIG. 2 is a schematic perspective view of the present utility model;

fig. 3 is a schematic diagram of a semiconductor package pin.

Detailed Description

The technical scheme of the utility model is further described below with reference to the attached drawings in the specification:

as shown in fig. 1 to 3, a double-base island series internal insulation packaging structure of a high-power semiconductor comprises a plastic package body 1, a base island carrier 2, an insulation ceramic sheet 3 and a heat dissipation sheet 4, wherein the insulation ceramic sheet 3 is welded on the heat dissipation sheet 4, the base island carrier 2 is welded on the insulation ceramic sheet 3, the base island carrier 2, the insulation ceramic sheet 3 and the heat dissipation sheet 4 are packaged together by the plastic package body 1, the base island carrier 2 comprises a double-base island 21, an aluminum wire 22 and five pins, and the double-base island 21 is electrically connected with the five pins through the aluminum wire 22.

As shown in fig. 3, the double-base island 21 includes a first fet chip M1 and a second fet chip M2, where a source S1 of the first fet chip M1 is connected to a drain D2 of the second fet chip M2. The five pins are a first pin 24, a second pin 25, a third pin 26, a fourth pin 27 and a fifth pin 28, the drain electrode D1 of the first field effect transistor chip M1 is connected with the first pin 24, the grid electrode G1 of the first field effect transistor chip M1 is connected with the second pin 25 through an aluminum wire 22, the source electrode S1 of the first field effect transistor chip M1 is connected with the third pin 26, the grid electrode G2 of the second field effect transistor chip M2 is connected with the fourth pin 27 through the aluminum wire 22, the source electrode S2 of the second field effect transistor chip M2 is connected with the fifth pin 28, and the drain electrode D2 of the first field effect transistor chip M2 is connected with the third pin 26.

As shown in fig. 1 and 2, the plastic package 1, the insulating ceramic sheet 3 and the heat sink 4 are all positioned at the top end of the island carrier 2, and the heat sink 4 is provided with heat dissipation holes 41. The five pins are uniformly arranged.

As shown in fig. 1 to 3, a dual-island series internal insulation packaging structure of a high-power semiconductor comprises a plastic package body 1, a island carrier 2, an insulation ceramic sheet 3 and a heat sink 4, wherein the plastic package body 1 is arranged on the outer side of the island carrier 2, the insulation ceramic sheet 3 is arranged on the inner side of the island carrier 2, the heat sink 4 is arranged on the outer side of the insulation ceramic sheet 3, the heat sink 4 is fixedly connected with the plastic package body 1, the island carrier 2 comprises a dual-island 21, an aluminum wire 22 and five pins, and the dual-island 21 is electrically connected with the five pins through the aluminum wire 22.

Working principle:

the insulating ceramic plate 3 is welded on the radiating fin 4, the slide base 2 is welded on the insulating ceramic plate 3, the base slide 2, the insulating ceramic plate 3 and the radiating fin 4 are encapsulated together by the plastic package body 1, and the source electrode S1 of the first field effect tube M1 is connected with the drain electrode D2 of the second field effect tube M2. The first field effect tube M1 and the second field effect tube M2 are in series packaging form, and any change of the external dimensions such as TO-263-5L, TO-247-5L, TO-3P-5L and the like is in the protection of the utility model.

The utility model adopts 2 field effect transistors to be packaged in series, thus the original application circuit driven by the motor adopts the single machine consumption of 6 to be reduced to 3 single machine consumption, the original consumption is divided by 2, the size of the PCB is greatly reduced, and the original products which cannot be realized due to the large PCB are realized by the utility model, and the application scope of the utility model is wider;

It should be noted that the above list is only one specific embodiment of the present utility model. It is obvious that the present utility model is not limited to the above embodiments, but many variations are possible, such as the number of pins, and in any case, all variations directly derived or suggested by the person skilled in the art from the disclosure of the present utility model should be considered as the protection scope of the present utility model.

Claims

1. The utility model provides a high-power semiconductor's double-base island series connection internal insulation packaging structure, its characterized in that includes plastic envelope body (1), base island slide glass (2), insulating ceramic piece (3), fin (4), welding above fin (4) insulating ceramic piece (3), welding above insulating ceramic piece (3) base island slide glass (2), plastic envelope body (1) encapsulates base island slide glass (2), insulating ceramic piece (3), fin (4) together, base island slide glass (2) include double-base island (21), aluminum wire (22), a plurality of pin, double-base island (21) are through aluminum wire (22) and a plurality of pin electric connection.

2. The dual island series internal insulation package structure of a high power semiconductor of claim 1, wherein said plurality of pins is five pins.

3. The double-base island series internal insulation packaging structure of the high-power semiconductor according to claim 2, wherein the double-base island (21) comprises a first field effect transistor chip M1 and a second field effect transistor chip M2, and a source electrode S1 of the first field effect transistor chip M1 is connected with a drain electrode D2 of the second field effect transistor chip M2.

4. The dual-island series internal insulation package structure of a high-power semiconductor according to claim 3, wherein the five pins are a first pin (24), a second pin (25), a third pin (26), a fourth pin (27) and a fifth pin (28), the drain D1 of the first fet chip M1 is connected to the first pin (24), the gate G1 of the first fet chip M1 is connected to the second pin (25) through an aluminum wire (22), the source S1 of the first fet chip M1 is connected to the third pin (26), the gate G2 of the second fet chip M2 is connected to the fourth pin (27) through an aluminum wire (22), the source S2 of the second fet chip M2 is connected to the fifth pin (28), and the drain D2 of the first fet chip M2 is connected to the third pin (26).

5. The double-base island series internal insulation packaging structure of the high-power semiconductor according to claim 1 is characterized in that the plastic package body (1), the insulating ceramic sheet (3) and the radiating fin (4) are all positioned at the top end of the base island carrier sheet (2).

6. The double-base island series internal insulation packaging structure of the high-power semiconductor according to claim 5, wherein the heat sink (4) is provided with a heat dissipation hole (41).

7. The dual island series internal insulation package structure of a high power semiconductor of claim 2, wherein said five pins are uniformly arranged.