CN219513109U

CN219513109U - Medium-high voltage shielding grid power MOSFET layout

Info

Publication number: CN219513109U
Application number: CN202320227265.XU
Authority: CN
Inventors: 薛华瑞; 董建新; 布凡; 钟添宾
Original assignee: Will Semiconductor Ltd
Current assignee: Will Semiconductor Ltd
Priority date: 2023-02-15
Filing date: 2023-02-15
Publication date: 2023-08-11
Anticipated expiration: 2033-02-15

Abstract

The embodiment of the utility model provides a middle-high voltage shielding grid power MOSFET layout, and the grid is led out through a grid polysilicon leading-out area through every other grid polysilicon area.

Description

Medium-high voltage shielding grid power MOSFET layout

Technical Field

The embodiment of the utility model relates to the field of MOSFET layout design, in particular to a middle-high voltage shielding grid power MOSFET layout.

Background

In MOSFET devices, there are two important parameters: on-state resistance Rdson; the other is the gate oxide charge Qg, and the lower these two values are, the better. Mainly they determine the conduction loss and the switching loss of the device, respectively. However, in many cases, the reduction of Qg and the reduction of Rdson are contradictory, so we have to use the figure of merit fom=rdson×qg as an indicator for measuring the performance of the device. Trench gate MOSFETs have a lower on-state resistance than conventional surface gate structures, but an increase in channel area results in an increase in gate charge, manifesting as an increase in parasitic capacitance of the gate, resulting in severe switching losses. As shown in the layout of fig. 1, the shielded gate power MOSFET layout is divided into a termination region 11 and a cell region 12, and in a specific design, it is necessary to connect the source polysilicon out through a source lead-out region 15, a gate lead-out region 16 (each gate polysilicon needs to have a contact hole etched to lead out the gate), and source lead-out regions 13 and 14, respectively, and isolate the source polysilicon electrode from the gate.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present utility model is to provide a middle-high voltage shielded gate power MOSFET layout to reduce gate capacitance and gate charge and reduce switching losses.

The embodiment of the utility model provides a middle-high voltage shielding grid power MOSFET layout, which comprises the following steps: the terminal area and the cell area are adjacently arranged;

the cell area comprises a first area, a second area and a third area, and the first area and the third area are distributed on two sides of the second area;

the first region comprises source electrode lead-out areas and source electrode polycrystalline silicon lead-out areas which are arranged at intervals, the second region comprises grid electrode polycrystalline silicon lead-out areas, every other grid electrode polycrystalline silicon area is used for leading out grid electrodes through one grid electrode polycrystalline silicon lead-out area, and the source electrode polycrystalline silicon areas are correspondingly provided with grid electrode polycrystalline silicon areas in the same groove;

the third region comprises a source electrode leading-out region and a grid electrode polycrystalline silicon leading-out region, the source electrode leading-out regions in the third region and the first region are correspondingly arranged, the source electrode polycrystalline silicon regions in the same groove are correspondingly arranged, the source electrode polycrystalline silicon leading-out region is not arranged in the groove provided with the grid electrode polycrystalline silicon leading-out region in the third region, and the source electrode leading-out region, the source electrode region and the grid electrode polycrystalline silicon not provided with the grid electrode polycrystalline silicon leading-out region are led out through the source electrode leading-out region.

In a preferred embodiment of the present utility model, the first region, the second region and the third region include a dielectric layer disposed on a surface of the semiconductor substrate and a conductive layer disposed on a surface of the dielectric layer.

In a preferred embodiment of the present utility model, the conductive layers disposed in the first region, the second region and the third region are spaced apart.

In a preferred embodiment of the present utility model, a source extraction region is provided in the second region of the termination region.

Compared with the prior art, the embodiment of the utility model provides a high-voltage shielding grid power MOSFET layout, in the embodiment of the utility model, instead of leading out the grid through the contact hole of each grid polysilicon, every other grid polysilicon area leads out the grid through a grid polysilicon leading-out area, and the current flow direction of the channel can be changed. The layout design of the utility model can reduce the gate capacitance and gate charge by 50%, effectively reduce the switching loss, but the channel resistance of medium and high voltage is less than 10%, the on-resistance is increased by about 13%, and finally, the quality factor can be effectively reduced, and the device performance is optimized.

Drawings

Fig. 1 is a schematic diagram of a middle-high voltage shielded gate power MOSFET layout provided in the prior art;

fig. 2 is a schematic diagram of a middle-high voltage shielded gate power MOSFET layout according to an embodiment of the present utility model;

FIG. 3 is a schematic cross-sectional view of a first region according to an embodiment of the present utility model;

FIG. 4 is a schematic cross-sectional view of a second region according to an embodiment of the present utility model;

fig. 5 is a schematic cross-sectional view of a third area according to an embodiment of the present utility model.

Detailed Description

In order to make the technical solution of the present utility model better understood by those skilled in the art, the technical solution of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

As shown in fig. 1-5, an embodiment of the present utility model provides a middle-high voltage shielded gate power MOSFET layout, including: a terminal region 21 and a cell region 22, the terminal region 21 being disposed adjacent to the cell region 22;

the cellular region comprises a first region 22-1, a second region 22-2 and a third region 22-3, wherein the first region 22-1 and the third region 22-3 are distributed on two sides of the second region 22-2;

the first region 22-1 includes a source extraction region 24 and a source polysilicon extraction region 25 that are arranged at intervals, the second region 22-2 includes a gate polysilicon extraction region 27, every other gate polysilicon region extracts a gate through one gate polysilicon extraction region 27, and the source polysilicon region 25 is correspondingly provided with a gate polysilicon region in the same trench;

the third region 22-3 includes a source extraction region 23 and a gate polysilicon extraction region 26, the source extraction region 23 in the third region 22-3 and the first region 22-1 are disposed corresponding to each other, the source polysilicon regions 26 in the same trench are disposed corresponding to each other, the source polysilicon extraction region 23 is not disposed in the trench in which the gate polysilicon extraction region 27 is disposed in the third region 22-3.

As an example, the semiconductor substrate may be a silicon substrate, a GaN substrate, or the like, and it is to be noted that, in general, the layout design of the present embodiment may be applied to MOSFET designs based on various material substrates.

In the embodiment of the utility model, not every grid polysilicon is led out of the grid through the contact hole, and every other grid polysilicon area is led out of the grid through a grid polysilicon leading-out area, so that the current flow direction of the channel can be changed. The layout design of the utility model can reduce the gate capacitance and gate charge by 50%, effectively reduce the switching loss, but the channel resistance of medium and high voltage is less than 10%, the on-resistance is increased by about 13%, and finally, the quality factor can be effectively reduced, and the device performance is optimized.

In a preferred embodiment of the present utility model, the first region 22-1, the second region 22-2 and the third region 22-3 include a dielectric layer disposed on the surface of the semiconductor substrate and a conductive layer disposed on the surface of the dielectric layer, where the dielectric layer may be made of silicon dioxide, silicon nitride, or other materials, and the conductive layer may be made of metal materials or polysilicon materials, and it should be noted that the above-listed concentrated materials are only a few preferred embodiments of the present utility model, and are not limited thereto in practical production.

In a preferred embodiment of the present utility model, the conductive layers disposed in the first region 22-1, the second region 22-2 and the third region 22-3 are spaced apart. By isolating the conductive layer, a short circuit between the gate and the source is prevented.

In a preferred embodiment of the present utility model, the second region 22-2 of the termination region is not provided with a gate polysilicon lead-out region, and the third region 22-3 of the termination region is provided with a source lead-out region, so that the gate capacitance and gate charge can be reduced by about 50%, the switching loss can be effectively reduced, the channel resistance of the medium-high voltage is less than 10%, the on-resistance is increased by about 13%, and the quality factor can be effectively optimized.

As an example, the layout design of the embodiment of the present utility model further includes a trench isolation structure, where the trench isolation structure is located at the periphery of the cell region and is used for isolating the device.

While the utility model has been described in detail in terms of its general description and specific embodiments, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the utility model and are intended to be within the scope of the utility model as claimed.

Claims

1. A medium-high voltage shielded gate power MOSFET layout comprising: the terminal area and the cell area are adjacently arranged;

the first region comprises source electrode lead-out areas and source electrode polycrystalline silicon lead-out areas which are arranged at intervals, the second region comprises grid electrode polycrystalline silicon lead-out areas, every other grid electrode polycrystalline silicon area is used for leading out grid electrodes through one grid electrode polycrystalline silicon lead-out area, and the source electrode polycrystalline silicon lead-out areas in the same groove are correspondingly provided with grid electrode polycrystalline silicon areas;

the third region comprises a source electrode leading-out region and a grid electrode polycrystalline silicon leading-out region, the source electrode leading-out regions in the third region and the first region are correspondingly arranged, the source electrode polycrystalline silicon leading-out regions in the same groove are correspondingly arranged, the source electrode polycrystalline silicon leading-out region is not arranged in the groove provided with the grid electrode polycrystalline silicon leading-out region in the third region, and the source electrode polycrystalline silicon leading-out region and the grid electrode polycrystalline silicon not provided with the grid electrode polycrystalline silicon leading-out region are led out through the source electrode leading-out region.

2. A medium and high voltage shielded gate power MOSFET layout according to claim 1, wherein said first, second and third regions comprise a dielectric layer disposed on a surface of a semiconductor substrate and a conductive layer disposed on a surface of the dielectric layer.

3. A medium and high voltage shielded gate power MOSFET layout according to claim 2 wherein conductive layers disposed in said first, second and third regions are spaced apart.

4. A medium and high voltage shielded gate power MOSFET layout according to claim 1, wherein no gate polysilicon lead-out is provided in the second region of the termination region and a source lead-out is provided in the third region of the termination region.