CN213958962U

CN213958962U - Layout structure of shielded gate power device

Info

Publication number: CN213958962U
Application number: CN202120257022.1U
Authority: CN
Inventors: 蒋平; 徐承福
Original assignee: SMIC Manufacturing Shaoxing Co Ltd
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
Priority date: 2021-01-29
Filing date: 2021-01-29
Publication date: 2021-08-13
Anticipated expiration: 2031-01-29

Abstract

The utility model provides a shielded gate power device's domain structure, including the cell district, the cell district is including crisscross first slot and the second slot that sets up, first slot and second slot play the shielding effect from horizontal and vertical two directions, make on-resistance descend, have strengthened the shielding effect, have improved the high pressure withstand voltage ability of device. Further, the utility model discloses a crisscross first slot that sets up and the design of second slot form closed terminal area overall arrangement in the domain structure of shielding grid power device, have saved terminal area, further improve BV withstand voltage and reduce on-resistance. Additionally, the utility model discloses well grid electrode potential is drawn forth from the gate region of the both sides in cellular region, and the overall arrangement can make active area obtain abundant utilization like this, improves the utilization ratio in active area.

Description

Layout structure of shielded gate power device

Technical Field

The utility model relates to a semiconductor integrated circuit makes the field, in particular to shielding grid power device's territory structure.

Background

At present, with the continuous development of semiconductor integrated circuits, a Shielded Gate (SGT) power device has become a power device with a wide application. The SGT power device serving as a novel device structure in a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with medium and low voltage can reduce the specific on-resistance of the traditional trench MOSFET to one half or even one fifth of the original specific on-resistance. The traditional groove type MOSFET is mainly used for increasing the groove density of a planar device so as to improve the current handling capacity of the device, and the SGT MOSFET is used as an improved groove MOSFET structure which can not only reduce the groove density, but also further reduce the resistance of a drift region.

According to the traditional strip-shaped shielding gate MOSFET structure, two vertical polycrystalline field plates are introduced into a groove, so that two new electric field peak values are introduced into a drift layer of a device, the Breakdown Voltage (BV) of the device is increased, an accumulation layer with higher concentration is formed around a vertical drain field plate of the device, and the on-resistance is reduced. Due to the vertical field plate between the longitudinal grid and the drain field plate of the device, the grid-drain capacitance value influencing the switching speed of the device is partially converted into the grid-source capacitance and the drain-source capacitance of the device, so that the N-type region realizes high breakdown voltage under high doping concentration, low on-resistance and high breakdown voltage are obtained at the same time, and the theoretical limit of the on-resistance of the traditional power MOSFET is broken.

For a shielded gate MOSFET junction, the withstand voltage is mainly born by a thick oxygen column of a gate structure below a deep groove structure, and in order to reduce the on-resistance, a drift layer substrate with high concentration is often adopted, so that the design requirement on the avalanche current capability of the device is high. Therefore, the MOSFET with the shield gate structure needs to have a high voltage withstanding capability. However, the layout design of the existing SGT power device adopts the stripe trench layout design, and the stripe trench design can only provide shielding effect (horizontal or longitudinal) along the trench direction, and has limited shielding effect and low high-voltage resistance and voltage resistance. Therefore, it is necessary to provide a layout design scheme for the SGT power device to continuously optimize the shielding effect, reduce the on-resistance, enhance the shielding effect, and improve the high-voltage withstand voltage capability.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a domain structure of shielding bars power device to strengthen the shielding effect, improved the high pressure withstand voltage ability of device.

The utility model provides a territory structure of shielding bars power device, include: the cell area comprises first grooves and second grooves which are arranged in a staggered mode, gate electrodes and shielding gate electrodes are formed in the first grooves and the second grooves, the gate electrodes are located above the shielding gate electrodes, and the gate electrodes are located on the shielding gate electrodes and are insulated from each other through dielectric layers.

Optionally, the first trench and the second trench are vertically disposed, and widths of the first trench and the second trench are equal.

Optionally, the cellular region is concave.

Optionally, the cell structure further comprises a gate region, wherein the gate region is in an inverted-mountain-shaped shape and surrounds the cell region in a half-surrounding mode.

Optionally, the gate structure further comprises a gate metal layer located on the gate region and connected to the gate electrode.

Optionally, a gate contact hole is formed in the gate metal layer for accessing a gate electrode potential, and the gate contact hole is located on the vertical arm on each of two sides of the inverted "chevron" shape.

Optionally, the semiconductor device further includes an isolation region located at the periphery of the cell region and surrounding the gate region to isolate the cell region from the gate region.

Optionally, the field effect transistor further comprises a well region and a source region, wherein the well region and the source region are formed in the substrate at the side edges of the first trench and the second trench and used for forming a shielded gate field effect transistor in the cell region.

Optionally, the semiconductor device further includes a source metal layer located above the source region and connected to the source region.

Optionally, a source contact hole is formed in the source polycrystalline layer and used for receiving a source potential, and the source contact hole is located in a region below the concave opening in the shape of the Chinese character 'ao'.

To sum up, the utility model provides an among shield grid power device's domain structure, including the cell district, the cell district is including crisscross first slot and the second slot that sets up, first slot and second slot play the shielding effect from horizontal and vertical two directions, make on-resistance descend, have strengthened the shielding effect, have improved the high-pressure withstand voltage ability of device.

Further, the utility model discloses a crisscross first slot that sets up and the design of second slot form closed terminal area overall arrangement in the domain structure of shielding grid power device, have saved terminal area, further improve BV withstand voltage and reduce on-resistance.

Further, the utility model discloses well grid electrode potential is drawn forth from the gate region of the both sides in cellular region, and the overall arrangement can make active area obtain abundant utilization like this, improves the utilization ratio in active area.

Drawings

Fig. 1 is a layout structure of a shielded gate power device provided by the present invention;

FIG. 2 is an enlarged view of the dashed area of FIG. 1;

FIG. 3 is a schematic cross-sectional view along AA' of FIG. 2;

wherein the reference numerals are:

1-a gate metal layer; 2-an isolating layer; 3-a source metal layer; 4-a trench structure; 5-Gate bus; 6-source poly;

10-cellular region; 11-a termination area; 12-a gate region; 13-an isolation region; 14-a source region; 15-well region; 16-a substrate; 17-contact vias;

41-a first trench; 42-a second trench; 51-a gate electrode; 52-shield gate electrode; 53-dielectric layer.

Detailed Description

The layout structure of the shielded gate power device according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the inventive concepts may be embodied in many different forms and are not limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but rather are provided for convenience and clarity in describing the embodiments of the invention.

The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.

Fig. 1 is a layout structure of a shielded gate power device according to this embodiment, fig. 2 is an enlarged view of a dotted line region in fig. 1, and fig. 3 is a schematic cross-sectional view of fig. 2 along the direction AA'. Referring to fig. 1, fig. 2, and fig. 3, the layout structure of the shielded gate power device provided in this embodiment includes: a cell region 10 (which may also be referred to as an active region) and a termination region 11, the termination region 11 being arranged around the cell region 10. A Trench structure (Trench)4 is formed in the cell region 10, the Trench structure 4 includes first trenches 41 and second trenches 42 which are arranged in a staggered manner, gate electrodes 51 and shield gate electrodes 52 are formed in the first trenches 41 and the second trenches 42, the gate electrodes 51 are located above the shield gate electrodes 52, and the gate electrodes 51 are located on the shield gate electrodes 52 and are insulated from each other by dielectric layers 53.

In this embodiment, the first trenches 41 and the second trenches 42 are staggered at a certain angle, so as to improve the conduction efficiency. Preferably, the first trenches 41 and the second trenches 42 are vertically arranged to form a trench structure 4 in a shape of a "well", for example, the first trenches 41 are horizontal trenches, the second trenches 42 are vertical trenches, and the first trenches 41 and the second trenches 42 arranged in a staggered manner divide the cell area 10 into a plurality of square cell structures. The widths of the first trench 41 and the second trench 42 may be the same or different. The first grooves 41 and the second grooves 42 may be arranged alternately to form various patterns, and are not limited to the above implementation. Compared with the existing strip-shaped trench structure, the transverse trench and the longitudinal trench in the square trench structure 4 provided by the embodiment can form shielding effect from two directions, so that the on-resistance is reduced, the shielding effect is enhanced, and the high-voltage withstand voltage capability of the device is improved.

As shown in fig. 1, the cell region 10 is in a concave shape, and the terminal region 11 is disposed around the cell region 10 to form a closed terminal region layout, thereby saving the terminal area, improving BV voltage resistance and reducing on-resistance.

The layout structure of the shielded gate power device provided in this embodiment further includes a gate region 12 and an isolation region 13, where the gate region 12 is in an inverted "hill" shape and partially surrounds the cell region 10. A gate metal layer 1 is formed on the gate region 12, and the gate metal layer 1 is connected to the gate electrode 51 in the trench structure 4. The isolation region 13 is located at the periphery of the cell region 10 and disposed around the gate region 12 to isolate the cell region 10 from the gate region 12. An isolation layer 2 is formed on the isolation region 13, and the isolation layer 2 may be a silicon dioxide layer, for example. As shown in fig. 1, the lateral trench (first trench 41) connects the gate metal layer 1 on the gate region 12 through the spacer 2.

The layout structure of the shielded gate power device further comprises a source region 14 and a well region 15, wherein the source region 14 and the well region 15 are formed in the substrate 16 at the side edges of the first trench 41 and the second trench 42 to form a shielded gate field effect transistor in the cell region 10. A source metal layer 3 is formed above the source region, and the source metal layer 3 is connected to the source region 14. An interlayer dielectric layer (not shown in fig. 3) is formed on each of the gate region 12 and the source region 14, the gate metal layer 1 and the source metal layer 3 are respectively connected to the gate electrode 51 and the source region 14 through a contact through hole 17 in the interlayer dielectric layer, the contact through hole 17 is filled with a metal layer, and the filled metal layer may be a tungsten layer.

In this embodiment, a Gate contact hole (Gate contact)5 is disposed on the Gate metal layer 1 and used for accessing a Gate electrode potential, as shown in fig. 1, the Gate contact hole 5 is connected to a lateral trench (a first trench 41) and respectively located on the vertical arms at two sides of the Gate region in an inverted "mountain" shape. And a source contact hole 6 is formed in the source metal layer 3 and used for receiving a source potential, and the source contact hole 6 is positioned in the area below the concave opening in the shape of the Chinese character 'ao' in the cellular area. Conductive metal (such as metal tungsten) is filled in the gate contact hole 5 and the source contact hole 6 to realize the connection and disconnection of corresponding potentials, namely, the gate potential is led out from two sides of the cellular area 10, and the source potential of the source region 14 is led out from the center of the cellular area 10, so that the active region is fully utilized, and the utilization rate of the active region is improved.

To sum up, the utility model provides a territory structure of shielding bars power device, including the cell district, the cell district is including crisscross first slot and the second slot that sets up, first slot and second slot play the shielding effect from horizontal and vertical two directions, make on-resistance descend, have strengthened the shielding effect, have improved the high pressure withstand voltage ability of device. Further, the utility model discloses a crisscross first slot that sets up and the design of second slot form closed terminal area overall arrangement in the domain structure of shielding grid power device, have saved terminal area, further improve BV withstand voltage and reduce on-resistance. Additionally, the utility model discloses well grid electrode potential is drawn forth from the gate region of the both sides in cellular region, and the overall arrangement can make active area obtain abundant utilization like this, improves the utilization ratio in active area.

The above description is only for the preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modification and modification made by those skilled in the art according to the above disclosure are all within the scope of the claims.

Claims

1. A layout structure of a shielded gate power device, comprising: the cell area comprises first grooves and second grooves which are arranged in a staggered mode, gate electrodes and shielding gate electrodes are formed in the first grooves and the second grooves, the gate electrodes are located above the shielding gate electrodes, and the gate electrodes and the shielding gate electrodes are insulated through dielectric layers.

2. The layout structure of the shielded gate power device according to claim 1, wherein the first trench and the second trench are vertically arranged, and widths of the first trench and the second trench are equal.

3. The layout structure of the shielded gate power device as claimed in claim 1, wherein the cell region is in a shape of a Chinese character 'ao'.

4. The layout structure of the shielded gate power device as claimed in claim 3, further comprising a gate region, wherein the gate region is in an inverted "mountain" shape and semi-surrounds the cell region.

5. The layout structure of the shielded gate power device as claimed in claim 4, further comprising a gate metal layer located on the gate region and connected to the gate electrode.

6. The layout structure of the shielded gate power device as claimed in claim 5, wherein a gate contact hole is formed on the gate metal layer for accessing a gate electrode potential; the grid contact hole is positioned on the vertical arms at two sides of the inverted Chinese character shan.

7. The layout structure of the shielded gate power device as claimed in claim 4, further comprising an isolation region located at the periphery of the cell region and surrounding the gate region to isolate the cell region from the gate region.

8. The layout structure of the shielded gate power device as claimed in claim 3, further comprising a well region and a source region formed in the substrate at the sides of the first trench and the second trench for forming a shielded gate field effect transistor in the cell region.

9. The layout structure of the shielded gate power device as claimed in claim 8, further comprising a source metal layer located above the source region and connected to the source region.

10. The layout structure of the shielded gate power device according to claim 9, wherein a source contact hole is formed in the source metal layer and used for receiving a source potential; the source contact hole is positioned in the area below the concave opening in the shape of the Chinese character 'ao'.