CN100580928C - Composite field effect transistor structure and manufacturing method thereof - Google Patents

Abstract

The structure of complex type field effect transistor (FET) includes FET of N type lateral double diffusion metallic oxide semiconductor (NLDMOS), and N type junction field effect tube (NJFET). The invention also discloses method for manufacturing the complex type FET. The method includes steps: forming common drain area of NLDMOS and NJFET from N+ diffusion layer in N type extension; forming connection electrode from N+ diffusion layer in N type extension to be as common drain electrode of NLDMOS and NJFET. The disclosed structure and method reduces area of chip effectively so as to be able to provide initial voltage of gate electrode of NLDMOS, and to turn off NLDMOS effectively. The invention reduces power consumption greatly.

Description

A kind of compound field-effect transistor structure and manufacture method thereof

Technical field

The present invention relates to semiconductor device, relate in particular to field-effect transistor.

Background technology

In high voltage integrated circuit, use high pressure lateral double diffusion metal oxide field effect transistor (LDMOS) or fetron (JFET) usually as high pressure resistant device.In order when improving LDMOS or JFET device withstand voltage, to reduce conducting resistance effectively, can realize the high withstand voltage and low on-resistance of circuit by the control electric field.But owing in the same circuit, have only a LDMOS or a JFET.When circuit needs high-voltage LDMOS and high pressure JFET simultaneously, must adopt independent high-voltage LDMOS and these two kinds of discrete components of high pressure JFET, and high-voltage LDMOS and high pressure JFET can take bigger chip area.

On the other hand, in high voltage integrated circuit, sometimes need effectively to control the power supply of high-pressure side for chip.For the circuit that only uses N type LDMOS, if when this circuit start, need provide high voltage supply, adopting enhancement mode NLDMOS can be zero not conducting because of its grid initial voltage, though and if adopt directly conducting and solve the problem that initially powers on of depletion type NLDMOS, it can not control shutoff (grid adds except the negative voltage) by grid.And, the circuit of Gou Chenging complex structure not only like this, and power consumption is also very high.

Summary of the invention

Defective at existing in LDMOS in the above-mentioned high voltage integrated circuit and the JFET use the invention provides a kind of compound field-effect tube structure.

According to one aspect of the present invention, provide a kind of compound field-effect tube structure.It comprises: horizontal double diffusion N type metal-oxide-semiconductor field effect t (NLDMOS) and N type technotron (NJFET).The shared drain region of the NLDMOS of described field-effect tube structure and NJFET, the P type substrate of the P trap substrate of NLDMOS and entire chip is as the grid region of NJFET, use on the P type around whole NLDMOS and the NJFET isolate and the P type under separator (isolating 104 under the P type in the accompanying drawing) form logical isolation, other element separation on the chip at NLDMOS and NJFET and described structure place are come.Between described P trap substrate, the source electrode of a N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) as NJFET arranged to logical isolation and NLDMOS.N type extension is the source electrode of a N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) as NJFET to be arranged between at the bottom of the NLDMOS.N type extension is the drain-drift region of NLDMOS, also is the tagma of NJFET.

Wherein, described NLDMOS comprises:

P type substrate as the substrate of total;

N type extension;

The drain region that N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) in the N type extension forms, wherein the N+ diffusion layer of N type extension (the N+ diffusion layer 112 in the accompanying drawing) forms connection electrode as drain electrode;

Be positioned at the substrate of the P trap 110 of N type extension as described NLDMOS, the P+ diffusion layer on the substrate of described NLDMOS (the P+ diffusion layer 108 in the accompanying drawing) forms connection electrode as the substrate link;

N+ diffusion layer in the substrate of described NLDMOS (the N+ diffusion layer 109 in the accompanying drawing) is as the source region of described NLDMOS, and this source region forms connection electrode as source electrode by N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing);

Across the source region of described NLDMOS and the P trap between the drain region, and the grid polycrystalline silicon that all intersects with the source region of described NLDMOS and drain region is as the grid of described NLDMOS, there are one section active area and one section place in the grid below of described NLDMOS, the thin oxide layer zone of described active area is as gate oxide, described place is positioned at the top, drain region of described NLDMOS, active area is positioned at P trap top, and it is crossing to cross over P trap and source region and drain region, and the length of described NLDMOS grid is the length that active area and P trap substrate intersect.

Wherein, described NJFET comprises:

With drain region, the drain region of described NLDMOS as described NJFET, P trap in the P type substrate of entire chip and the N type extension is as the grid region of described NJFET, wherein the P+ diffusion layer (the P+ diffusion layer 106 in the accompanying drawing) in the separator forms connection electrode as grid on P+ diffusion layer (the P+ diffusion layer 108 in the accompanying drawing) in the P trap and the P type, isolate on the P type and the P type under separator (separator 104 under the P type in the accompanying drawing) form logical isolation, connect P type substrate and grid, form the source electrode of connection electrode as described NJFET with respect to described NLDMOS grid region and near the N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) on the N type extension of source side, described NJFET source electrode N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) is between isolating on the P of described NLDMOS trap substrate and the P type.

Further, near the grid of the described NLDMOS of described compound field-effect tube structure, side near drain electrode, separator under the one P type (separator 103 under the P type in the accompanying drawing) can be arranged between substrate of P type and the N type extension, also can not have separator under the P type (separator 103 under the P type in the accompanying drawing);

Further, one N trap layer can be arranged, also can not have a N trap layer at the described NLDMOS of described compound field-effect tube structure and the drain electrode end of described NJFET;

Further, in described compound field-effect tube structure, on the N type extension of the drain-drift region that is used as described NLDMOS, promptly between the P trap substrate of the drain electrode exit of NLDMOS drain region N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) and NLDMOS, increase a kind of P type diffusion, this P type diffusion can be one section, also can be K section (K＞1).After increasing described P type diffusion, can improve the concentration of N type extension, reduce the conducting resistance of NLDMOS, realize meeting the high withstand voltage optimal design that requires with conducting resistance.

Further, in described compound field-effect tube structure, N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing) as described NLDMOS source region can be contained in the N-diffusion layer, with the P trap substrate that improves described NLDMOS and the withstand voltage in source region, also can be at the N+ in NLDMOS source region diffusion layer (the N+ diffusion layer 109 in the accompanying drawing) neither one N-diffusion layer on every side, when a current potential is connected in the P trap substrate of or NLDMOS lower with the voltage in the P trap substrate that is applicable at NLDMOS and source region and source region;

Further, described compound field effect transistor presents complete centrosymmetric circular configuration.Below with having separator under N trap layer, the P type (separator 103 under the P type in the accompanying drawing) and the field-effect tube structure of N-diffusion layer describes, at described symmetrical centre place is the drain electrode of described NLDMOS and described NJFET, and its drain region is made up of N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing), N trap layer and N type extension.N trap layer has certain distance apart from the P trap in N type extension, the size of this distance has determined the withstand voltage height of NLDMOS and NJFET, and N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) in N trap layer, is positioned at the symmetrical centre place.Be used for separator (separator 103 under the P type of accompanying drawing) under the P type of NLDMOS, be arranged between the N+ diffusion layer (the N+ diffusion layer 112 of accompanying drawing) of the P type substrate of NLDMOS and NLDMOS drain electrode, also between substrate of P type and N type extension.In described field-effect tube structure, the outermost layer of whole NLDMOS and NJFET be isolate on the P type and the P type under separator (separator 104 under the P type in the accompanying drawing) form to logical isolation, described to leading to isolation by P+ diffusion layer (the P+ diffusion layer 106 in the accompanying drawing), connect aluminum strip by contact hole and receive electronegative potential, this contact hole is for isolating contact hole.It between the P trap substrate of isolating contact hole and NLDMOS N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) as the source electrode contact hole of NJFET.Between the N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) of the N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) of the source electrode of NJFET and NLDMOS drain electrode as the P trap, as the substrate of NLDMOS, also as the grid of NJFET.P+ diffusion layer in described NLDMOS substrate (the P+ diffusion layer 108 in the accompanying drawing) is as the substrate contact hole of NLDMOS, N+ diffusion layer in the NLDMOS substrate (the N+ diffusion layer 109 in the accompanying drawing) is as the source electrode of NLDMOS, and the N+ diffusion layer of described NLDMOS source electrode (the N+ diffusion layer 109 in the accompanying drawing) is also as contact hole.Have at the source electrode edge of NLDMOS with above between the drain region of grid polycrystalline silicon across the substrate of NLDMOS and NLDMOS near drain region one side, the below of this grid polycrystalline silicon is the two-stage oxidizing layer, one section is thin oxide layer, one section is thick oxide layer, between the drain region of thin oxide layer across the substrate of NLDMOS and NLDMOS, and an overlapping is arranged with the source electrode of NLDMOS, the size of this overlapping is by the horizontal proliferation decision of N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing), and thick oxide layer is positioned at the top as the N type extension in NLDMOS drain region.This grid polycrystalline silicon is connected to aluminum strip by contact hole, and this grid polycrystalline silicon is exactly the grid of NLDMOS.Can be contained in the N-diffusion layer by N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing), to improve the withstand voltage in NLDMOS substrate and source region the NLDMOS source region.

According to another aspect of the present invention, provide a kind of compound field-effect tube structure.It comprises: NLDMOS and NJFET.The shared drain region of the NLDMOS of described field-effect tube structure and NJFET, the P type substrate of the P trap substrate of NLDMOS and entire chip is as the grid region of NJFET, use on the P type around whole NLDMOS and the NJFET isolate and the P type under separator (separator 104 under the P type in the accompanying drawing) form logical isolation, other element separation on the chip at NLDMOS and NJFET and described structure place are come.Between described P trap substrate, the source of a N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) as NJFET arranged to logical isolation and NLDMOS.N type extension is the drain-drift region of NLDMOS, also is the tagma of NJFET.

Wherein, described NLDMOS comprises:

P type substrate as the substrate of total;

N type extension;

The drain region that N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) in the N type extension forms, wherein the N+ diffusion layer of N type extension (the N+ diffusion layer 112 in the accompanying drawing) forms connection electrode as drain electrode;

Be positioned at the substrate of the P trap of N type extension as described NLDMOS, the P+ diffusion layer on the substrate of described NLDMOS (the P+ diffusion layer 108 in the accompanying drawing) forms connection electrode as the substrate link;

N+ diffusion layer in the P of described NLDMOS trap substrate (the N+ diffusion layer 109 in the accompanying drawing) is as the source region of described NLDMOS, and this source region forms connection electrode as source electrode by N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing);

Across the source region of described NLDMOS and the P trap between the drain region, and the grid polycrystalline silicon that all intersects with the source region of described NLDMOS and drain region is as the grid of described NLDMOS, there are one section active area and one section place in the grid polycrystalline silicon below of described NLDMOS, the thin oxide layer zone of described active area is as gate oxide, described place is positioned at the top, drain region of described NLDMOS, active area is positioned at P trap top, and it is crossing to cross over P trap and source region and drain region, and the length of described NLDMOS grid is the length that active area and P trap substrate intersect.

Wherein, described NJFET comprises:

With drain region, the drain region of described NLDMOS as described NJFET, P trap in the P type substrate of entire chip and the N type extension is as the grid region of described NJFET, P+ diffusion layer (the P+ diffusion layer 106 in the accompanying drawing) in wherein isolating on P+ diffusion layer (the P+ diffusion layer 108 in the accompanying drawing) in the P trap and the P type is connected to form grid as electrode, isolate on the P type and the P type under separator (separator 104 under the P type in the accompanying drawing) form logical isolation, connect P type substrate and grid, form the source electrode of connection electrode as described NJFET with respect to described NLDMOS grid region and near the N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) on the N type extension of source side, described NJFET source electrode N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) is between isolating on the P of described NLDMOS trap substrate and the P type.

Further, in described compound field-effect tube structure, near the grid of NLDMOS, near drain electrode one side, separator under the one P type (separator 103 under the P type in the accompanying drawing) can be arranged between substrate of P type and the N type extension, also can not have separator under the P type (separator 103 under the P type in the accompanying drawing);

Further, the described NLDMOS of described compound field-effect tube structure and the drain electrode of NJFET extremely can have a N trap layer, also can not have a N trap layer;

Further, in described compound field-effect tube structure, be used as on the N type extension of NLDMOS drain-drift region, promptly between the P trap substrate of the drain electrode exit of the N+ in NLDMOS drain region diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) and NLDMOS, increase a kind of p type diffused layer, this p type diffused layer can be one section, it also can be K section (K＞1), after increasing described P type diffusion, can improve the concentration of N type extension, reduce the conducting resistance of NLDMOS, realize meeting the high withstand voltage optimal design that requires with conducting resistance;

Further, in described compound field-effect tube structure, N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing) as described NLDMOS source region can be contained in the N-diffusion layer, with the P trap substrate that improves described NLDMOS and the withstand voltage in source region, also can be around the N+ in NLDMOS source region diffusion 2 neither one N-diffusion layer, when a current potential is connected in the P trap substrate of or NLDMOS lower with the voltage in the P trap substrate that is applicable at NLDMOS and source region and source region;

Further, described compound field effect transistor presents the centrosymmetric circular configuration of part, and wherein NLDMOS presents complete center symmetry, and NJFET presents part center symmetry.Below utilize and have separator under N trap layer, the P type (separator 103 under the P type in the accompanying drawing) and the field-effect tube structure of N-diffusion layer describes.At the symmetrical centre place is the drain region of described high pressure NLDMOS and high pressure NJFET, and this drain region is made up of N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing), N trap layer and N type extension.Described N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) has certain distance apart from the P trap, the size of this distance has determined the withstand voltage height of NLDMOS and NJFET, described N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) is positioned at the symmetrical centre place in described N trap layer.Be used for separator (separator 103 under the P type of accompanying drawing) under the P type of NLDMOS, be arranged between the N+ diffusion layer (the N+ diffusion layer 112 of accompanying drawing) of the P type substrate of NLDMOS and NLDMOS drain electrode, also between substrate of P type and N type extension.In described compound field-effect tube structure, the outermost layer of whole NLDMOS and NJFET be isolate on the P type and the P type under separator (separator 104 under the P type in the accompanying drawing) form to logical isolation, described to leading to isolation by P+ diffusion layer (the P+ diffusion layer 106 in the accompanying drawing), connect aluminum strip by contact hole and receive electronegative potential, this contact hole is for isolating contact hole.Drain electrode center by NLDMOS is outside, beyond the P of NLDMOS trap substrate, present part center symmetry, in same figure, here be divided into two sections arcs, one section arcuate structure wherein is the N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) that is used as the source electrode contact hole of NJFET between the P trap substrate of isolating contact hole and NLDMOS; Another section arc is the N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) that is not used as the source electrode contact hole of NJFET between the P trap substrate of isolating contact hole and NLDMOS.The size of these two sections arcs can be according to the convenience of domain and actual needs change.Between the N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) of the N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) of the source electrode of NJFET and NLDMOS drain electrode as the P trap, as the substrate of NLDMOS, also as the grid of NJFET.Be useful on the P+ diffusion layer (the P+ diffusion layer 108 in the accompanying drawing) of the substrate contact hole of NLDMOS and be used for the N+ diffusion layer (the N+ diffusion layer 109 of accompanying drawing) of NLDMOS source electrode in the substrate of NLDMOS, the N+ diffusion layer of NLDMOS source electrode (the N+ diffusion layer 109 in the accompanying drawing) also is used for contact hole.Have at the source electrode edge of NLDMOS with above between the drain region of grid polycrystalline silicon across the substrate of NLDMOS and NLDMOS near drain region one side, the below of this grid polycrystalline silicon is the two-stage oxidizing layer, one section is thin oxide layer, another section is a thick oxide layer, between the drain region of thin oxide layer across the substrate of NLDMOS and NLDMOS, and an overlapping is arranged with the source electrode of NLDMOS, the size of this overlapping is by the horizontal proliferation decision of N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing), and thick oxide layer is positioned at the top as the N type extension in NLDMOS drain region.This grid polycrystalline silicon is connected to aluminum strip by contact hole, and this grid polycrystalline silicon is exactly the grid of NLDMOS.Can be contained in the N-diffusion layer by N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing), to improve the withstand voltage in NLDMOS substrate and source region the NLDMOS source region.

According to another aspect of the present invention, provide a kind of manufacture method of compound field effect transistor.It comprises:

With the P type substrate of NLDMOS substrate as entire chip;

On the N of NLDMOS type extension, form N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing), N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing), N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing), P+ diffusion layer (the P+ diffusion layer 106 in the accompanying drawing) and P+ diffusion layer (the P+ diffusion layer 108 in the accompanying drawing);

Produce on the P type around described whole NLDMOS and the NJFET isolate and the P type under separator (separator 104 under the P type in the accompanying drawing) form logical isolation;

With the substrate of the P trap in the described N type extension, and use the substrate of described NLDMOS to comprise described N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing) and described P+ diffusion layer (the P+ diffusion layer 108 in the accompanying drawing) as described NLDMOS; With

Described N+ diffusion layer in the described N type extension (the N+ diffusion layer 112 in the accompanying drawing) is formed the drain region of described NLDMOS, and use described N+ diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) to form connection electrode as described NLDMOS and the common drain electrode of described NJFET; Described P+ diffusion layer on the substrate of described NLDMOS (the P+ diffusion layer 108 in the accompanying drawing) is formed the substrate link of connection electrode as described NLDMOS; With the source region of the described N+ diffusion layer in the substrate of described NLDMOS (the N+ diffusion layer 109 in the accompanying drawing) as described NLDMOS, and by the source electrode of described N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing) formation connection electrode as described NLDMOS; Will be across the source region of described NLDMOS and the P trap between the drain region, and the grid polycrystalline silicon that all intersects with source region and the drain region of described NLDMOS is as the grid of described NLDMOS; With

Described P+ diffusion layer (the P+ diffusion layer 106 in the accompanying drawing) in isolating on described P+ diffusion layer in the described P trap (the P+ diffusion layer 108 in the accompanying drawing) and the described P type is formed the grid of connection electrode as described NJFET; Forming the source electrode of connection electrode with respect to the grid region of described NLDMOS and near the described N+ diffusion layer (the N+ diffusion layer 107 in the accompanying drawing) on the N type extension of the source side of described NLDMOS as described NJFET.

In addition, in described compound field effect transistor, near the grid of NLDMOS and near drain electrode one side, can be added with separator under the P type (separator 103 under the P type in the accompanying drawing) between substrate of P type and the N type extension, also can not add separator under the P type (separator 103 under the P type in the accompanying drawing);

In addition, in described compound field effect transistor, extremely can add a N trap layer, also can not add a N trap layer in the drain electrode of NLDMOS and NJFET;

In addition, in described compound field effect transistor, between the P trap substrate of the drain electrode exit of the N+ in NLDMOS drain region diffusion layer (the N+ diffusion layer 112 in the accompanying drawing) and NLDMOS, can add the p type diffused layer of a section or K section (K＞1), further, increase described p type diffused layer after, can improve the concentration of N type extension, reduce the conducting resistance of NLDMOS, realize the optimal design of chip;

In addition, in described compound field effect transistor, between P trap and N+ diffusion layer (the N+ diffusion layer 109 in the accompanying drawing), can add a N-diffusion layer, also can not add a N-diffusion layer, further, after adding described N-diffusion layer, the P trap substrate of described NLDMOS and the withstand voltage in source region be will improve, the P trap substrate of the lower or NLDMOS of the voltage in the P trap substrate of NLDMOS and source region and source region will not be mainly used in when connecting a current potential and do not add described N-diffusion layer;

In addition, described compound field effect transistor can manufacture and present complete centrosymmetric circular configuration, also can manufacture and present the centrosymmetric circular configuration of part, further, in the centrosymmetric circular configuration of part, the NLDMOS structure presents complete center symmetry, and the NJFET structure presents part center symmetry.

Utilize compound field-effect tube structure of the present invention, when the high-pressure side of NLDMOS and NJFET applies identical voltage, can effectively reduce chip area, the grid initial voltage of NLDMOS can not only be provided, also can effectively turn-off NLDMOS, thereby greatly reduce power consumption.

Description of drawings

The reader will become apparent various aspects of the present invention after the reference accompanying drawing has been read the specific embodiment of the present invention.Wherein,

Fig. 1 shows the whole longitudinal profile structural representation of compound field effect transistor of the present invention;

Fig. 2 shows compound field effect transistor of the present invention and is complete centrosymmetric longitudinal profile structural representation;

Fig. 3 shows the longitudinal profile structural representation that compound field effect transistor of the present invention has P type diffusion 539;

Fig. 4 shows the longitudinal profile structural representation that compound field effect transistor of the present invention does not have N trap layer 111;

Fig. 5 illustrates the longitudinal profile structural representation that compound field effect transistor of the present invention does not have isolation 103 under the P type;

Fig. 6 shows the longitudinal profile structural representation that compound field effect transistor of the present invention has N-diffusion layer 640;

Fig. 7 is that compound field effect transistor of the present invention presents centrosymmetric vertical figure and vertical view;

Fig. 8 is that compound field effect transistor of the present invention presents centrosymmetric vertical figure of part and vertical view; And

Fig. 9 is corresponding to the NLDMOS of Fig. 1 to Fig. 8 and the electrical block diagram of NJFET.

Embodiment

With reference to the accompanying drawings, various embodiment of the present invention are described in further detail.

Fig. 2 shows a kind of embodiment of compound field effect transistor of the present invention.

As shown in Figure 2, compound field effect transistor presents complete center symmetry, and has separator 103 and N trap layer 111 under the P type.Separator 103 is near the grid polycrystalline silicon 130 of NLDMOS and near between the P type substrate 101 and N type extension 102 of drain electrode one side, the drain electrode that described N trap layer 111 is positioned at NLDMOS and NJFET is extreme under the described P type.In described compound field-effect tube structure, the shared drain region of NLDMOS and NJFET, the P type substrate 101 of the P trap substrate of NLDMOS and entire chip is as the grid region of NJFET, isolate logical, other elements on NLDMOS and NJFET and the described structure place chip are separated using on the P type under the separator 105 and P type separator 104 to form around whole NLDMOS and the NJFET.Between described P trap substrate, the source region of a N+ diffusion layer 107 as NJFET arranged to logical isolation and NLDMOS.N type extension 102 is the drain-drift region of NLDMOS, also is the tagma of NJFET.

Fig. 3 has increased by a p type diffused layer 539 on the basis of Fig. 2, described p type diffused layer 539 is between the P trap substrate of the drain electrode exit of NLDMOS drain region N+ diffusion layer 112 and NLDMOS.After having increased described p type diffused layer 539, the fundamental characteristics of entire chip is constant, and can improve the concentration of N type extension 102, reduces the conducting resistance of NLDMOS, to realize the optimal design of chip.

Fig. 4 has removed a N trap layer 111 on the basis of Fig. 2.Use does not have the described structure of N trap layer 111, can strengthen the conducting resistance of NLDMOS and NJFET, is suitable for being applied in the less demanding circuit of conducting resistance.

Fig. 5 is removing separator 103 under the P type on the basis of Fig. 2, use the described structure that does not have separator 103 under the P type, can improve the pinch-off behavior of NJFET, makes NJFET have constant-current characteristics preferably.

Fig. 6 has increased by a N-diffusion layer 640 on the basis of Fig. 2.Described N-diffusion layer 640 is positioned at P trap substrate 110, the N+ diffusion layer 109 in NLDMOS source region is contained in the described N-diffusion layer 640, can improve the substrate of NLDMOS and the withstand voltage between the end of source, be suitable for being applied in substrate and source end and need bear big withstand voltage circuit.

Fig. 7 shows the another embodiment of compound field-effect tube structure of the present invention.As shown in Figure 7, total presents complete centrosymmetric circular configuration, has separator 103 under N trap layer 111 and the P type in the described circular configuration.Being positioned at the center is the drain electrode of this high pressure NLDMOS and high pressure NJFET, and this drain region is made up of N+ diffusion layer 112, N trap layer 111 and N type extension 102.N trap layer 111 is in N type extension 102, apart from P trap 110 certain distance is arranged, the size of this distance has determined the withstand voltage of NLDMOS and NJFET, and described N+ diffusion layer 112 is in described N trap layer 111, be arranged in center (in the structure that does not have N trap layer 111, N+ diffusion layer 112 is positioned at the center).From symmetrical centre outward, be used for separator 103 under the P type of NLDMOS between the N+ diffusion layer 112 of the substrate of NLDMOS and NLDMOS drain electrode, also between P type substrate 101 and N type extension 102.The outermost layer of whole NLDMOS and NJFET is isolating logical that separator 104 is formed under separator 105 and the P type on the P type, describedly isolates by P+ diffusion layer 106 logical, connects aluminum strip by contact hole and receives electronegative potential, and this contact hole is for isolating contact hole.It between the P trap substrate of isolating contact hole and NLDMOS N+ diffusion layer 107 as the source electrode contact hole of NJFET, between the N+ diffusion layer 112 of the source electrode N+ of NJFET diffusion layer 107 and NLDMOS drain electrode as P trap 110, as the substrate of NLDMOS, also be used as the grid of NJFET.P+ diffusion layer 108 in the NLDMOS substrate is as the substrate contact hole of NLDMOS, and the N+ diffusion layer 109 in the NLDMOS substrate is as the source electrode of NLDMOS, and the N+ diffusion layer 109 of NLDMOS source electrode also is used for contact hole.Have at the source electrode edge of NLDMOS with above between the drain region of grid polycrystalline silicon 130 across the substrate of NLDMOS and NLDMOS near drain region one side, there is the two-stage oxidizing layer described grid polycrystalline silicon 130 belows, one section is thin oxide layer 129, one section is thick oxide layer, between the drain region of thin oxide layer 129 across the substrate of NLDMOS and NLDMOS, and an overlapping is arranged with the source electrode of NLDMOS, the size of this overlapping is by the horizontal proliferation decision of N+ diffusion layer 109, and thick oxide layer is positioned at the top as the N type extension 102 in NLDMOS drain region.Described grid polycrystalline silicon 130 is connected to aluminum strip by contact hole, and this grid polycrystalline silicon 130 is exactly the grid of NLDMOS.Can be contained in by N+ diffusion layer 109 in the N-diffusion layer 640, to improve the withstand voltage in NLDMOS substrate and source region the NLDMOS source region.

Fig. 8 is the another embodiment of compound field-effect tube structure of the present invention.Described compound field effect transistor presents the centrosymmetric circular configuration of part, and wherein NLDMOS presents complete center symmetry, and NJFET presents part center symmetry.Described compound field effect transistor has separator 103 and N-diffusion layer 640 under N trap layer 111, the P type.At the symmetrical centre place is the drain region of described NLDMOS and NJFET, and this drain region is made up of N+ diffusion layer 112, N trap layer 111 and N type extension 102.Described N+ diffusion layer 112 has certain distance apart from P trap 110, and the size of this distance has determined the withstand voltage height of NLDMOS and NJFET, and described N+ diffusion layer 112 is positioned at the symmetrical centre place in described N trap layer 111.Be used for separator 103 under the P type of NLDMOS, between the N+ diffusion layer 112 of substrate 101 of the P of NLDMOS type and NLDMOS drain electrode, also between P type substrate 101 and N type extension 102.In described compound field-effect tube structure, the outermost layer of whole NLDMOS and NJFET is isolating logical that separator 104 is formed under separator 105 and the P type on the P type, describedly isolate by P+ diffusion layer 106 logical, connect aluminum strip by contact hole and receive electronegative potential, this contact hole is for isolating contact hole.Drain electrode center by NLDMOS is outside, beyond the P of NLDMOS trap substrate, present part center symmetry, in same figure, here be divided into two sections arcs, one section arcuate structure wherein is the N+ diffusion layer 107 that is used as the source electrode contact hole of NJFET between the P trap substrate of isolating contact hole and NLDMOS; Another section arc is the N+ diffusion layer 107 that is not used as the source electrode contact hole of NJFET between the P trap substrate of isolating contact hole and NLDMOS.The size of these two sections arcs can be according to the convenience of domain and actual needs change.Substrate that having between the source electrode N+ of NJFET diffusion layer 107 and NLDMOS source electrode N+ diffusion layer 112 is used as NLDMOS and the P trap 110 that is used as the grid of NJFET.Be useful on the P+ diffusion layer 108 and the N+ diffusion layer 109 that is used for the source electrode of NLDMOS of the substrate contact hole of NLDMOS in the substrate of NLDMOS, the N+ diffusion layer 109 of NLDMOS source electrode also is used for contact hole.Have at the source electrode edge of NLDMOS with above between the drain region of grid polycrystalline silicon 130 across the substrate of NLDMOS and NLDMOS near drain region one side, described grid polycrystalline silicon 130 belows are two-stage oxidizing layers, one section is thin oxide layer 129, another section is a thick oxide layer, between the drain region of thin oxide layer 129 across the substrate of NLDMOS and NLDMOS, and an overlapping is arranged with the source electrode of NLDMOS, the size of this overlapping is by the horizontal proliferation decision of N+ diffusion layer 109, and thick oxide layer is positioned at the top as the N type extension 102 in NLDMOS drain region.Described grid polycrystalline silicon 130 is connected to aluminum strip by contact hole, and this grid polycrystalline silicon 130 is exactly the grid of NLDMOS.Can be contained in by N+ diffusion layer 109 in the N-diffusion layer 640, to improve the withstand voltage in NLDMOS substrate and source region the NLDMOS source region.

Fig. 9 shows corresponding to the NLDMOS of Fig. 1 to Fig. 8 and the electrical block diagram of NJFET.Wherein, NJFET431, NLDMOS432 correspond respectively to NJFET and the NLDMOS among Fig. 1; The grid 433 of NJFET431 is corresponding to contact extraction electrode 113 of the isolation among Fig. 1-8 and P trap extraction electrode 115, the source electrode 434 of NJFET431 is corresponding to the source electrode extraction electrode 114 among Fig. 1-8, and the common drain 437 of NJFET431 and NLDMOS432 is corresponding to the drain electrode exit 118 among Fig. 1-8.The substrate utmost point 438 of NLDMOS 432 is corresponding to the P trap exit 115 among Fig. 1-8, and the grid 435 of NLDMOS432 is corresponding to the grid 130 of the NLDMOS among Fig. 1-8, and the source electrode 436 of NLDMOS432 is corresponding to the source electrode 116 of the NLDMOS among Fig. 1-8.

Above, describe the specific embodiment of the present invention with reference to the accompanying drawings.But those skilled in the art can understand, and under situation without departing from the spirit and scope of the present invention, can also do various changes and replacement to the field-effect transistor types in the specific embodiment of the present invention and functional layer length etc.These changes and replace all drop in claims of the present invention institute restricted portion.

Claims (28)

1. compound field-effect transistor structure, it is characterized in that, it comprises: lateral double diffusion metal oxide field effect transistor LDMOS and technotron JFET, described LDMOS and described JFET all have source region and grid region separately, and described LDMOS and the shared identical drain region of described JFET, described LDMOS and described JFET are respectively enhancement mode NLDMOS and NJFET, described NJFET comprises: with the drain region as described NJFET, the drain region of described NLDMOS, wherein the N+ diffusion layer (112) on the N type extension (102) forms the drain electrode of connection electrode as described NJFET; P trap (110) in P type substrate (101) and the N type extension (102) is as the grid region of described NJFET, wherein the 2nd P+ diffusion layer (106) in the separator (105) forms the grid of connection electrode as described NJFET on P+ diffusion layer (108) in the P trap (110) and the P type, forms the source electrode of connection electrode as described NJFBT with respect to described NLDMOS grid region and near the 2nd N+ diffusion layer (107) on the N type extension (102) of LDMOS source side.

2. structure as claimed in claim 1 is characterized in that, described NLDMOS comprises: P type substrate (101); N type extension (102); Be positioned at the substrate of the P trap (110) of described N type extension (102) as described NLDMOS, the described P+ diffusion layer (108) in the described P trap (110) forms connection electrode as the substrate link.

3. structure as claimed in claim 2, it is characterized in that, described NLDMOS comprises: the drain region that the described N+ diffusion layer (112) in the described N type extension (102) forms, and a described N+ diffusion layer (112) of wherein said N type extension (102) forms the drain electrode of connection electrode as described NLDMOS; The 3rd N+ diffusion layer (109) in the substrate of described NLDMOS is as the source region of described NLDMOS, and by described the 3rd N+ diffusion layer (109) formation connection electrode as source electrode; Across the source region of described NLDMOS and the described P trap (110) between the drain region, the grid polycrystalline silicon (130) that all intersects with the source region of described NLDMOS and drain region is as the grid of described NLDMOS.

4. structure as claimed in claim 1 is characterized in that, described the 2nd N+ diffusion layer (107) of described NJFET source electrode is positioned on described P trap (110) and the P type between the separator (105).

5. structure as claimed in claim 3 is characterized in that, near the grid of described NLDMOS, and a side of close drain electrode, separator (103) under the P type is arranged between described P type substrate (101) and described N type extension (102).

6. structure as claimed in claim 1 is characterized in that, at the drain electrode end of described NLDMOS and described NJFET one N trap layer (111) is arranged.

7. structure as claimed in claim 1, it is characterized in that, between described P trap (110) substrate of the drain electrode exit (118) of the N+ diffusion layer (112) in described NLDMOS drain region and described NLDMOS, increase a kind of P type diffusion (539), described P type diffusion (539) is one section.

8. structure as claimed in claim 1, it is characterized in that, between described P trap (110) substrate of the drain electrode exit (118) of the N+ diffusion layer (112) in described NLDMOS drain region and described NLDMOS, increase a kind of P type diffusion (539), described P type diffusion (539) is the K section, and wherein K is greater than 1.

9. structure as claimed in claim 1 is characterized in that, comprises a N-diffusion layer (640) between described the 3rd N+ diffusion layer (109) that is used as described NLDMOS source region and described P trap (110).

10. structure as claimed in claim 1 is characterized in that, described compound field-effect transistor presents complete centrosymmetric circular configuration or presents the centrosymmetric circular configuration of part.

11. structure as claimed in claim 10 is characterized in that, when described compound field-effect transistor presented the centrosymmetric circular configuration of part, described NLDMOS presented complete center symmetry, and described NJFET presents part center symmetry.

12. structure as claimed in claim 1, it is characterized in that, isolate logical using on the described P type under the separator (105) and the 2nd P type separator (104) to form around whole described LDMOS and the described JFET, and logical isolation is separated other elements on the chip at described LDMOS and described JFET and described structure place by described.

13. the manufacture method of a compound field-effect transistor is characterized in that, it comprises:

Step (a): with the P type substrate (101) of NLDMOS substrate as entire chip;

Step (b): with the substrate of the P trap (110) on the N type extension (102) as described NLDMOS;

Step (c): the described N type extension (102) at described NLDMOS goes up formation the one N+ diffusion layer (112), the 2nd N+ diffusion layer (107), the 3rd N+ diffusion layer (109), the 2nd P+ diffusion layer (106) and a P+ diffusion layer (108);

Step (d): go up described NLDMOS of formation and the common drain electrode (437) of described NJFET in described N type extension (102);

Step (e): go up source electrode (436) and the grid (435) that forms described NLDMOS in described N type extension (102);

Step (f): go up the substrate link (438) that forms described NLDMOS in described N type extension (102);

Step (g): go up source electrode (434) and the grid (433) that forms described NJFET in described N type extension (102), in step (g),, and form the source electrode (434) of connection electrode as described NJFET near described the 2nd N+ diffusion layer (107) on the N type extension (102) of described NLDMOS source side in grid region with respect to described NLDMOS.

14. method as claimed in claim 13 is characterized in that, in described step (a) and step (b) are contained in described the 3rd N+ diffusion layer (109) and a described P+ diffusion layer (108) described P trap (110) on the described N type extension (102).

15. method as claimed in claim 13, it is characterized in that, in step (c) and step (d), described N+ diffusion layer (112) on the described N type extension (102) is formed described NLDMOS and the common drain region of described NJFET, and use a described N+ diffusion layer (112) to form connection electrode as described NLDMOS and the common drain electrode (437) of described NJFET.

16. method as claimed in claim 13, it is characterized in that, in step (e),, and form the source electrode (436) of connection electrode as described NLDMOS by described the 3rd N+ diffusion layer (109) with the source region of described the 3rd N+ diffusion layer (109) in the described NLDMOS substrate as described NLDMOS.

17. method as claimed in claim 13, it is characterized in that, also comprise in step (e): across the source region of described NLDMOS and the described P trap (110) between the drain region, the grid polycrystalline silicon (130) that all intersects with the source region of described NLDMOS and drain region is as the grid (435) of described NLDMOS.

18. method as claimed in claim 13 is characterized in that, in step (f) the described P+ diffusion layer (108) on the described NLDMOS substrate is formed the substrate link (438) of connection electrode as described NLDMOS.

19. method as claimed in claim 13, it is characterized in that, in step (g), also comprise: described the 2nd P+ diffusion layer (106) of isolating on described P+ diffusion layer (108) in the described P trap (110) and the described P type in (105) is formed the grid (433) of connection electrode as described NJFET.

20. method as claimed in claim 13 is characterized in that, near the grid of described NLDMOS, and a side of close drain electrode, forming separator (103) under the P type between described P type substrate (101) and the described N type extension (102).

21. method as claimed in claim 13 is characterized in that, at the extreme N trap layer (111) that forms of the drain electrode of described NLDMOS and described NJFET.

22. method as claimed in claim 13, it is characterized in that, between described P trap (110) substrate of the described N+ diffusion layer (112) in described NLDMOS drain region and described NLDMOS, form a kind of p type diffused layer (539), and described P type diffusion (539) is one section.

23. method as claimed in claim 13, it is characterized in that, between described P trap (110) substrate of the described N+ diffusion layer (112) in described NLDMOS drain region and described NLDMOS, form a kind of p type diffused layer (539), and described P type diffusion (539) is the K section, and wherein K is greater than 1.

24. method as claimed in claim 13 is characterized in that, forms a N-diffusion layer (640) in described P trap (110), and makes described N-diffusion layer (640) comprise described the 3rd N+ diffusion layer (109).

25. method as claimed in claim 13 is characterized in that, adopts complete centrosymmetric circular configuration to form the composite structure of described NLDMOS and described NJFET formation.

26. method as claimed in claim 13 is characterized in that, adopts the centrosymmetric circular configuration of part to adopt the composite structure of described NLDMOS of formation and described NJFET formation.

27. method as claimed in claim 26 is characterized in that, when described composite structure presents when having the centrosymmetric circular configuration of part, described NLDMOS adopts complete center symmetry, and described NJFET adopts part center symmetry.

28. method as claimed in claim 13, it is characterized in that, adopt spacer medium to form the interelectrode insulation of described NLDMOS and described NJFET, and it is formed to logical isolation, with other element separation on the chip at described NLDMOS and described NJFET and described structure place by separator (104) under isolation (105) and the 2nd P type on the P type.

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