CN108695384A - High electron mobility transistor - Google Patents
High electron mobility transistor Download PDFInfo
- Publication number
- CN108695384A CN108695384A CN201710220931.6A CN201710220931A CN108695384A CN 108695384 A CN108695384 A CN 108695384A CN 201710220931 A CN201710220931 A CN 201710220931A CN 108695384 A CN108695384 A CN 108695384A
- Authority
- CN
- China
- Prior art keywords
- layer
- grid
- electron mobility
- high electron
- mobility transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000010410 layer Substances 0.000 claims abstract description 194
- 239000011241 protective layer Substances 0.000 claims abstract description 49
- 230000004888 barrier function Effects 0.000 claims abstract description 47
- 238000002161 passivation Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000013459 approach Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000013589 supplement Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
This disclosure relates to a kind of high electron mobility transistor, including:Substrate, channel layer, barrier layer, drain electrode, grid, source electrode and multiple protective layers; substrate, channel layer, barrier layer stack gradually from the bottom to top; source electrode and drain electrode is respectively formed at the left and right ends of barrier layer upper surface, grid be formed between source electrode and drain electrode and respectively with source electrode and drain electrode interval;Multiple protective layers stack the barrier layer upper surface being arranged between source electrode and drain electrode and are covered on grid;Each protective layer in multiple protective layers includes the shielded layer of passivation layer and formation on the passivation layer, and from the edge of grid, gradually approach drains the shielded layer in multiple protective layers from bottom to top;It is least partially overlapped in the projection on the direction of barrier layer upper surface positioned at the shielded layer of bottom and grid in multiple protective layers.By the technical solution of the disclosure, its breakdown voltage can be improved in the case where not increasing high electron mobility transistor conducting resistance, while reducing parasitic input capacitance and feedback capacity.
Description
Technical field
This disclosure relates to technical field of semiconductors, and in particular, to a kind of high electron mobility transistor.
Background technology
With the development of science and technology, the power device with more third generation semi-conducting material manufacturings a little is a dark horse,
Wherein start the second generation semiconductor power device for gradually replacing Si, GaAs representative by the power device represented of GaN base.Phase
Than in the high electron mobility transistor of Si and GaAs making, GaN base high electron mobility transistor (High Electron
Mobility Transistor, HEMT) there is the characteristics such as better frequency, efficiency and higher power, and then extensive use
Microwave, RF application power device in.In civil field, with the development of 5G technologies, LDMOS (Lateral Double-
Diffused Metal-Oxide Semiconductor) it will cannot be satisfied with the demand of base station power amplification system, by GaN HEMT
Power device replaces LDMOS device that will become display needs.
The power characteristic of device and breakdown characteristics are closely related, in order to make power device have good power characteristic with more
Meet the needs of base station power amplification system well, its breakdown voltage should be improved as much as possible when designing GaN HEMT devices.
In the related technology, usually by increasing the distance between the source electrode and drain electrode of GaN HEMT devices, or deposit list
Layer shielding layer structure improves the breakdown voltage of GaN HEMT devices.But the distance for increasing source electrode and drain electrode increases leading for device
Be powered resistance, and single-layer shield layer structure may cause punch through voltage reduction or because under shielded layer because shielded layer length is long
Square barrier layer thickness is too low and parasitic capacitance is caused to increase.
Invention content
To achieve the goals above, the disclosure provides a kind of high electron mobility transistor, including:Substrate, channel layer, gesture
Barrier layer, drain electrode, grid, source electrode and multiple protective layers, the substrate, the channel layer, the barrier layer are from the bottom to top successively
It stacks, the source electrode and described drain are respectively formed at the left and right ends of the barrier layer upper surface, and the grid is formed in institute
State between source electrode and the drain electrode and respectively with the source electrode and the drain space;
The multiple protective layer stack the upper surface for the barrier layer being arranged between the source electrode and the drain electrode and
It is covered on the grid;
Each protective layer in the multiple protective layer includes passivation layer and the shielded layer that is formed on the passivation layer, institute
The shielded layer stated in multiple protective layers gradually approaches the drain electrode from bottom to top from the edge of the grid;
Positioned at the shielded layer of bottom and the grid perpendicular to the barrier layer upper surface in the multiple protective layer
Projection on direction is least partially overlapped.
Optionally, the thickness of the passivation layer of bottom is uniform in the multiple protective layer;
The passivation layer positioned at bottom includes:Half passivation layer of a left side between the source electrode and the grid, position
Half passivation layer of the right side between the grid and the drain electrode and the intermediate passivation layer for being covered in the gate surface.
Optionally, the shielded layer of the bottom extends to right half passivation layer from the upper surface of the intermediate passivation layer
Upper surface and the shielded layer thickness it is uniform.
Optionally, the shape phase of the shape of remaining shielded layer in the multiple protective layer and the shielded layer of the bottom
Together.
Optionally, the shielded layer in the multiple protective layer the projection on the direction of the barrier layer upper surface extremely
Small part is overlapped.
Optionally, the shielded layer in the multiple protective layer the projection on the direction of the barrier layer upper surface it
Between spacing distance be less than or equal to 0.2um.
Optionally, the shielded layer in the multiple protective layer is electrically connected with the source electrode respectively.
Optionally, the length of the shielded layer in the multiple protective layer is more than 0.5um.
Optionally, the square resistance resistance value of the shielded layer in the multiple protective layer is less than 10 Ω.
Optionally, the material of the passivation layer in the multiple protective layer includes SiN and SiO2。
Through the above technical solutions, by using multilayer screen layer structure, high electron mobility crystal can not increased
Its breakdown voltage is improved in the case of the conducting resistance of pipe, while can reduce its parasitic input capacitance and feedback capacity.
Other feature and advantage of the disclosure will be described in detail in subsequent specific embodiment part.
Description of the drawings
Attached drawing is for providing further understanding of the disclosure, and a part for constitution instruction, with following tool
Body embodiment is used to explain the disclosure together, but does not constitute the limitation to the disclosure.In the accompanying drawings:
Fig. 1 is the cross-sectional view according to the high electron mobility transistor of an embodiment of the present disclosure;
The schematic diagram that barrier layer surface field line is distributed in high electron mobility transistor when Fig. 2 is unshielded layers;
Fig. 3 is the schematic diagram that barrier layer surface field line is distributed in high electron mobility transistor when having shielded layer;
Fig. 4 is the cross-sectional view according to the high electron mobility transistor of the another embodiment of the disclosure.
Reference sign
1 substrate, 2 channel layer
3 barrier layer, 4 grid
5 source electrodes 6 drain
71 first passivation layer, 72 first screen layer
81 second passivation layer, 82 secondary shielding layer
91 third passivation layer, 92 third shielded layer
Specific implementation mode
The specific implementation mode of the disclosure is described in detail below in conjunction with attached drawing.It should be understood that this place is retouched
The specific implementation mode stated is only used for describing and explaining the disclosure, is not limited to the disclosure.
In the disclosure, in the absence of explanation to the contrary, the noun of locality used such as " upper and lower, left and right " is typically phase
For the page of attached drawing.
Fig. 1 is the cross-sectional view according to the high electron mobility transistor of an embodiment of the present disclosure.Such as
Shown in Fig. 1, by taking the quantity of protective layer is 2 as an example.The high electron mobility transistor includes:Substrate 1, channel layer 2, barrier layer
3, grid 4, source electrode 5, the 6, first protective layer of drain electrode and the second protective layer.
Wherein, substrate 1, channel layer 2 and barrier layer 3 stack gradually from the bottom to top.For example, channel layer 2 can be by substrate 1
Upper epitaxial structures growth is formed, and barrier layer 3 is formed on channel layer 2.
The material of substrate 1 can for example include but not limited to:SiC, Si and sapphire etc..
The thickness of channel layer is 1~4um, and material can be GaN.
Its thickness of barrier layer is 0.1~0.5um, and material can be AlGaN.
Source electrode 5 and drain electrode 6 are respectively formed at the left and right ends of 3 upper surface of barrier layer, and grid 4 is formed in source electrode 5 and drain electrode 6
Between and respectively with source electrode 5 and drain electrode 6 interval, grid 4, source electrode 5 and drain electrode 6 can by the upper surface of barrier layer 3 deposit shape
At.In addition, source electrode 5 and drain electrode 6 use Ohmic contact between barrier layer 3 respectively, to reduce its contact resistance;Grid 4 and gesture
Schottky contacts are used between barrier layer 3.
First protective layer is arranged the upper surface of the barrier layer 3 between source electrode 5 and drain electrode 6 and is covered on grid 4, second
Protective layer is stacked on the first protective layer.
It passivation layer 71 and the first screen layer 72 that is formed on the first passivation layer 71 that first protective layer, which includes first,;Second protects
It passivation layer 81 and the secondary shielding layer 82 that is formed on the second passivation layer 81 that sheath, which includes second,.First passivation layer 71 and second is blunt
Change layer 81 material can for example including:SiN and SiO2。
First screen layer 72 is least partially overlapped in the projection on 3 upper surface direction of barrier layer with grid 4, and the
One shielded layer 72 gradually approaches drain electrode 6 from bottom to top with secondary shielding layer 82 from the edge of grid 4.
First screen layer 72 and secondary shielding layer 82 are electrically connected with source electrode 5.For high electron mobility transistor, work as grid
When pole 4 plus negative pressure and drain electrode 6 plus positive pressure, the electric field line of barrier layer 3 is straight immediately below grid, but in grid 4 close to the side of drain electrode 6
At edge, the electric field line on 3 surface of barrier layer is concentrated to 4 edge of grid, under same bias, 3 surface of barrier layer at 4 edge of grid
Peak value electric field is far longer than 4 underface barrier layer of grid, 6 surface peak electric field so that easily sends out on 3 surface of barrier layer at 4 edge of grid
Raw breakdown, as shown in Figure 2.
And positioned at the first screen layer 72 that direction drain electrode 6 extends on grid 4, it can be generated after being electrically connected with source electrode 5 vertical
The electric field on its straight surface, to change the field distribution in the barrier layer 3 at 4 edge of grid so that electric field line concentration degree
It reduces, 3 surface peak electric field of barrier layer is reduced, to improve the breakdown voltage of high electron mobility transistor, such as Fig. 3 institutes
Show.
It therefore, can be by adjusting the thickness of 72 the first passivation layer 71 of lower section of length and first screen layer of first screen layer 72
It spends to optimize the breakdown voltage of high electron mobility transistor.In general, the length of increase first screen layer 72 and reduction by first are blunt
Breakdown voltage can be improved by changing the thickness of layer 71, but when the length of first screen layer 72 is long or the thickness of the first passivation layer 71
Voltage reduction can be caused punch through when spending low instead, while parasitic capacitance can be caused to increase.And positioned at 72 top of first screen layer
Secondary shielding layer 82, overlap in the longitudinal direction compared to first screen layer 72, and the height from barrier layer 3 is passed
Increase, supplement optimization electric field can be played the role of in the case where not increasing by 72 length of first screen layer, reach raising breakdown potential
The effect of pressure, while the parasitic capacitance of high electron mobility transistor will not be increased.
Compared with using the high electron mobility transistor of single shielded layer, in the high electronics of the two-layer screen layer of the present embodiment
In mobility transistor, secondary shielding layer 82 has compared to height of the first screen layer 72 from barrier layer 3 to be incremented by and moves closer to source
Pole 6, do not change source electrode 5 and drain electrode 6 between distance in the case of, can by adjusting first screen layer 72 length, second
This four parameters of the thickness of the length of shielded layer 82, the thickness of the first passivation layer 71 and the second passivation layer 81 are moved to optimize high electronics
The breakdown voltage of shifting rate transistor, that is, can be by reduction close to the length of the first screen layer 72 of grid 4, with the second screen
The length of layer 82 is covered to supplement the effect of optimization electric field, while can improve the first passivation layer positioned at 72 lower section of first screen layer
71 thickness reduces parasitic capacitance.
In addition, compared to the T-type grid structure that shielded layer and grid short circuit are formed, first screen layer and secondary shielding layer are undirected
The part that source electrode extends, thus the parasitic input capacitance C of device will not be increased while improving device electric breakdown strengthgsAnd feedback
Capacitance Cgd。
In one embodiment, as shown in Figure 1, the thickness of the first passivation layer 71 is uniform, which includes position
Half passivation layer of a left side between source electrode 5 and grid 4, half passivation layer of the right side between grid 4 and drain electrode 6 and it is covered in grid
The intermediate passivation layer on 4 surfaces.
And the thickness of first screen layer 72 on the first passivation layer 71 is formed in uniformly and from the upper surface of intermediate passivation layer
The upper surface for extending to right half passivation layer, forms step shape.
In one embodiment, as shown in Figure 1, first screen layer 72 and secondary shielding layer 82 are on barrier layer 3
Projection in surface direction can partly overlap (such as overlapping 0.1um).In addition, throwing of the two on 3 upper surface direction of barrier layer
Shadow can also be completely overlapped or spaced, and spacing distance is less than or equal to 0.2um, is no longer described in detail herein.
The cross sectional shape of secondary shielding layer 82 can be strip (as shown in Figure 1), can also be with first screen layer 72
Shape is identical, is no longer described in detail herein.
In one embodiment, the length L of first screen layer 72SH1With the length L of secondary shielding layer 82SH2To be more than
0.5um;The square resistance of first screen layer 72 and secondary shielding layer 82 is less than 10 Ω.
In another embodiment, high electron mobility transistor can also include more protective layers.It will be appreciated that all
Protective layer stack be arranged source electrode 5 and drain electrode 6 between barrier layer upper surface and be covered on grid 4.Every protective layer
Include passivation layer and form shielded layer on the passivation layer, and the shielded layer in multiple protective layers from the edge of grid 4 under
And upper gradual approach drain electrode 6;Shielded layer and grid 4 positioned at bottom is in the projection on 3 upper surface direction of barrier layer
It is least partially overlapped.Each shielded layer is electrically connected with source electrode 5.
In addition, shielded layer in multiple protective layers can at least portion in the projection on 3 upper surface direction of barrier layer
Divide overlapping, can also be spaced, and spacing distance is less than or equal to 0.2um;The length of each shielded layer be more than 0.5um,
And square resistance resistance value is less than 10 Ω.As shown in figure 4, by taking high electron mobility transistor includes three protective layers as an example, at this
In embodiment, high electron mobility transistor further includes third protective layer other than including structure same as shown in Figure 1.Wherein,
Third protective layer includes third passivation layer 91 and the third shielded layer 92 that is formed on third passivation layer 91.Third shielded layer 92 with
Source electrode 5 is electrically connected, and the gradually approach drain electrode 6 from top to bottom of first screen layer 72, secondary shielding layer 82 and third shielded layer 92.
The preferred embodiment of the disclosure is described in detail above in association with attached drawing, still, the disclosure is not limited to above-mentioned reality
The detail in mode is applied, in the range of the technology design of the disclosure, a variety of letters can be carried out to the technical solution of the disclosure
Monotropic type, these simple variants belong to the protection domain of the disclosure.
It is further to note that specific technical features described in the above specific embodiments, in not lance
In the case of shield, it can be combined by any suitable means.In order to avoid unnecessary repetition, the disclosure to it is various can
The combination of energy no longer separately illustrates.
In addition, arbitrary combination can also be carried out between a variety of different embodiments of the disclosure, as long as it is without prejudice to originally
Disclosed thought equally should be considered as disclosure disclosure of that.
Claims (10)
1. a kind of high electron mobility transistor, which is characterized in that including:Substrate, channel layer, barrier layer, drain electrode, grid, source
Pole and multiple protective layers, the substrate, the channel layer, the barrier layer stack gradually from the bottom to top, the source electrode and institute
It states drain electrode and is respectively formed at the left and right ends of the barrier layer upper surface, the grid is formed in the source electrode and the drain electrode
Between and respectively with the source electrode and the drain space;
The multiple protective layer stacks the upper surface for the barrier layer being arranged between the source electrode and the drain electrode and covering
On the grid;
Each protective layer in the multiple protective layer includes passivation layer and the shielded layer that is formed on the passivation layer, described more
Shielded layer in a protective layer gradually approaches the drain electrode from bottom to top from the edge of the grid;
Positioned at the shielded layer of bottom and the grid perpendicular to barrier layer upper surface direction in the multiple protective layer
On projection it is least partially overlapped.
2. high electron mobility transistor according to claim 1, which is characterized in that bottom in the multiple protective layer
Passivation layer thickness it is uniform;
The passivation layer positioned at bottom includes:Half passivation layer of a left side between the source electrode and the grid is located at institute
It states half passivation layer of the right side between grid and the drain electrode and is covered in the intermediate passivation layer of the gate surface.
3. high electron mobility transistor according to claim 2, which is characterized in that the shielded layer of the bottom is from institute
State intermediate passivation layer upper surface extend to right half passivation layer upper surface and the shielded layer thickness it is uniform.
4. according to claim 3 any one of them high electron mobility transistor, which is characterized in that in the multiple protective layer
Remaining shielded layer shape it is identical as the shape of the shielded layer of the bottom.
5. high electron mobility transistor according to claim 1, which is characterized in that the shielding in the multiple protective layer
Layer is least partially overlapped in the projection on the direction of the barrier layer upper surface.
6. high electron mobility transistor according to claim 1, which is characterized in that the shielding in the multiple protective layer
Spacing distance of the layer between the projection on the direction of the barrier layer upper surface is less than or equal to 0.2um.
7. high electron mobility transistor according to claim 1, which is characterized in that the shielding in the multiple protective layer
Layer is electrically connected with the source electrode respectively.
8. high electron mobility transistor according to claim 1, which is characterized in that the shielding in the multiple protective layer
The length of layer is more than 0.5um.
9. high electron mobility transistor according to claim 1, which is characterized in that the shielding in the multiple protective layer
The square resistance resistance value of layer is less than 10 Ω.
10. high electron mobility transistor according to claim 1, which is characterized in that blunt in the multiple protective layer
The material for changing layer is SiN or SiO2。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710220931.6A CN108695384A (en) | 2017-04-06 | 2017-04-06 | High electron mobility transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710220931.6A CN108695384A (en) | 2017-04-06 | 2017-04-06 | High electron mobility transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108695384A true CN108695384A (en) | 2018-10-23 |
Family
ID=63842750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710220931.6A Withdrawn CN108695384A (en) | 2017-04-06 | 2017-04-06 | High electron mobility transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108695384A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109659366A (en) * | 2018-12-21 | 2019-04-19 | 英诺赛科（珠海）科技有限公司 | High electron mobility transistor and its manufacturing method |
| CN111128893A (en) * | 2019-12-20 | 2020-05-08 | 华虹半导体(无锡)有限公司 | EDMOS manufacturing method based on CMOS double-well process and structure thereof |
-
2017
- 2017-04-06 CN CN201710220931.6A patent/CN108695384A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109659366A (en) * | 2018-12-21 | 2019-04-19 | 英诺赛科（珠海）科技有限公司 | High electron mobility transistor and its manufacturing method |
| CN111684605A (en) * | 2018-12-21 | 2020-09-18 | 英诺赛科（珠海）科技有限公司 | Semiconductor device and method for manufacturing the same |
| US11784237B2 (en) | 2018-12-21 | 2023-10-10 | Innoscience (Zhuhai) Technology Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| CN111684605B (en) * | 2018-12-21 | 2024-03-19 | 英诺赛科（珠海）科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN111128893A (en) * | 2019-12-20 | 2020-05-08 | 华虹半导体(无锡)有限公司 | EDMOS manufacturing method based on CMOS double-well process and structure thereof |
| CN111128893B (en) * | 2019-12-20 | 2022-04-05 | 华虹半导体(无锡)有限公司 | EDMOS manufacturing method based on CMOS double-well process and structure thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9431527B1 (en) | Enhancement mode high electron mobility transistor | |
| JP7017525B2 (en) | Multi-stage surface passivation structure and method for manufacturing it | |
| US11056584B2 (en) | Semiconductor device | |
| CN101320751B (en) | HEMT device and manufacturing method thereof | |
| CN110649096B (en) | High-voltage n-channel HEMT device | |
| US8823061B2 (en) | Semiconductor device | |
| CN104201201B (en) | A kind of adaptive-biased field plate for GaN base HEMT device | |
| EP2321850B1 (en) | LDMOS having a field plate | |
| CN105409007B (en) | Gallium nitride device and its preparation method with reduced output capacitance | |
| CN110660851A (en) | High-voltage n-channel HEMT device | |
| JP2015122361A (en) | Field effect transistor | |
| JP2009253126A (en) | Semiconductor device | |
| CN104916682A (en) | Semiconductor device | |
| US8519442B2 (en) | High electron mobility transistor having a high speed switching function | |
| CN102315262B (en) | Semiconductor device and making method thereof | |
| WO2013027722A1 (en) | Semiconductor device | |
| CN102403349A (en) | III nitride MISHEMT device | |
| CN108695384A (en) | High electron mobility transistor | |
| CN117174756B (en) | SiC MOSFET cell structure with double multilayer shielding structure, device and preparation method | |
| CN104201204B (en) | Manufacture method for transverse symmetrical DMOS (double diffusion metal-oxide-semiconductor) pipe | |
| CN106972060B (en) | Semiconductor power device | |
| CN110649097B (en) | High-voltage p-channel HFET device | |
| CN106373996B (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN110660843A (en) | High-voltage p-channel HEMT device | |
| CN206322705U (en) | A kind of GaN HEMT devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20181023 |
|
| WW01 | Invention patent application withdrawn after publication |