CN218240296U - Aging plate suitable for aging test of ULQ2003 triode array - Google Patents

Abstract

The utility model discloses a be suitable for experimental burn-in board of ULQ2003 triode array burn-in relates to components and parts reliability test technical field, solves the unable big experimental problem of burning-in of realizing ULQ2003 triode array in batches. The aging board comprises a substrate, the substrate is divided into a power interface area and a working area, the power interface area comprises a first power positive terminal VCC, a second power positive terminal VMUX, a multi-path driving signal terminal and a power grounding terminal, the working area comprises m rows and n rows of test units for testing the ULQ2003 triode array, and the test units are connected with the first power positive terminal VCC, the second power positive terminal VMUX, the multi-path driving signal terminal and the power grounding terminal through copper sheet circuits on the top layer and/or the bottom layer of the substrate. Use the utility model discloses can test a plurality of ULQ2003 triode arrays simultaneously under the same experimental biasing circumstances, realize ageing experimental in batches.

Description

Be suitable for ageing board of experimental of ULQ2003 triode array ageing

Technical Field

The utility model relates to an electronic components reliability test technical field especially relates to a be suitable for experimental board of smelting always of ULQ2003 triode array.

Background

The aging test is a method for eliminating early failure products and improving the system reliability in common use in engineering. Certain electric stress is continuously applied to the electronic components in a longer time, various physical and chemical reaction processes in the components are accelerated through the comprehensive action of the electric stress and the thermal stress, various potential defects in the components are promoted to be exposed early, and the aim of removing early failure products is fulfilled.

Burn-in is a non-destructive test that only induces a potentially defective circuit without causing new failure mechanisms or changing its failure distribution after the circuit has been screened as a whole. Only the use reliability of the circuit can be changed through aging tests, but the inherent reliability of the whole circuit cannot be changed, and the selection of test conditions is mainly based on the reliability requirement degree of the circuit and the characteristic of a failure mechanism of the circuit. When the aging test is carried out, the electronic components are placed on the aging plate and placed in the aging box to apply thermal stress and electric stress, so that the early failure of the circuit is stimulated.

The reliability of each component in the same batch of products is different due to various uncertain factors of electronic components produced in batches. The burn-in test has good screening effect on a series of defects possibly existing in the process manufacturing process, such as surface contamination, poor lead welding, channel leakage, silicon wafer cracks, oxide layer defects, local heating pads, secondary breakdown and the like, and can promote the electrical parameters of a defect-free component to be stable, so that the product quality is ensured.

The ULQ2003 triode is a Darlington tube, also called a composite tube, and is formed by properly connecting two triodes together to form an equivalent new triode. This is equivalent to the amplification of a triode being the product of the two. As shown in fig. 1, a schematic diagram of the ULQ2003 triode structure is shown, and two bipolar transistors are connected in a dc coupling manner (two transistors are cascaded) to achieve secondary amplification of current, so that a large current amplification capability can be easily achieved. Because the ULQ2003 triode array is packaged by DIP16, 7 ULQ2003 triodes with consistent parameter performance are packaged in the ULQ2003 triode array, the output current is large, the power dissipation is high, and the packaging form is special, so that the ULQ2003 triode array is difficult to burn in power, the ULQ2003 triode array is always in an open-top test state, and the use reliability of the ULQ2003 triode array device cannot meet the actual requirement.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a be suitable for experimental burn-in board of ULQ2003 triode array burn-in for solve and can't realize carrying out the experimental problem of high temperature anti-inclined to one side burn-in to ULQ2003 triode array device in batches.

In order to achieve the above object, the present invention provides the following technical solutions:

the utility model provides a be suitable for ageing board of test of ageing of ULQ2003 triode array, include: the test device comprises a substrate, wherein the substrate is divided into a power interface area and a working area, the power interface area comprises a first power positive terminal VCC, a second power positive terminal VMUX, a plurality of driving signal terminals and a power grounding terminal, the working area comprises m rows and n columns of test units for the ULQ2003 triode array test, and the test units are connected with the first power positive terminal VCC, the second power positive terminal VMUX, the plurality of driving signal terminals and the power grounding terminal through copper-clad circuits on the top layer and/or the bottom layer of the substrate;

the testing unit comprises a device station with a contact point matched with the ULQ2003 triode array pin, an input load resistor connected between the input pin contact point and a driving signal end, a first output load resistor connected between the output pin contact point and a first power supply positive terminal VCC, a second output load resistor connected between the output pin contact point and a second power supply positive terminal VMUX, and a diode connected between a collector common pin contact point and a second power supply positive terminal VMUX, wherein the ground pin contact point is connected with a power supply grounding terminal, the first power supply positive terminal VCC is connected with the power supply grounding terminal through a first capacitor, and the second power supply positive terminal VMUX is connected with the power supply grounding terminal through a second capacitor.

Preferably, the active area includes 52 test units, i.e. m =4,n =13, and the test units are distributed in an array of 4 rows and 13 columns in the active area. Furthermore, the driving signal terminals are 28 lines, which are divided into 4 groups, and the 7 lines of the driving signal terminals in each group serve as common driving signals to provide driving signals for a row of test units, and are connected with the first pin contact point, the second pin contact point, the third pin contact point, the fourth pin contact point and the seventh pin contact point which correspond to the pins serving as the signal input terminals. Furthermore, the first power supply positive terminal VCC, the second power supply positive terminal VMUX and the power supply ground terminal are respectively divided into 13 discrete copper-clad lines by the number of columns, and each copper-clad line is connected with 4 test units.

Preferably, the number m of rows of the test units ranges from 1 to 5, the number of columns ranges from 4 to 20, and the number of test units ranges from 4 to 100. Furthermore, the number of the driving signal lines is 7 times of m, the driving signal lines are divided into m groups, and the 7 driving signal lines in each group serve as a common driving signal to provide driving signals for a row of test units and are connected with the first pin contact point, the second pin contact point and the seventh pin contact point which correspond to pins serving as signal input ends. Furthermore, the first power supply positive terminal VCC, the second power supply positive terminal VMUX and the power supply ground terminal are respectively divided into n discrete copper-clad lines according to the number of columns, and each copper-clad line is connected with m test units.

Preferably, the temperature resistance of the board of the aging board substrate is more than or equal to 170 ℃. The thickness of the copper sheet circuit is greater than or equal to 70 micrometers, and the value range of the line width is in the range of 10mil to 20 mil. The number of the wiring through holes of each network copper sheet circuit on the substrate is less than or equal to 3, and the wiring distance between adjacent copper sheet circuits is greater than or equal to 0.3mm.

The traditional burn-in board design method can only solve the problem of small-batch device tests, is complex in installation mode and operation method, poor in reliability and not suitable for the requirements of reliability screening and testing of large-batch ULQ2003 triode array devices, so that the existing burn-in test carrier does not have the capability of performing high-temperature reverse-biased burn-in tests on the ULQ2003 triode array devices. Compared with the prior art, the utility model provides a be suitable for ULQ2003 triode array to burn in experimental burn in board design scheme, adopt m to arrange the test unit array overall arrangement that n was listed as, can be simultaneously to 1 to 52, test more test device simultaneously even, improved and burned in the test ability, satisfy the requirement that big batch ULQ2003 triode array carried out the experiment simultaneously under the same experimental condition circumstances, have big batch test ability and satisfy the identity test requirement. The temperature resistance of the base plate of the aging plate is more than or equal to 170 ℃, so that the high-temperature aging test can be realized. Through the reasonable design of the wiring line width and the number of the through holes, the electrical performance of the aging board can be ensured to meet the test requirement.

The utility model discloses a burn and smelt board structural design is reasonable, and actual operation is simple, and the operation is reliable, can realize the nimble reliable burn and smelt experiment that disposes device quantity simultaneously, has improved the test efficiency in the production process of product batch greatly, especially can realize small batch volume, big batch, high reliable, easy operation's ULQ2003 triode array burn and smelt experiment.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

FIG. 1 is a schematic diagram of a ULQ2003 triode configuration;

fig. 2 is a schematic diagram of the high-temperature reverse bias principle of the ULQ2003 triode array device in the embodiment of the present invention;

fig. 3 is a schematic diagram of a top layer design of a burn-in board suitable for a burn-in test of an ULQ2003 triode array according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a burn-in board bottom layer design suitable for a ULQ2003 triode array burn-in test according to an embodiment of the present invention.

Detailed Description

For the convenience of clearly describing the technical scheme of the embodiment of the present invention, in the embodiment of the present invention, words such as "first", "second", etc. are adopted to distinguish the same items or similar items with basically the same function and action. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

At present, no aging board suitable for reliability screening and testing of large-batch ULQ2003 triode array devices exists, and therefore aging tests of the ULQ2003 triode array devices cannot be carried out on large batches. By taking an ULQ2003 triode array as an example, as shown in fig. 2, a schematic diagram of a power aging test principle of the ULQ2003 triode array is given.

In fig. 2, driving signal sources F1 to F7 provide square wave signals to first to seventh pins of the ULQ2003 triode array through input resistors RI1 to RI7, and when the driving signals F1 to F7 are at a high level, base voltages of 7 triodes inside the ULQ2003 triode array are simultaneously high, and corresponding triodes are in a conducting state; when the driving signals F1-F7 are at low level, the base voltages of 7 triodes in the ULQ2003 triode array are simultaneously low, and the triodes are in a cut-off state. The output terminals OUT1 to OUT7 are connected to the power source VCC and the power source VMUX through the corresponding sixteenth to tenth pins via the load resistors RO1 to RO7, respectively.

When the base voltages of 7 triodes in the ULQ2003 triode array are high, the triodes are in a conducting state, and test currents respectively flow through the 7 internal triodes through a power supply VCC, a power supply VMUX and load resistors RO 1-RO 7 and are grounded through an emitter; when the base voltage of 7 triodes in the ULQ2003 triode array is low, the triodes are in a cut-off state, and the 7 internal triodes are in a reverse cut-off state. An eighth pin of the ULQ2003 triode array is grounded, and the ninth pin is used as a common end of collectors of the internal 7 triodes and is connected with a power supply VMUX through a protection diode D1.

A schematic diagram of a suitable ULQ2003 triode array burn-in top layer design is shown in fig. 3. As shown in fig. 4, a schematic diagram of the bottom layer design of the ULQ2003 triode array burn-in board is shown. In fig. 3, a power burn-in test of the 7 triodes in the ULQ2003 triode array is realized by connecting the 7 triodes in the ULQ2003 triode array in parallel through a reasonable circuit design.

It can be seen that the utility model discloses be suitable for ageing experimental mill board of ULQ2003 triode array, include: the test device comprises a substrate, wherein the substrate is divided into a power interface area and a working area, the power interface area comprises a first power positive terminal VCC, a second power positive terminal VMUX, a plurality of driving signal terminals and a power grounding terminal, the working area comprises m rows and n columns of test units for the ULQ2003 triode array test, and the test units are connected with the first power positive terminal VCC, the second power positive terminal VMUX, the plurality of driving signal terminals and the power grounding terminal through copper-clad circuits on the top layer and/or the bottom layer of the substrate;

as can be seen from fig. 2, the test unit includes a device station having a contact point matching with the ULQ2003 triode array pin, an input load resistor connected between the input pin contact point and the driving signal terminal, a first output load resistor connected between the output pin contact point and the first power supply positive terminal VCC, a second output load resistor connected between the output pin contact point and the second power supply positive terminal VMUX, and a diode connected between the collector common pin contact point and the second power supply positive terminal VMUX, the ground pin contact point is connected to the power supply ground terminal, the first power supply positive terminal VCC is connected to the power supply ground terminal through a first capacitor, and the second power supply positive terminal VMUX is connected to the power supply ground terminal through a second capacitor.

Specifically, as shown in fig. 3 and 4, the active area includes 52 test units, i.e., m =4,n =13, and the test units are arranged in an array of 4 rows and 13 columns in the active area. Furthermore, the driving signal terminals are 28 lines, which are divided into 4 groups, and the 7 lines of driving signal lines in each group are used as common driving signals to provide driving signals for a row of test units, and are connected with the first pin contact point, the second pin contact point, the third pin contact point and the fourth pin contact point which are corresponding to the pins used as the signal input terminals. Furthermore, the first power supply positive terminal VCC, the second power supply positive terminal VMUX and the power supply ground terminal are respectively divided into 13 discrete copper clad lines by the number of columns, and each copper clad line is connected with 4 test units.

Furthermore, the range of the row number m of the test units is 1 to 5, the range of the column number is 4 to 20, and the range of the number of the test units is 4 to 100. Furthermore, the number of the driving signal lines is 7 times of m, the driving signal lines are divided into m groups, and the 7 driving signal lines in each group serve as a common driving signal to provide driving signals for a row of test units and are connected with the first pin contact point, the second pin contact point and the seventh pin contact point which correspond to pins serving as signal input ends. Furthermore, the first power supply positive terminal VCC, the second power supply positive terminal VMUX and the power supply ground terminal are respectively divided into n discrete copper-clad lines according to the number of columns, and each copper-clad line is connected with m test units. By flexibly configuring the values of m and n and reasonably designing the wiring, the design of the aging board with various combinations can be realized by referring to fig. 3 and 4.

The temperature resistance of the board of the aging board substrate in the embodiment is more than or equal to 170 ℃. The thickness of the copper sheet circuit is greater than or equal to 70 micrometers, and the value range of the line width is in the range of 10mil to 20 mil. The number of wiring through holes of each network copper-clad circuit on the substrate is less than or equal to 3, and the wiring distance between adjacent copper-clad circuits is greater than or equal to 0.3mm.

The aging board suitable for the ULQ2003 triode array meets the requirement of equipment test capability on one hand, and can realize that 7 triodes in the same ULQ2003 triode array are tested simultaneously under the same test bias condition; on the other hand, the batch burn-in test capability can be realized, 52 test stations are planned and designed for the whole burn-in board, and the batch burn-in test of 1-52 ULQ2003 triode array devices can be realized.

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the present invention has been described in connection with the specific features and embodiments thereof, it is apparent that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A burn-in board suitable for a ULQ2003 triode array burn-in test, comprising: the test device comprises a substrate, wherein the substrate is divided into a power interface area and a working area, the power interface area comprises a first power positive terminal VCC, a second power positive terminal VMUX, a plurality of driving signal terminals and a power grounding terminal, the working area comprises m rows and n columns of test units for the ULQ2003 triode array test, and the test units are connected with the first power positive terminal VCC, the second power positive terminal VMUX, the plurality of driving signal terminals and the power grounding terminal through copper-clad circuits on the top layer and/or the bottom layer of the substrate;

the testing unit comprises a device station with a contact point matched with the ULQ2003 triode array pin, an input load resistor connected between the input pin contact point and a driving signal end, a first output load resistor connected between the output pin contact point and a first power supply positive terminal VCC, a second output load resistor connected between the output pin contact point and a second power supply positive terminal VMUX, and a diode connected between a collector common pin contact point and a second power supply positive terminal VMUX, wherein the ground pin contact point is connected with a power supply grounding end, the first power supply positive terminal VCC is connected with the power supply grounding end through a first capacitor, and the second power supply positive terminal VMUX is connected with the power supply grounding end through a second capacitor.

2. The burn-in board of claim 1, wherein the active area includes 52 test cells, i.e., m =4,n =13, and the test cells are arranged in an array of 4 rows and 13 columns in the active area.

3. The burn-in board of claim 2 wherein said drive signal terminals are 28-way, divided into 4 groups, and the 7 drive signal lines of each group serve as a common drive signal to provide drive signals for a row of test cells connected to corresponding first through seventh pin contacts serving as signal input terminals.

4. The refining plate of claim 2 or 3,

the testing device comprises a first power supply positive terminal VCC, a second power supply positive terminal VMUX and a power supply grounding terminal, wherein the first power supply positive terminal VCC, the second power supply positive terminal VMUX and the power supply grounding terminal are respectively divided into 13 discrete copper-clad lines according to the number of columns, and each copper-clad line is connected with 4 testing units.

5. The aging board of claim 1, wherein the number of rows m of test units ranges from 1 to 5, the number of columns ranges from 4 to 20, and the number of test units ranges from 4 to 100.

6. The refining board of claim 5,

the number of the drive signal lines is 7 times of m, the drive signal lines are divided into m groups, and the 7 drive signal lines in each group serve as common drive signals to provide drive signals for a row of test units and are connected with first pin contact points, second pin contact points and seventh pin contact points corresponding to pins serving as signal input ends.

7. The aging board according to claim 5 or 6,

the testing device comprises a first power supply positive terminal VCC, a second power supply positive terminal VMUX and a power supply grounding terminal, wherein the first power supply positive terminal VCC, the second power supply positive terminal VMUX and the power supply grounding terminal are respectively divided into n paths of discrete copper-clad lines according to the number of columns, and each path of copper-clad line is connected with m testing units.

8. The aging board of claim 7,

the temperature resistance of the board of the aging board substrate is more than or equal to 170 ℃;

the thickness of the copper sheet circuit is greater than or equal to 70 micrometers, and the value range of the line width is in the interval of 10 mils to 20 mils;

the number of wiring through holes of each network copper-clad circuit on the substrate is less than or equal to 3, and the wiring distance between adjacent copper-clad circuits is greater than or equal to 0.3mm.

9. The aging board of claim 4,

the temperature resistance of the board of the aging board substrate is more than or equal to 170 ℃;

the thickness of the copper sheet circuit is greater than or equal to 70 micrometers, and the value range of the line width is in the range of 10mil to 20 mil;

the number of the wiring through holes of each network copper sheet circuit on the substrate is less than or equal to 3, and the wiring distance between adjacent copper sheet circuits is greater than or equal to 0.3mm.

10. The aging board of any one of claims 1, 2 or 5,

the temperature resistance of the board of the aging board substrate is more than or equal to 170 ℃;

the thickness of the copper sheet circuit is greater than or equal to 70 micrometers, and the value range of the line width is in the interval of 10 mils to 20 mils;

the number of the wiring through holes of each network copper sheet circuit on the substrate is less than or equal to 3, and the wiring distance between adjacent copper sheet circuits is greater than or equal to 0.3mm.

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