CN215910592U

CN215910592U - Be suitable for field effect transistor to burn and smelt experimental board of smelting always

Info

Publication number: CN215910592U
Application number: CN202121115053.XU
Authority: CN
Inventors: 左洪涛; 贾民杰; 宁凯; 张凡
Original assignee: CASIC Defense Technology Research and Test Center
Current assignee: CASIC Defense Technology Research and Test Center
Priority date: 2021-05-24
Filing date: 2021-05-24
Publication date: 2022-02-25
Anticipated expiration: 2031-05-24

Abstract

The utility model discloses a burn-in board suitable for a field effect transistor burn-in test, relates to the technical field of component reliability tests, and solves the problem that the high-temperature reverse-biased burn-in test of field effect transistors cannot be realized in a large scale. The aging board comprises a substrate, the substrate is divided into a power interface area and a working area, the power interface area comprises a power positive end and a power negative end, the working area comprises m rows of n rows of test units used for testing field effect tubes, each test unit comprises a protective tube and a device station matched with the base pins of the field effect tubes, each device station comprises a grid contact, a drain contact and a source contact, the power positive end is electrically connected with the drain contact through the protective tube, and the power negative end is in short circuit connection with the grid contact and the source contact. The aging plate of the utility model has reasonable structure design and can realize reliable high-temperature reverse-biased aging test of any number of devices between 1 and 80 devices.

Description

Be suitable for field effect transistor to burn and smelt experimental board of smelting always

Technical Field

The utility model relates to the technical field of reliability testing of electronic components, in particular to a burn-in board suitable for a field effect transistor burn-in test.

Background

The aging test is a method for eliminating early failure products and improving the system reliability in common use in engineering. Certain electric stress is continuously applied to the electronic components in a longer time, various physical and chemical reaction processes in the components are accelerated through the comprehensive action of the electric stress and the thermal stress, various potential defects in the components are promoted to be exposed early, and the aim of removing early failure products is fulfilled.

Burn-in is a non-destructive test that only induces a potentially defective circuit without causing new failure mechanisms or changing its failure distribution after the circuit has been screened as a whole. Only the use reliability of the circuit can be changed through aging tests, but the inherent reliability of the whole circuit cannot be changed, and the test conditions are mainly selected according to the reliability requirement degree of the circuit and the characteristics of a failure mechanism of the circuit. When the aging test is carried out, the electronic components are placed on the aging plate and placed in the aging box to apply thermal stress and electric stress, so that the early failure of the circuit is stimulated.

The reliability of each component in the same batch of products is different due to various uncertain factors of electronic components produced in batches. The burn-in test has good screening effect on a series of defects possibly existing in the process manufacturing process, such as surface contamination, poor lead welding, channel leakage, silicon wafer cracks, oxide layer defects, local heating pads, secondary breakdown and the like, and can promote the electrical parameters of a defect-free component to be stable, so that the product quality is ensured.

Among the common chip Package formats, DIP Package (Dual In-line Package), also called Dual In-line Package technology, refers to an integrated circuit chip packaged In a Dual In-line format. The SOP (Small Out-Line Package) is an element Package form, and is also a very common surface mount Package technology, pins are led Out from two sides of the Package to form a gull wing shape (L shape), and the Package material mainly includes two types of plastics and ceramics. DIP packages and SOP packages differ in that DIP is an in-line package and SOP is a patch package. Both are widely used in the design of electronic circuit production. The SOP-8 package has 8 pins more suitable for patch production in production distribution.

The high-temperature reverse-biased aging test can shorten the early failure time of the device, can fully expose most failure mechanisms of the device, and is an effective measure for improving the use reliability of the device. Because the IRF7811 field effect transistor adopts SOP-8 encapsulation, 1N-MOS field effect transistor is encapsulated inside the IRF7811 field effect transistor, and a mode that a plurality of leading-out terminals (8 pins) are connected in parallel is adopted. As shown in fig. 1, a schematic diagram of an IRF7811 fet pin array structure is given. No. 1 to No. 3 pins of the IRF7811 field effect transistor correspond to a source electrode (S end) inside the field effect transistor, No. 4 pins correspond to a grid electrode (G end) inside the field effect transistor, and No. 5 to No. 8 pins correspond to a drain electrode (D end) inside the field effect transistor.

The high-temperature reverse-biased aging test needs to be carried out at a high temperature, and the encapsulation form of the IRF7811 field effect tube device is special, so that the high-temperature reverse-biased aging test of the IRF7811 field effect tube device is difficult, the IRF7811 field effect tube device is always in an incomplete test state, and the use reliability of the device cannot meet the actual requirement. The existing aging test carrier can only carry out small-batch aging test, and an aging plate suitable for screening and testing the reliability of field effect tube devices in large batch does not exist at present, so that high-temperature reverse bias test on the field effect tube devices in large batch cannot be realized.

SUMMERY OF THE UTILITY MODEL

The utility model aims to provide a burn-in board suitable for a field effect tube burn-in test, which is used for solving the problem that the field effect tube device can not be subjected to a high-temperature reverse-biased burn-in test in a large scale.

In order to achieve the above purpose, the utility model provides the following technical scheme:

the application provides a be suitable for field effect transistor to smelt experimental mill and smelt board includes: the device comprises a substrate, wherein the substrate is divided into a power interface area and a working area, the power interface area comprises a power positive end and a power negative end, the working area comprises m rows of n rows of test units for testing field effect tubes, and the test units are connected in parallel between the power positive end and the power negative end through copper sheet circuits on the top layer and/or the bottom layer of the substrate;

the testing unit comprises a protective tube and a device station matched with a base pin of the field effect tube, the device station comprises a grid contact, a drain contact and a source contact, the positive end of the power supply is electrically connected with the drain contact through the protective tube, and the negative end of the power supply is in short circuit connection with the grid contact and the source contact.

Preferably, the working area comprises 40 test units, i.e. m is 4 and n is 10, and the test units are distributed in an array of 4 rows and 10 columns in the working area. And the positive end of the power supply is respectively connected with the 4 rows of test units through 4 copper sheet circuits on the top layer of the substrate and is connected with the protective tubes in 10 test units in each row.

Furthermore, each test unit comprises 2 device stations, the negative end of the power supply is in short-circuit connection with the drain contact and the source contact through 40 discrete copper sheet circuits on the top layer of the substrate, and each row of test units is distributed with 5 copper sheet circuits; and the negative end of the power supply is in short-circuit connection with the drain contact and the source contact through 40 discrete copper circuits on the bottom layer of the substrate, wherein each row of test units is distributed with 5 copper circuits.

Preferably, the number of rows m in the working area ranges from 1 to 5, the number of columns n ranges from 1 to 16, and the number of test units ranges from 1 to 80.

Further, the working area comprises 30 test units, namely m is 3, n is 10, and the test units are distributed in an array of 3 rows and 10 columns in the working area.

Further, the working area comprises 30 test units, namely m is 2, n is 15, and the test units are distributed in an array with 2 rows and 15 columns in the working area.

Preferably, the temperature resistance of the board of the aging board substrate is greater than or equal to 170 ℃.

Preferably, the field effect transistor is an IRFR120N field effect transistor.

Preferably, the thickness of the copper sheet circuit is greater than or equal to 70 micrometers, and the line width ranges from 10 mils to 20 mils; the number of wiring through holes of each network copper-clad circuit on the substrate is less than or equal to 3, and the wiring distance between adjacent copper-clad circuits is greater than or equal to 0.3 mm.

The traditional burn-in board design method can only solve the problem of very small batch of device tests, is complex in installation mode and operation method and poor in reliability, and is not suitable for the requirements of reliability screening and testing of large batch of field effect devices, so that the existing burn-in test carrier does not have the capability of performing high-temperature reverse-biased burn-in tests on the field effect devices.

Compared with the prior art, in the aging board design scheme suitable for the aging test of the field effect transistor, the test unit array layout with m rows and n columns is adopted, a plurality of test devices can be tested in batches at the same time, the aging test capability is improved, the requirement that a large batch of field effect transistors are tested at the same time under the same test condition is met, and the aging board has the large batch test capability and meets the requirement of the same test. The temperature resistance of the base plate of the aging plate is more than or equal to 170 ℃, so that the aging test of high-temperature reverse deflection can be realized. By reasonably designing the wiring line width and the number of the through holes, the electrical performance of the aging board can be ensured to meet the test requirement. The aging plate is reasonable in structure design, has 40 testing units and 80 device stations, is simple in actual operation and reliable in operation, can realize reliable high-temperature reverse-bias tests of any number of devices between 1 and 80 devices, greatly improves the test efficiency in the production process of product batches, and particularly can realize IRF7811 field effect high-temperature reverse-bias aging tests which are small in batch, large in batch, high in reliability and simple in operation.

Drawings

The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model and not to limit the utility model. In the drawings:

FIG. 1 is a schematic structural diagram of an IRF7811 field effect transistor;

FIG. 2 is a schematic diagram of the high temperature reverse bias principle of an IRF7811 FET in an embodiment of the present invention;

FIG. 3 is a schematic diagram of a top layer design of a burn-in board suitable for a field effect transistor burn-in test in an embodiment of the present invention;

FIG. 4 is a schematic diagram of a burn-in board bottom layer design suitable for a field effect transistor burn-in test in an embodiment of the present invention.

Detailed Description

In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

Taking the IRF7811 fet as an example, as shown in fig. 2, a schematic diagram of the high temperature reverse bias principle of the IRF7811 fet is given. The power supply Vc is a test power supply configured for the equipment corresponding to the aging board and is responsible for providing test bias voltage for the IRF7811 field effect transistor high-temperature reverse bias test. The positive end of a power supply Vc is simultaneously applied to pins 5 to 8 of a drain electrode (D end) inside the corresponding IRF7811 field effect tube device through a protective tube, the negative end of the power supply Vc is simultaneously applied to pins 1 to 3 of an inner source electrode (S end) of the corresponding IRF7811 field effect tube and a pin 4 of an inner grid electrode (G end) of the corresponding IRF7811 field effect tube, and short-circuit connection of the pins 1 to 4 of the IRF7811 field effect tube is ensured simultaneously. In fig. 2, the reliable short circuit of the No. 1 to No. 4 pins and the No. 5 to No. 8 pins of the IRF7811 field effect transistor is ensured through circuit design, and the IRF7811 field effect transistor is connected with a test bias power supply Vc, so that the high-temperature reverse bias test of the IRF7811 field effect transistor can be realized.

As shown in fig. 3, a schematic diagram of a burn-in top design suitable for a fet burn-in test is shown. As shown in fig. 4, a schematic diagram of a burn-in board bottom layer design suitable for a fet burn-in test is shown.

It can be seen that the burn-in board for the field effect transistor burn-in test of the present application comprises: the device comprises a substrate, wherein the substrate is divided into a power interface area and a working area, the power interface area comprises a power positive end and a power negative end, the working area comprises m rows of n rows of test units for testing field effect tubes, and the test units are connected in parallel between the power positive end and the power negative end through copper sheet circuits on the top layer and/or the bottom layer of the substrate;

Based on the test circuit in fig. 2, fig. 3 and fig. 4 show a preferred design, where the active area includes 40 test units, i.e., m is 4 and n is 10, and the test units are arranged in an array of 4 rows and 10 columns in the active area. And the positive end of the power supply is respectively connected with the 4 rows of test units through 4 copper sheet circuits on the top layer of the substrate and is connected with the protective tubes in 10 test units in each row.

Each test unit comprises 2 device stations, the negative end of the power supply is in short-circuit connection with the drain contact and the source contact through 40 discrete copper circuits on the top layer of the substrate, and each row of test units is distributed with 5 copper circuits; and the negative end of the power supply is in short-circuit connection with the drain contact and the source contact through 40 discrete copper circuits on the bottom layer of the substrate, wherein each row of test units is distributed with 5 copper circuits.

Based on the design schemes shown in fig. 3 and 4, the test unit array arrangement of the substrate working area can be adjusted by combining with the test requirements, the value range of the row number m in the working area is 1 to 5, the value range of the column number n is 1 to 16, and the value range of the number of the test units is 1 to 80.

For example, the working area includes 30 test units, i.e., m is 3, and n is 10, and the test units are arranged in an array of 3 rows and 10 columns in the working area.

For example, the working area includes 30 test units, i.e., m is 2, and n is 15, and the test units are arranged in an array of 2 rows and 15 columns in the working area.

In order to adapt to a high-temperature test, the temperature resistance of the plate of the aging plate substrate is more than or equal to 170 ℃. In order to ensure the test quality, on one hand, reliable electric connection is ensured, and enough power supply is provided, the thickness of the copper clad circuit is greater than or equal to 70 micrometers, and the line width is in a range from 10 mils to 20 mils; on the other hand, the high-quality electric isolation between copper foil circuits is ensured, the number of wiring through holes of each network copper foil circuit on the substrate is less than or equal to 3, and the wiring distance between adjacent copper foil circuits is greater than or equal to 0.3 mm.

Preferably, the field effect transistor is an IRF7811 field effect transistor. The technical scheme of the aging board is not limited to the IRF7811 field effect transistor, but also applicable to other field effect transistors with similar packaging structures and pin designs, including but not limited to the improved series devices of the IRF7811 field effect transistor.

The aging plate of the utility model has reasonable structure design, simple practical operation and reliable operation, can realize reliable high-temperature back-bias test of any number of devices between 1 and 80 devices, greatly improves the test efficiency in the production process of product batches, and particularly can realize IRF7811 field effect high-temperature back-bias test with small batch, large batch, high reliability and simple operation.

While the utility model has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

While the utility model has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the utility model. Accordingly, the specification and figures are merely exemplary of the utility model as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the utility model. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the utility model. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A be suitable for field effect transistor burn-in board of experimental burn-in, its characterized in that includes: the device comprises a substrate, wherein the substrate is divided into a power interface area and a working area, the power interface area comprises a power positive end and a power negative end, the working area comprises m rows of n rows of test units for testing field effect tubes, and the test units are connected in parallel between the power positive end and the power negative end through copper sheet circuits on the top layer and/or the bottom layer of the substrate;

2. The millboard of claim 1, wherein the work area comprises 40 test units, i.e., m-4 and n-10, which are arranged in an array of 4 rows and 10 columns in the work area.

3. The aging board of claim 2, wherein the positive power terminal is connected to the 4 rows of test units through 4 copper traces on the top layer of the substrate, and is connected to the fuse tubes in 10 test units in each row.

4. The burn-in board of claim 3, wherein each of said test cells includes 2 device sites, and said negative power terminal is short-circuited to said drain and source contacts by 40 discrete copper traces on the top substrate layer, wherein 5 copper traces are assigned to each row of test cells; and the negative end of the power supply is in short-circuit connection with the drain contact and the source contact through 40 discrete copper circuits on the bottom layer of the substrate, wherein each row of test units is distributed with 5 copper circuits.

5. The aging board of claim 1, wherein the number of rows m in the working area ranges from 1 to 5, the number of columns n ranges from 1 to 16, and the number of test units ranges from 1 to 80.

6. The millboard of claim 5, wherein the work area comprises 30 test units, i.e., m-3 and n-10, which are arranged in an array of 3 rows and 10 columns in the work area.

7. The millboard of claim 5, wherein the work area comprises 30 test units, i.e., m-2 and n-15, which are arranged in an array of 2 rows and 15 columns in the work area.

8. The millboard of any of claims 1 to 7, wherein the sheet temperature resistance of the millboard substrate is greater than or equal to 170 degrees Celsius.

9. The millboard of claim 8, wherein the field effect transistor is an IRFR120N field effect transistor.

10. The refining board of claim 9,

the thickness of the copper sheet circuit is greater than or equal to 70 micrometers, and the value range of the line width is in the range of 10mil to 20 mil;

the number of wiring through holes of each network copper-clad circuit on the substrate is less than or equal to 3, and the wiring distance between adjacent copper-clad circuits is greater than or equal to 0.3 mm.