CN216117883U - Bias test board - Google Patents
Bias test board Download PDFInfo
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- CN216117883U CN216117883U CN202122616476.6U CN202122616476U CN216117883U CN 216117883 U CN216117883 U CN 216117883U CN 202122616476 U CN202122616476 U CN 202122616476U CN 216117883 U CN216117883 U CN 216117883U
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- microstrip line
- contact point
- fuse
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- binding post
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Abstract
The utility model provides a bias test board which comprises a plurality of stations, a first binding post, a second binding post, a third binding post, a first microstrip line, a second microstrip line and a third microstrip line, wherein the stations are arranged in an array; each station is provided with a first fixed resistor, a first fast fuse, a second fixed resistor, a second fast fuse, a first source contact point, a first drain contact point, a first grid contact point, a second source contact point, a second drain contact point and a second grid contact point which are longitudinally arranged; the first source contact, the first drain contact, the second source contact and the second drain contact are all connected to the first microstrip line. The utility model can integrally check the double-core combined-sealing type power MOSFET module and has high checking efficiency.
Description
Technical Field
The utility model relates to the field of semiconductor testing, in particular to a bias test board.
Background
The power MOSFET module (double-core sealing, LMOS chip and HMOS chip sealing) is called module for short, two types of power MOSFET chips with the same or different specifications are integrated in the module, and the power MOSFET module has wide application in power management systems such as photovoltaic or wind power. In order to ensure the reliability of module application, two internal chips need to be checked during module check. The existing test board for bias assessment of the power MOSFET chip is commonly a three-hole mounting seat externally connected with two power interfaces and 80 stations. Three holes of the mounting seat are respectively butted with a G grid electrode, a D drain electrode and an S source electrode, G and D, S (DS short circuit during grid electrode bias) or D and G, S (GS short circuit during reverse bias) are butted in two power interface boards, a positive stage and a negative stage of an external power supply are connected, and 80 stations can ensure that the bias test of at most 60-80 devices under the same bias condition can be executed at one time, but the bias test is only limited to a single-core device. The adopted bias test assessment method comprises the following steps: the LMOS chip and the HMOS chip in the module are respectively placed in two bias test boards, and different voltages are applied by two different power supplies (which may be the same) for examination. This way of assessment has the following drawbacks: 1. only one chip is examined each time, and the practical application environment including heat dissipation, power consumption and the like cannot be accurately simulated; 2. the same board examination cannot be carried out, and the consistency of module examination is influenced; 3. each bias test project is added with one check, and the same HTGB project needs to do the module twice; 4. the checking plate is added, the checking efficiency is lower, and the productivity utilization rate is not high. Therefore, the two chips in the current module work independently or in a matching mode, but the application design characteristics of the integrated examination leading-out terminal are not provided, so that the current universal power MOSFET chip bias test board cannot be efficiently adapted to the type of module test examination during power-on examination of bias tests and the like, the LMOS chip and the HMOS chip in the module must be examined respectively, and the examination efficiency, the capacity release and the accuracy of test simulation examination are greatly influenced.
Therefore, how to integrally evaluate the dual-core combined-package type power MOSFET module has become one of the problems to be solved urgently by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, the present invention provides a bias test board for solving the problem that the dual-core seal-type power MOSFET module in the prior art cannot be integrally examined.
To achieve the above and other related objects, the present invention provides an offset test plate comprising: the device comprises a plurality of stations, a first binding post, a second binding post, a third binding post, a first microstrip line, a second microstrip line and a third microstrip line which are arranged in an array;
each station is provided with a first fixed resistor, a first fast fuse, a second fixed resistor, a second fast fuse, a first source contact point, a first drain contact point, a first grid contact point, a second source contact point, a second drain contact point and a second grid contact point which are longitudinally arranged;
the first source contact, the first drain contact, the second source contact and the second drain contact are all connected to a first microstrip line;
the first microstrip line is connected with a first external power supply end through the first binding post;
the first grid contact point is connected to the second microstrip line sequentially through the first fixed resistor and the first fast fuse;
the second microstrip line is connected with a second external power supply end through the second binding post;
the second grid contact point is connected to the third microstrip line sequentially through the second fixed resistor and the second fast fuse;
the third microstrip line is connected with a third external power supply end through the third binding post.
An offset test plate comprising: the device comprises a plurality of stations, a first binding post, a second binding post, a third binding post, a first microstrip line, a second microstrip line and a third microstrip line which are arranged in an array;
each station is provided with a first fixed resistor, a first fast fuse, a second fixed resistor, a second fast fuse, a first source contact point, a first grid contact point, a first drain contact point, a second source contact point, a second grid contact point and a second drain contact point which are longitudinally arranged;
the first source contact, the first gate contact, the second source contact and the second gate contact are all connected to a first microstrip line;
the first microstrip line is connected with a first external power supply end through the first binding post;
the first grid contact point is connected to the second microstrip line sequentially through the first fixed resistor and the first fast fuse;
the second microstrip line is connected with a second external power supply end through the second binding post;
the second grid contact point is connected to the third microstrip line sequentially through the second fixed resistor and the second fast fuse;
the third microstrip line is connected with a third external power supply end through a third binding post.
Optionally, the array comprises 3 rows and 15 columns.
Optionally, the first fast fuse and the second fast fuse are taken out through a fuse puller.
Optionally, the blowing current of the first fast fuse and the second fast fuse is 100 mA.
Optionally, the first fast fuse and the second fast fuse are packaged by using ceramic.
Optionally, bases of the first and second fast fuses are gold plated.
Optionally, the surface of the bias test plate is provided with an insulating layer.
Optionally, the surface of the bias test plate is provided with a three-proofing coating.
As described above, the offset test plate of the present invention has the following advantageous effects:
the bias test board is suitable for bias test integrated assessment projects of the double-core combined-sealing type power MOSFET module, and is high in assessment efficiency and high in productivity utilization rate.
2, the bias test board can relatively accurately simulate the application environment of the dual-core combined-sealing type power MOSFET module.
3, the bias test board can save the using amount of the bias test board of the dual-core combined-sealing type power MOSFET module.
4, the bias test plate can be completely matched with the current test box on the basis of unchanged plate volume size of the current test plate.
Drawings
Fig. 1 shows a schematic diagram of the station structure of the present invention.
FIG. 2 is a schematic diagram of an offset test plate structure according to the present invention.
Description of the element reference numerals
1 first terminal
2 second terminal
3 third terminal
4 first source contact
5 first drain contact
6 first gate contact
7 second source contact
8 second drain contact
9 second gate contact
10 first fast fuse
11 second fast fuse
12 first microstrip line
13 second microstrip line
14 third microstrip line
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The utility model is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The embodiment provides a bias test board, which includes a plurality of stations arranged in an array, a first terminal 1, a second terminal 2, a third terminal 3, a first microstrip line 12, a second microstrip line 13, and a third microstrip line 14.
As shown in fig. 2, in the present embodiment, a high temperature gate test (HTGB) test board is taken as an example, and during practical examination, the positions of the drain contact points or the gate contact points are changed or the connection relationship between the source and the drain is adjusted according to the requirement, which is not described herein. The stations are arranged in an array of 3 rows and 15 columns. It should be noted that the existing common power MOSFET chip offset test board has 80 stations, and the utility model has at most 45 stations to completely match the existing test box on the premise that the sizes of the at most 80 stations of the existing test board are not changed. In actual production, the required number of stations can be set according to the size of a specific test board, and the method is not limited to the embodiment.
Specifically, as shown in fig. 1, a schematic structural diagram of any one station of the present invention is provided, and the station is longitudinally provided with a first source contact 4, a first drain contact 5, a first gate contact 6, a second source contact 7, a second drain contact 8, and a second gate contact 9. The station is also provided with a first fixed resistor R1, a first fast fuse 10, a second fixed resistor R2 and a second fast fuse 11.
It should be noted that the longitudinal arrangement of the first source contact 4, the first drain contact 5, the first gate contact 6, the second source contact 7, the second drain contact 8, and the second gate contact 9 in the present invention means that the arrangement of the six contacts is longitudinal, and the arrangement order of the contacts is not limited, and can be adjusted as needed. For example, the first contact point disposed in the vertical direction is a first gate contact point, the second contact point is a first drain contact point, the third contact point is a first source contact point, the fourth contact point is a second gate contact point, the fifth contact point is a second drain contact point, and the sixth contact point is a second source contact point, which is not limited in this embodiment.
Specifically, in the present embodiment, taking gate bias as an example, the first source contact 4, the first drain contact 5, the second source contact 7 and the second drain contact 8 are all connected to the first microstrip line 12. The first microstrip line 12 of each station is connected to the first terminal 1, and is connected to a first external power source terminal through the first terminal 1.
Specifically, the first gate contact 6 is connected to the second microstrip line 13 through the first fixed resistor R1 and the first fast fuse 10 in sequence. The second microstrip lines 13 of all the stations are connected together to the second binding post 2, and are connected with a second external power supply end through the second binding post 2.
Specifically, the second gate contact 9 is connected to the third microstrip line 14 through the second fixed resistor R2 and the second fast fuse 11 in sequence. The third microstrip lines 14 of all the stations are connected together to the third terminal 3, and are connected to a third external power source through the third terminal 3.
More specifically, the first fast fuse 10 and the second fast fuse 11 are used for overcurrent protection, and can be taken out through a fuse puller, so as to achieve the purpose of replacement.
More specifically, the blowing current of the first fast fuse 10 and the second fast fuse 11 is 100mA, and fast fuses with other blowing currents may be selected according to actual needs, which is not limited to this embodiment.
As another example of the present invention, the first fast fuse 10 and the second fast fuse 11 are packaged by ceramic, and will not explode in case of an overcurrent extreme, which is safer.
As another example of the present invention, the bases of the first and second fast fuses 10 and 11 are plated with gold, so that the passing current can be reduced, the transmitted current is stable, and the transmission is accurate.
As shown in fig. 2, in this embodiment, the first terminal 1(PS-) is connected to the negative electrodes (ground) of the first external power source and the second external power source, the second terminal 2 is connected to the positive electrode of the first external power source, and the third terminal 3(PS +) is connected to the positive electrode of the second external power source, so that the two MOS transistors are powered on simultaneously and examined simultaneously. In actual work, the anode and the cathode of the power supply can be exchanged according to needs, which is not described herein.
Specifically, the surface of the bias test board is provided with the insulating layer, so that the insulating degree is increased, and the safety is improved.
As another example of the utility model, the surface of the bias test plate is provided with a three-proofing coating which can resist moisture, salt mist and mildew.
According to the bias test board, the first source electrode contact point, the first drain electrode contact point and the first grid electrode contact point are welded with the first MOS tube, the second source electrode contact point, the second drain electrode contact point and the second grid electrode contact point are welded with the second MOS tube, the two MOS tubes are integrated on one station, and the first wiring terminal 1, the second wiring terminal 2 and the third wiring terminal 3 are connected with an external power supply, so that the bias test can be integrated, the check efficiency is high, and the productivity and the utilization rate are high. Because two MOS pipes can be examined simultaneously in this real novel type, and then the applied environment of the class power MOSFET module is sealed to two cores of simulation that can be relatively accurate. Compared with the existing bias test board, the two MOS tubes cannot be simultaneously examined at one time, and the bias test board of the dual-core closed-package type power MOSFET module is reduced in dosage as long as the test board needs to be separately placed and examined.
Example two
The present embodiment provides a bias test board, which is different from the first embodiment in that the present embodiment is a structural connection manner of a reverse bias test, and the first source contact 4, the first gate contact 6, the second source contact 7, and the second gate contact 9 are all connected to a first microstrip line; the first microstrip line 12 is connected to the first terminal 1, and is connected to an external power supply through the first terminal 1; the first gate contact 6 is connected to the second microstrip line 13 through the first fixed resistor R1 and the first fast fuse 10 in sequence; the second microstrip line 13 is connected to the second terminal 2, and is connected to an external power supply through the second terminal 2; the second gate contact 9 is connected to the third microstrip line 14 through the second fixed resistor R2 and the second fast fuse 11 in sequence; the third microstrip line 14 is connected to the third terminal 3, and is connected to an external power supply through the third terminal 3.
It should be noted that the other features of the structure, the principle, and the like are similar to those of the first embodiment, and are not repeated herein.
In summary, the present invention provides a bias test board, which includes a plurality of stations arranged in an array, a first terminal, a second terminal, a third terminal, a first microstrip line, a second microstrip line, and a third microstrip line; each station is provided with a first fixed resistor, a first fast fuse, a second fixed resistor, a second fast fuse, a first source contact point, a first drain contact point, a first grid contact point, a second source contact point, a second drain contact point and a second grid contact point which are longitudinally arranged; the first source contact, the first drain contact, the second source contact and the second drain contact are all connected to a first microstrip line; the first microstrip line is connected with a first external power supply end through the first binding post; the first grid contact point is connected to the second microstrip line sequentially through the first fixed resistor and the first fast fuse; the second microstrip line is connected with a second external power supply end through the second binding post; the second grid contact point is connected to the third microstrip line sequentially through the second fixed resistor and the second fast fuse; the third microstrip line is connected with a third external power supply end through a third binding post. The bias test board can be used for simultaneously checking two types of MOS (metal oxide semiconductor) tubes, and is high in checking efficiency and high in productivity utilization rate. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the utility model. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. An offset test plate, comprising at least: the device comprises a plurality of stations, a first binding post, a second binding post, a third binding post, a first microstrip line, a second microstrip line and a third microstrip line which are arranged in an array;
each station is provided with a first fixed resistor, a first fast fuse, a second fixed resistor, a second fast fuse, a first source contact point, a first drain contact point, a first grid contact point, a second source contact point, a second drain contact point and a second grid contact point which are longitudinally arranged;
the first source contact, the first drain contact, the second source contact and the second drain contact are all connected to the first microstrip line;
the first microstrip line is connected with a first external power supply end through the first binding post;
the first grid contact point is connected to the second microstrip line sequentially through the first fixed resistor and the first fast fuse;
the second microstrip line is connected with a second external power supply end through the second binding post;
the second grid contact point is connected to the third microstrip line sequentially through the second fixed resistor and the second fast fuse;
the third microstrip line is connected with a third external power supply end through the third binding post.
2. An offset test plate, comprising at least: the device comprises a plurality of stations, a first binding post, a second binding post, a third binding post, a first microstrip line, a second microstrip line and a third microstrip line which are arranged in an array;
each station is provided with a first fixed resistor, a first fast fuse, a second fixed resistor, a second fast fuse, a first source contact point, a first grid contact point, a first drain contact point, a second source contact point, a second grid contact point and a second drain contact point which are longitudinally arranged;
the first source contact, the first gate contact, the second source contact and the second gate contact are all connected to a first microstrip line;
the first microstrip line is connected with a first external power supply end through the first binding post;
the first grid contact point is connected to the second microstrip line sequentially through the first fixed resistor and the first fast fuse;
the second microstrip line is connected with a second external power supply end through the second binding post;
the second grid contact point is connected to the third microstrip line sequentially through the second fixed resistor and the second fast fuse;
the third microstrip line is connected with a third external power supply end through the third binding post.
3. The bias test plate according to claim 1 or 2, wherein: the array comprises 3 rows and 15 columns.
4. The bias test plate according to claim 1 or 2, wherein: the first fast-melting fuse and the second fast-melting fuse are taken out through a fuse puller.
5. The bias test plate according to claim 1 or 2, wherein: the fusing current of the first fast fusing fuse and the second fast fusing fuse is 100 mA.
6. The bias test plate according to claim 1 or 2, wherein: the first fast fuse and the second fast fuse are packaged by ceramic.
7. The bias test plate according to claim 1 or 2, wherein: and bases of the first fast melting fuse and the second fast melting fuse are plated with gold.
8. The bias test plate according to claim 1 or 2, wherein: the surface of the bias test board is provided with an insulating layer.
9. The bias test plate according to claim 1 or 2, wherein: and a three-proofing coating is arranged on the surface of the bias test plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122616476.6U CN216117883U (en) | 2021-10-27 | 2021-10-27 | Bias test board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122616476.6U CN216117883U (en) | 2021-10-27 | 2021-10-27 | Bias test board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216117883U true CN216117883U (en) | 2022-03-22 |
Family
ID=80710650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122616476.6U Active CN216117883U (en) | 2021-10-27 | 2021-10-27 | Bias test board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216117883U (en) |
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2021
- 2021-10-27 CN CN202122616476.6U patent/CN216117883U/en active Active
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