CN101769964A - Method, device and system for testing conducting resistance of packaged field-effect tube - Google Patents
Method, device and system for testing conducting resistance of packaged field-effect tube Download PDFInfo
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- CN101769964A CN101769964A CN200810247313A CN200810247313A CN101769964A CN 101769964 A CN101769964 A CN 101769964A CN 200810247313 A CN200810247313 A CN 200810247313A CN 200810247313 A CN200810247313 A CN 200810247313A CN 101769964 A CN101769964 A CN 101769964A
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Abstract
The invention discloses a method, a device and a system for testing the conducting resistance of a packaged field-effect tube. The method comprises the following steps of: respectively connecting a drain electrode of a packaged field-effect tube and a voltmeter and an anode of a constant current power supply by a first contact shrapnel and a second contact shrapnel of the test socket and respectively connecting a source electrode of the packaged field-effect tube and the voltmeter and a cathode of the constant current power supply by a third contact shrapnel and a fourth contact shrapnel of the test socket; and confirming the conducting resistance of the field-effect tube according to a voltage value output by the voltmeter and a current value output by the constant current power supply. Based on technical scheme provided by the embodiment of the invention, the conducting resistance of the tested field-effect tube can be accurately tested according to the voltage value output by the voltmeter and the current value output by the constant current power supply.
Description
Technical field
The present invention relates to the semiconductor assembly and test technical field, relate in particular to method, the Apparatus and system of the conducting resistance of the field effect transistor after the test package.
Background technology
At MOS (Metal-Oxide Semiconductor, complementary metal oxide semiconductor (CMOS), also claim insulated-gate type) FET (Field Effect Transistor, field effect transistor) in the device, conducting resistance after the device package (representing with RDS in the following narration) is as one of key characteristic parameter of weighing device, RDS is more little, and the switch power consumption is low more.
At present, RDS after the test MOS FET device package IC (IntegratedCircuit that adopt as shown in Figure 1 more, integrated circuit) socket, by drain electrode (D) end of this socket at test package pipe (i.e. MOS FET device after the encapsulation), source electrode (S) end and grid (G) are drawn a lead respectively, the lead that the D end is drawn links to each other with the positive pole of constant current source, the lead that the S end is drawn links to each other with the negative pole of constant current source, and at constant current source two ends shunt voltage table, specifically as shown in Figure 2, according to circuit diagram shown in Figure 2, apply certain gate source voltage VGS, the ratio of the voltage that voltage table is measured and the electric current of constant current source output is defined as the conducting resistance after the MOS FET device package.
In actual test process, according to annexation shown in Figure 2, be about the hundreds of milliohm by the lead resistance that connects the lead introducing, pin by package tube is connected about tens milliohms of introducing of contact resistance with IC socket contact flat spring, therefore, the equivalent circuit diagram of above-mentioned Fig. 2 correspondence as shown in Figure 3, wherein, R1 is the lead resistance between D end and the constant current source IS and the equivalent resistance of contact resistance sum, R2 is the lead resistance between S end and the constant current source IS and the equivalent resistance of contact resistance sum, as seen from Figure 3, utilize the ratio of voltage VDS that voltage table measures and the electric current of constant current source IS output, be actually equivalent resistance R1, equivalent resistance R2 and RDS sum.For the RDS of MOS FET device, the resistance that the test link is introduced is too big, therefore, and according to the accurate conducting resistance RDS after the test MOS FET device package of said method.
Summary of the invention
The method of the conducting resistance of the field effect transistor after the test package provided by the invention, Apparatus and system are in order to improve the accuracy of the conducting resistance after the test field effect transistor encapsulates.
The embodiment of the invention is achieved through the following technical solutions:
The embodiment of the invention provides the system of the conducting resistance of the field effect transistor after the test package, comprises
Packaged field-effect tube, constant current source, voltage table and test jack;
The drain electrode of described packaged field-effect tube links to each other with the positive pole of described voltage table by first contact flat spring of described test jack, and second contact flat spring by described test jack links to each other with the positive pole of described constant current source;
The source electrode of described packaged field-effect tube links to each other with the negative pole of described voltage table by the 3rd contact flat spring of described test jack, and the 4th contact flat spring by described test jack links to each other with the negative pole of described constant current source.
The embodiment of the invention also provides a kind of test jack, is used for the conducting resistance of the field effect transistor after the test package, and this test jack comprises:
At least four contact flat springs;
Wherein, an end of first contact flat spring and second contact flat spring is used for linking to each other with the drain electrode of described field effect transistor, and described first contact flat spring does not contact mutually with described second contact flat spring; One end of the 3rd contact flat spring and the 4th contact flat spring is used for linking to each other with the source electrode of described field effect transistor, and described the 3rd contact flat spring does not contact mutually with the 4th contact flat spring;
The other end of described first contact flat spring is used for linking to each other with the positive pole of voltage table;
The other end of described second contact flat spring is used for linking to each other with the positive pole of constant current source;
The other end of described the 3rd contact flat spring is used for linking to each other with the negative pole of voltage table;
The other end of described the 4th contact flat spring is used for linking to each other with the negative pole of constant current source.
The embodiment of the invention also provides a kind of method of using the conducting resistance of the field effect transistor after the above-mentioned test jack test package, comprising:
The drain electrode of packaged field-effect tube first contact flat spring by described test jack is linked to each other with the positive pole of voltage table and constant current source respectively with second contact flat spring, and the source electrode of packaged field-effect tube the 3rd contact flat spring by described test jack is linked to each other with the negative pole of voltage table and constant current source respectively with the 4th contact flat spring;
According to the magnitude of voltage of described voltage table output and the current value of described constant current source output, determine the conducting resistance of described field effect transistor.
Pass through technique scheme, in the embodiment of the invention, be connected the positive pole of constant current source and the positive pole of voltage table by test jack respectively with two contact flat springs that the drain electrode of tested field effect transistor links to each other, be connected the negative pole of constant current source and the negative pole of voltage table by test jack respectively with two contact flat springs that the source electrode of tested field effect transistor links to each other, according to this annexation, voltage table is directly parallel in the two ends of tested field effect transistor, by the characteristics of parallel circuit, the voltage that voltage table records is the voltage at tested field effect transistor two ends; Constant current source is connected with tested field effect transistor, characteristics by series circuit, the electric current of constant current source output is the electric current by tested field effect transistor, therefore, according to the technique scheme that the embodiment of the invention provides, can accurately record the conducting resistance of tested field effect transistor divided by the current value of constant current source output according to the magnitude of voltage that voltage table is measured.
Description of drawings
Fig. 1 used IC socket figure during for the RDS of test MOS FET in the prior art of the present invention;
Fig. 2 is the circuit connection diagram of the RDS of test MOS FET in the prior art of the present invention;
Fig. 3 is the equivalent circuit diagram of the RDS of test MOS FET in the prior art of the present invention;
Used test jack structural drawing when Fig. 4 is the RDS of test MOS FET in the embodiment of the invention;
Fig. 5 is system's connection layout of the RDS of test MOS FET in the embodiment of the invention;
Fig. 6 is the equivalent circuit diagram of circuit diagram shown in Figure 5 in the embodiment of the invention.
Embodiment
During at the conducting resistance of prior art after test field effect transistor encapsulation, because the resistance of introducing is the problem of test conduction resistance too greatly and accurately, the embodiment of the invention has proposed a kind of method, Apparatus and system of testing the conducting resistance after the field effect transistor encapsulation, is explained in detail to the main realization principle of technical solution of the present invention, specific implementation process and to the beneficial effect that should be able to reach below in conjunction with Figure of description and specific embodiment.
As shown in Figure 4, in order to make contact resistance that the test link introduces and lead resistance drop to minimum to the influence of RDS, the embodiment of the invention does not adopt IC socket as shown in Figure 1 in test process, and employing test jack as shown in Figure 4, this socket is compared with IC socket shown in Figure 1, can be from three utmost points of test package pipe, it is the D end, S end and G end are drawn two leads by two contact flat springs respectively, wherein, two contact flat springs that link to each other with the D end are respectively D/F, D/S, the company's contact flat spring that links to each other with the S end is respectively S/S, S/F, two contact flat springs that link to each other with the G end are respectively G/S, G/F.In this test jack, two contact flat springs that link to each other with the D end do not contact mutually, and promptly D/F does not contact mutually with D/S; Two contact flat springs that link to each other with the S end do not contact mutually, and promptly S/F does not contact mutually with S/S; Two contact flat springs that link to each other with the G end do not contact mutually, and promptly G/F does not contact mutually with G/S.
In conjunction with test jack shown in Figure 4, the concrete test process of the embodiment of the invention is described in detail:
As shown in Figure 5, be the system that the embodiment of the invention adopts when the test package pipe, this system comprises test package pipe, voltage table, constant current source and test jack.Wherein:
The lead that the contact flat spring 1 that is linked to each other by the D end of test jack and test package pipe is drawn links to each other with the positive pole of constant current source;
The lead that the contact flat spring 4 that is linked to each other by the S end of test jack and test package pipe is drawn links to each other with the negative pole of constant current source;
The lead that the contact flat spring 2 that is linked to each other by the D end of test jack and test package pipe is drawn links to each other with the positive pole of voltage table;
The lead that the contact flat spring 3 that is linked to each other by the S end of test jack and test package pipe is drawn links to each other with the negative pole of voltage table.
By above-mentioned annexation, form the test structure of one four end Kelvin connection.Wherein, the constant current source that is adopted is that (load of general provision constant current source is during greater than setting value for constant current source with high load capability, this constant current source has high load capability), voltage table be have high in the voltage table of resistance (the interior resistance of general provision voltage table is during greater than setting value, this voltage table has high interior resistance), concrete testing range is looked different product and is different, the conducting resistance of general package tube encapsulation Pretesting is more little, the electric current that the constant current source that requirement is selected for use can provide is big more, and it is accurately high more that voltage table can reach.
According to annexation shown in Figure 5, the lead resistance sum equivalence that will be connected the resistance of introducing by the pin of test package pipe with the contact flat spring of test jack and be introduced by the connection lead is resistance R i, particularly, four ends that are connected with the contact flat spring 1,2,3,4 of test jack, promptly the equivalent resistance of D/F, D/S, S/S, S/F end is followed successively by R1, R2, R3, R4; Wherein, D/F, D/S represent the offset signal end and the test signal end that drain, and S/F, S/S are the offset signal and the test signal end of source electrode.According to this equivalent relation, the equivalent circuit diagram of Fig. 5 correspondence as shown in Figure 6, like this, R1, R4, RDS and constant current source IS constitute bias loop, R2, R3, RDS and voltage table VDS formation test loop.According to this equivalence circuit diagram, in test loop, because voltage table has very large internal resistance (as tens kilo-ohms), the electric current that therefore flows through test loop is zero; In bias loop, the characteristic equal everywhere according to series circuit current, the electric current that flows through RDS and R1, R4 is IS, therefore, the magnitude of voltage at the D/S that voltage table tests out, S/S two ends is the voltage at RDS two ends, like this, after applying certain gate source voltage VGS, read the voltage VDS of voltage table output, and the current IS of constant current source output, conducting resistance RDS can obtain according to following formula:
RDS＝VDS/IS；
According to the technique scheme that the embodiment of the invention provides, the MOSFET test case with low on-resistance is as follows:
In test condition is that IS is 1.00A, VGS=10.00V, and the specimen model is that the conducting resistance RDS of the MOS FET of the A900156.1 related data of testing is as follows:
In theory, the conducting resistance that MOS FET tests out after encapsulation increases 2 to 3 milliohms than the conducting resistance that the encapsulation Pretesting goes out, and as can be seen from the above table, the test result that the method for testing of using the embodiment of the invention to provide obtains is coincide with expection.
Pass through technique scheme, in the embodiment of the invention, be connected the positive pole of constant current source and the positive pole of voltage table by test jack respectively with two contact flat springs that the drain electrode of tested field effect transistor links to each other, be connected the negative pole of constant current source and the negative pole of voltage table by test jack respectively with two contact flat springs that the source electrode of tested field effect transistor links to each other, according to this annexation, voltage table is directly parallel in the two ends of tested field effect transistor, by the characteristics of parallel circuit, the voltage that voltage table records is the voltage at tested field effect transistor two ends; Constant current source is connected with tested field effect transistor, characteristics by series circuit, the electric current of constant current source output is the electric current by tested field effect transistor, therefore, according to the technique scheme that the embodiment of the invention provides, can accurately record the conducting resistance of tested field effect transistor according to the current value that the magnitude of voltage and the constant current source of voltage table output are exported.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (8)
1. the system of the conducting resistance of the field effect transistor after the test package is characterized in that, comprising:
Packaged field-effect tube, constant current source, voltage table and test jack;
The drain electrode of described packaged field-effect tube links to each other with the positive pole of described voltage table by first contact flat spring of described test jack, and second contact flat spring by described test jack links to each other with the positive pole of described constant current source;
The source electrode of described packaged field-effect tube links to each other with the negative pole of described voltage table by the 3rd contact flat spring of described test jack, and the 4th contact flat spring by described test jack links to each other with the negative pole of described constant current source.
2. the system as claimed in claim 1 is characterized in that, the load of described constant current source is greater than setting value.
3. the system as claimed in claim 1 is characterized in that, the interior resistance of described voltage table is greater than setting value.
4. test jack is used for the conducting resistance of the field effect transistor after the test package, it is characterized in that, comprising:
At least four contact flat springs;
Wherein, an end of first contact flat spring and second contact flat spring is used for linking to each other with the drain electrode of described field effect transistor, and described first contact flat spring does not contact mutually with described second contact flat spring; One end of the 3rd contact flat spring and the 4th contact flat spring is used for linking to each other with the source electrode of described field effect transistor, and described the 3rd contact flat spring does not contact mutually with the 4th contact flat spring;
The other end of described first contact flat spring is used for linking to each other with the positive pole of voltage table;
The other end of described second contact flat spring is used for linking to each other with the positive pole of constant current source;
The other end of described the 3rd contact flat spring is used for linking to each other with the negative pole of voltage table;
The other end of described the 4th contact flat spring is used for linking to each other with the negative pole of constant current source.
5. a method of using the conducting resistance of the field effect transistor after the test jack test package as claimed in claim 4 is characterized in that, comprising:
The drain electrode of packaged field-effect tube first contact flat spring by described test jack is linked to each other with the positive pole of voltage table and constant current source respectively with second contact flat spring, and the source electrode of packaged field-effect tube the 3rd contact flat spring by described test jack is linked to each other with the negative pole of voltage table and constant current source respectively with the 4th contact flat spring;
According to the magnitude of voltage of described voltage table output and the current value of described constant current source output, determine the conducting resistance of described field effect transistor.
6. method as claimed in claim 5 is characterized in that the load of described constant current source is greater than setting value.
7. method as claimed in claim 5 is characterized in that, the interior resistance of described voltage table is greater than setting value.
8. method as claimed in claim 5 is characterized in that, according to the magnitude of voltage of described voltage table output and the current value of described constant current source output, determines the conducting resistance of described field effect transistor, specifically comprises:
The ratio of the current value that the magnitude of voltage of described voltage table output and described constant current source are exported is defined as the conducting resistance of described field effect transistor.
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Application publication date: 20100707 |