CN220473650U - Aging board suitable for SOT23-3 packaged chip aging test - Google Patents
Aging board suitable for SOT23-3 packaged chip aging test Download PDFInfo
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- CN220473650U CN220473650U CN202320666749.4U CN202320666749U CN220473650U CN 220473650 U CN220473650 U CN 220473650U CN 202320666749 U CN202320666749 U CN 202320666749U CN 220473650 U CN220473650 U CN 220473650U
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- 238000012360 testing method Methods 0.000 title claims abstract description 140
- 230000032683 aging Effects 0.000 title claims abstract description 65
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 238000004806 packaging method and process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
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- 238000012986 modification Methods 0.000 description 2
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- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
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- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
A burn-in board suitable for SOT23-3 packaged chip burn-in test comprises a PCB substrate, wherein a power input interface and a voltage output interface are arranged on the PCB substrate; the PCB substrate is provided with a single or a plurality of aging test fixture modules, and each aging test fixture module is provided with an input module connected with a power input interface, an output module connected with a voltage output interface, a load group module and a test module; the input module is VIN, is connected with the test module after passing through the input capacitor, and supplies power for the aging test chip in the test module; the output module is VOUT, outputs voltage after passing through the output capacitor, and detects the voltage of the chip burn-in test. The utility model can perform the high Wen Laolian test of any number of devices between 1 to m multiplied by n devices at one time, realizes the burn-in test of a large number of SOT23-3 packaged chips under the same test condition, and improves the test efficiency.
Description
Technical Field
The utility model relates to the technical field of reliability test of electronic components, in particular to a burn-in board suitable for a burn-in test of an SOT23-3 packaged chip.
Background
Aging tests are a method which is commonly used in engineering to remove early failure products and improve the reliability of the system. And a certain electric stress is continuously applied to the electronic component for a long time, various physical and chemical reaction processes in the component are accelerated through the comprehensive effect of the electric-thermal stress, various potential defects in the component are promoted to be exposed early, and the aim of eliminating early failure products is fulfilled.
The burn-in test is a non-destructive test that merely induces a potentially defective circuit without causing a new failure mechanism or altering its failure profile after the circuit is screened as a whole. The use reliability of the circuit can only be changed through the burn-in test, the inherent reliability of the whole circuit can not be changed, and the test conditions are selected mainly according to the reliability requirement degree of the circuit and the characteristics of failure mechanism. When the burn-in test is carried out, the electronic components are placed on the burn-in board and placed in a burn-in box to apply thermal stress and electrical stress, so as to excite early failure of the circuit.
The reliability of various components in the same batch of products is different due to various uncertainty factors of the electronic components in batch production. The aging test has good screening effect on a series of defects possibly existing in the process of manufacturing, such as surface contamination, poor lead welding, channel leakage, silicon chip crack, oxide layer defect, local heating pad, secondary breakdown and the like, and can promote the stability of electrical parameters of non-defective components, thereby ensuring the quality of products.
The traditional boss design causes the practical utilization area of the boss to be low due to station limitation, and the quantity of the products which can be aged is small, so that when the boss is aged in a large batch, more bosses are needed, the cost is increased, and the efficiency is reduced.
Moreover, the traditional ageing test board has the test mode of single type number and single load packaged in the same specification, so that the ageing test of the product can be realized, and different ageing test boards are required to be designed aiming at different output and different load ageing tests of packaged products in the same specification, and the cost of the ageing test board is increased.
Disclosure of Invention
Aiming at the technical problems, the technical scheme provides the aging board suitable for the SOT23-3 packaging chip aging test, which can perform the high Wen Laolian test of any number of devices between 1 and m multiplied by n devices at one time, realizes the aging test of a large number of SOT23-3 packaging chips under the same test condition, and improves the test efficiency; the problems can be effectively solved.
The utility model is realized by the following technical scheme:
a burn-in board suitable for SOT23-3 packaged chip burn-in test comprises a PCB substrate, wherein a power input interface and a voltage output interface are arranged on the PCB substrate; the PCB substrate is provided with a single or a plurality of aging test fixture modules, and each aging test fixture module is provided with an input module connected with a power input interface, an output module connected with a voltage output interface, a load group module and a test module; the input module is VIN, is connected with the test module after passing through the input capacitor, and supplies power for the aging test chip in the test module; the output module is VOUT, outputs voltage after passing through the output capacitor, and detects the voltage of the chip burn-in test.
Further, when the aging test fixture module is single or multiple, the load group module adopts a load combination multiplexing module, the load combination multiplexing module comprises a jumper terminal and N load resistors with different powers, the N load resistors with different powers are arranged in parallel and are respectively connected with pins on one side of the jumper terminal, and loads with different powers are selected through jumper caps to be connected with the test module.
Further, 2*N jumper pins are arranged in parallel on the jumper terminals, 2*N jumper pins are arranged in parallel on a row of jumper pins close to the load resistor, pins at the lower part of the jumper pins are respectively connected with the corresponding load resistor, pins at the lower part of the jumper pins are far away from the load resistor, the pins at the lower part of the jumper pins are respectively connected with the test module, and each group of corresponding jumper terminals in the 2 rows of jumper terminals are connected through a jumper wire or a jumper cap.
Further, when the jumper terminal is connected by adopting a jumper, one end of the jumper is fixed with the jumper terminal close to the load resistor, and the other end of the jumper is suspended; and selecting a jumper wire corresponding to a certain load resistor according to requirements, and connecting the jumper wire with a jumper wire terminal at one side far away from the load resistor, so that the test module is communicated with the certain load resistor.
Further, when the jumper terminal is connected by using the jumper cap, the jumper cap is a movable part, the outer layer is made of insulating plastic, and the inner layer is made of conductive material; when a certain load resistor is selected according to requirements, the jumper cap is inserted onto two jumper pins corresponding to the certain load resistor, and the two jumper pins are connected; when the jumper cap is buckled on the two jumper pins, the jumper pins are in an on state, current passes through, and when the jumper cap is not buckled, the jumper pins are in an off state, and no current passes through.
Further, the load resistor adopts a resistor with a resistance value of 1K or/and 1.2K or/and 2.5K or/and 3.3K or/and 4.5K or/and other different powers.
Further, when the aging test fixture modules are multiple, the load group module comprises a single power resistor connected with the test module, and the power resistor is connected with the test module through a load.
Further, the resistance value of the power resistor is 2.5K.
Further, the capacitance value of the input capacitor and the output capacitor is 0.1uF.
Further, the test module comprises m rows and n columns of aging test fixtures for fixing SOT23-3 packaged chips, and the aging test fixtures are connected with the power input interface and the voltage output interface through copper sheet circuits on the top layer or the bottom layer of the PCB substrate.
Advantageous effects
Compared with the prior art, the aging board suitable for the SOT23-3 packaging chip aging test has the following beneficial effects:
(1) When the boss is used for the double-station boss test, the boss can increase the boss quantity of the SOT23-3 (GER 3025 product) packaged chip device in a high Wen Laolian test at one time, for example, when the quantity of the boss is 1400, for example, the existing single-station boss can be used for boss 100 chips, 14 boss PCBs need to be provided, if the boss can be used for boss 140 chips, 10 boss PCBs need to be provided, and the cost can be reduced by 28%. As the same aging PCB is added with a multi-station test unit, the number of 100 chips in the original basic single station is increased to 140 chips in the existing double station, and the efficiency is improved by 40%.
(2) The aging board solves the problem that products of the same series and different types cannot share one aging board by using jumper terminals and jumper/jumper caps to select different power resistors. If the GER30XX series products have four different outputs, four sets of aging plates with different loads are needed, and one set of plates can realize four output aging tests with different models through jumper wire selection multiplexing, so that the cost can be directly reduced by about 75%.
Drawings
FIG. 1 is a schematic diagram of the structure of a packaged chip product of SOT23-3GER30XX series products.
Fig. 2 is a block diagram showing the overall structure of embodiment 1 of the present utility model.
Fig. 3 is a schematic circuit diagram of the burn-in test fixture module of example 1.
FIG. 4 is a schematic top-level diagram of a boss suitable for SOT23-3 chip production in example 1.
FIG. 5 is a schematic of the bottom layer of a boss suitable for SOT23-3 chip products in example 1.
Fig. 6 is a block diagram showing the overall structure of embodiment 2 of the present utility model.
Fig. 7 is a schematic circuit diagram of the burn-in test fixture module of example 2.
FIG. 8 is a schematic top-level diagram of a boss suitable for SOT23-3 chip production in example 2.
FIG. 9 is a schematic view of the bottom layer of a boss suitable for SOT23-3 chip products in example 2.
Detailed Description
The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. The described embodiments are only some, but not all, embodiments of the utility model. Various modifications and improvements of the technical scheme of the utility model, which are made by those skilled in the art, are included in the protection scope of the utility model without departing from the design concept of the utility model.
Example 1:
as shown in FIG. 2, the burn-in board suitable for the burn-in test of SOT23-3 packaged chips comprises a PCB substrate, wherein a power input interface and a voltage output interface are arranged on the PCB substrate; a single aging test fixture module is arranged on the PCB substrate, and each aging test fixture module is provided with an input module connected with a power input interface, an output module connected with a voltage output interface, a load group module and a test module; the input module is VIN, is connected with the test module after passing through the input capacitor, and supplies power for the aging test chip in the test module; the output module is VOUT, outputs voltage after passing through the output capacitor, and detects the voltage of the chip burn-in test.
The aging test fixture module is single, the load group module adopts a load combination multiplexing module, the load combination multiplexing module comprises a jumper terminal and N load resistors with different powers, the N load resistors with different powers are arranged in parallel and are respectively connected with pins on one side of the jumper terminal, and loads with different powers are selected through jumper caps to be connected with the test module.
The jumper terminals are provided with 2*N jumper pins in parallel, 2*N jumper pins are arranged in parallel, a row of jumper pins close to the load resistor is connected with the corresponding load resistor, a row of jumper pins far away from the load resistor is connected with the test module, and the corresponding jumper terminals of each group in the 2 rows of jumper terminals are connected through jumpers or jumper caps.
When the jumper terminal is connected by adopting a jumper, one end of the jumper is fixed with the jumper terminal close to the load resistor, and the other end of the jumper is suspended; and selecting a jumper wire corresponding to a certain load resistor according to requirements, and connecting the jumper wire with a jumper wire terminal at one side far away from the load resistor, so that the test module is communicated with the certain load resistor.
When the jumper terminal is connected by using the jumper cap, the jumper cap is a movable component, the outer layer is made of insulating plastic, and the inner layer is made of conductive material; when a certain load resistor is selected according to requirements, the jumper cap is inserted onto two jumper pins corresponding to the certain load resistor, and the two jumper pins are connected; when the jumper cap is buckled on the two jumper pins, the jumper pins are in an on state, current passes through, and when the jumper cap is not buckled, the jumper pins are in an off state, and no current passes through.
As shown in fig. 3, the test module is provided with three pins, which are in turn: one pin, two pins and three pins. The input VIN is connected with a pin through an input capacitor, a power supply is conveyed to the test module, meanwhile, the pin is connected with three pins through the input capacitor, two pins are connected with one side of the jumper terminal through 4 load resistors, and the 4 load resistors respectively adopt resistors with different power of 1.2K, 2.5K, 3.3K and 4.5K. The other side of the jumper terminal is connected with the three pins. The second pin is connected with the third pin through an output capacitor. The capacitance of the input capacitance and the output capacitance was 0.1uF.
And forming aging conditions, and selecting different loads through jumper wires or jumper wire caps according to different test products.
The test module comprises 10 rows and 10 columns of aging test fixtures for fixing SOT23-3 packaged chips, and the aging test fixtures are connected with a power input interface and a voltage output interface through copper sheet circuits on the top layer or the bottom layer of the PCB substrate
The power supply of PCB base plate is provided by external equipment, and the positive pole of power is connected through 10 VIN copper sheet lines of board back to provide the experimental chip in every ageing anchor clamps, the power negative pole is connected with the third foot of every ageing chip through N copper sheet lines of ageing board (board positive and board back). As shown in fig. 4 and 5.
The current situation that products of the same series and different types cannot share one set of aging board is solved by using a jumper terminal and a jumper/jumper cap to select different power resistors; the method is applicable to common aging boards with multiple types of SOT23-3 packaging chips (GER 30XX series products), and the corresponding types of the products are as follows: GER3012, GER3025, GER3033, and GER3050. Through jumper wire selection multiplexing, one set of board can realize four output aging tests of different models, and the cost can be directly reduced by about 75%.
Example 2:
as shown in FIG. 6, the double-station burn-in board suitable for the SOT23-3 packaged chip burn-in test comprises a PCB substrate, wherein a power input interface and a voltage output interface are arranged on the PCB substrate; two aging test fixture modules are arranged on the PCB substrate, and each aging test fixture module is provided with an input module connected with a power input interface, an output module connected with a voltage output interface, a load group module and a test module; the input module is VIN, is connected with the test module after passing through the input capacitor, and supplies power for the aging test chip in the test module; the output module is VOUT, outputs voltage after passing through the output capacitor, and detects the voltage of the chip burn-in test.
The ageing test fixture modules are two, the load group module comprises a single power resistor connected with the test module, and the power resistor is connected with the test module through a load.
As shown in fig. 7, the burn-in test fixture module has two test modules, i.e., the test module adopts a duplex position, and the pins thereof include an input pin 1 and an input pin 11, and output end hardware 2 and an output end 12, and a ground pin 3 and an output end 13.
The two input ends VIN are respectively connected with the 1 pin and the 11 pin through input capacitors to transmit power to the test module, meanwhile, the 1 pin is connected with the 3 pin through the input capacitors, and the 11 pin is connected with the 13 pin through the input capacitors; the 2 pin is connected with one end of a load resistor, the other end of the load resistor is connected with the 3 pin, the 12 pin is connected with one end of the load resistor, and the other end of the load resistor is connected with the 3 pin; the resistance of the load resistor was 2.5K. The 2 pin is connected with the 3 pin through an output capacitor, and the 12 pin is connected with the 13 pin through the output capacitor. The capacitance of the input capacitance and the output capacitance was 0.1uF. Aging test conditions were established.
The test module comprises 7 rows and 10 columns of aging test fixtures for fixing SOT23-3 packaged chips, and the aging test fixtures are connected with a power input interface and a voltage output interface through copper sheet circuits on the top layer or the bottom layer of the PCB substrate
The power supply of PCB base plate is provided by external equipment, and the positive pole of power is connected through 10 VIN copper sheet lines of board back to be connected to every test module's input, provide the experimental chip in every ageing anchor clamps in the test module, the power negative pole is connected with the 3 rd foot and 13 pins of ageing chip through ageing board (board positive and board back) N copper sheet lines. As shown in fig. 8 and 9.
When the burn-in board for the double-station burn-in test is adopted, the burn-in quantity for carrying out a high Wen Laolian test on SOT23-3 (GER 3025 product) packaged chip devices can be increased once, and as the same burn-in PCB substrate is a double-station test unit, each test unit can test 7X 10 packaged chips, and the efficiency is increased by 40% because the number of the disposable batch burn-in products is 1400.
Example 3:
a burn-in board suitable for SOT23-3 packaged chip burn-in test comprises a PCB substrate, wherein a power input interface and a voltage output interface are arranged on the PCB substrate; the PCB substrate is provided with a plurality of aging test fixture modules, and each aging test fixture module is provided with an input module connected with a power input interface, an output module connected with a voltage output interface, a load group module and a test module; the input module is VIN, is connected with the test module after passing through the input capacitor, and supplies power for the aging test chip in the test module; the output module is VOUT, outputs voltage after passing through the output capacitor, and detects the voltage of the chip burn-in test.
The load group modules in the aging test fixture modules all adopt load combination multiplexing modules, and the structures and connection modes of the load combination multiplexing modules and other components are the same as those in the embodiment 1. The figures are not provided in this embodiment.
The foregoing is only illustrative of the present utility model, but the scope of the present utility model is not limited thereto, and any changes, substitutions and modifications within the technical scope of the present utility model are within the scope of the present utility model.
Claims (10)
1. A burn-in board suitable for SOT23-3 packaged chip burn-in test comprises a PCB substrate, wherein a power input interface and a voltage output interface are arranged on the PCB substrate; the method is characterized in that: the PCB substrate is provided with a single or a plurality of aging test fixture modules, and each aging test fixture module is provided with an input module connected with a power input interface, an output module connected with a voltage output interface, a load group module and a test module; the input module is VIN, is connected with the test module after passing through the input capacitor, and supplies power for the aging test chip in the test module; the output module is VOUT, outputs voltage after passing through the output capacitor, and detects the voltage of the chip burn-in test.
2. A burn-in board for use in a SOT23-3 packaged chip burn-in test as defined in claim 1, wherein: when the aging test fixture modules are single or multiple, the load group module adopts a load combination multiplexing module, the load combination multiplexing module comprises a jumper terminal and N load resistors with different powers, the N load resistors with different powers are arranged in parallel and are respectively connected with pins on one side of the jumper terminal, and loads with different powers are selected through jumper caps to be connected with the test module.
3. A burn-in board for use in a SOT23-3 packaged chip burn-in test as defined in claim 2, wherein: the jumper terminal is provided with 2*N jumper pins in parallel, 2*N jumper pins are arranged in parallel, a row of jumper pins close to the load resistor is connected with the corresponding load resistor, a row of jumper pins far away from the load resistor is connected with the test module, and the corresponding jumper terminals of each group in the 2 rows of jumper terminals are connected through jumpers or jumper caps.
4. A burn-in board for use in a SOT23-3 packaged chip burn-in test as defined in claim 3, wherein: when the jumper terminal is connected by adopting a jumper, one end of the jumper is fixed with the jumper terminal close to the load resistor, and the other end of the jumper is suspended; and selecting a jumper wire corresponding to a certain load resistor according to requirements, and connecting the jumper wire with a jumper wire terminal at one side far away from the load resistor, so that the test module is communicated with the certain load resistor.
5. A burn-in board for use in a SOT23-3 packaged chip burn-in test as defined in claim 3, wherein: when the jumper terminal is connected by using a jumper cap, the jumper cap is a movable part, the outer layer is made of insulating plastic, and the inner layer is made of conductive material; when a certain load resistor is selected according to requirements, the jumper cap is inserted onto two jumper pins corresponding to the certain load resistor, and the two jumper pins are connected; when the jumper cap is buckled on the two jumper pins, the jumper pins are in an on state, current passes through, and when the jumper cap is not buckled, the jumper pins are in an off state, and no current passes through.
6. A boss for SOT23-3 packaged chip burn-in testing according to any one of claims 2 to 5, wherein: the load resistor adopts a resistor with the resistance value of 1K or/and 1.2K or/and 2.5K or/and 3.3K or/and 4.5K power.
7. A burn-in board for use in a SOT23-3 packaged chip burn-in test as defined in claim 1, wherein: when the ageing test fixture modules are multiple, the load group module comprises a single power resistor connected with the test module, and the power resistor is connected with the test module through a load.
8. The burn-in board for use in a SOT23-3 packaged chip burn-in test of claim 7, wherein: the resistance value of the power resistor is 2.5K.
9. A boss for SOT23-3 packaged chip burn-in testing according to any one of claims 1-5 and 7, wherein: the capacitance of the input capacitor and the output capacitor is 0.1uF.
10. A burn-in board for use in a SOT23-3 packaged chip burn-in test as defined in claim 1, wherein: the test module comprises m rows and n columns of aging test fixtures for fixing SOT23-3 packaging chips, and the aging test fixtures are connected with a power input interface and a voltage output interface through copper sheet circuits on the top layer or the bottom layer of the PCB substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320666749.4U CN220473650U (en) | 2023-03-29 | 2023-03-29 | Aging board suitable for SOT23-3 packaged chip aging test |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320666749.4U CN220473650U (en) | 2023-03-29 | 2023-03-29 | Aging board suitable for SOT23-3 packaged chip aging test |
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| CN220473650U true CN220473650U (en) | 2024-02-09 |
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