CN217768131U - Multilayer ceramic capacitor - Google Patents
Multilayer ceramic capacitor Download PDFInfo
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- CN217768131U CN217768131U CN202221275946.5U CN202221275946U CN217768131U CN 217768131 U CN217768131 U CN 217768131U CN 202221275946 U CN202221275946 U CN 202221275946U CN 217768131 U CN217768131 U CN 217768131U
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Abstract
A laminated ceramic capacitor is provided with: a laminate including an internal layer section in which internal dielectric layers and internal electrode layers are alternately laminated; a1 st external electrode disposed on one side in the longitudinal direction of the laminate; and 2 nd external electrodes disposed on the other side in the longitudinal direction, the internal electrode layers each having: a1 st external electrode side electrode layer connected to the 1 st external electrode; and a2 nd external electrode side electrode layer connected to the 2 nd external electrode, the tip of the 2 nd external electrode side electrode layer facing the tip of the 1 st external electrode side electrode layer with a deviation in the lamination direction of 20 μm or less, the internal electrode layers further including a1 st internal electrode layer and a2 nd internal electrode layer alternately arranged, wherein tip portions including tips facing each other of the 1 st external electrode side electrode layer and the 2 nd external electrode side electrode layer among the internal electrode layers closest to the 1 st main surface which is a surface on one side in the lamination direction in the laminated body are bent toward the 1 st main surface side. This makes it difficult for the interface between the inner layer portion and the outer layer portion to peel off.
Description
Technical Field
The utility model relates to a range upon range of ceramic capacitor.
Background
A multilayer ceramic capacitor is provided with: a laminate body including an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated with each other, and an outer layer portion provided on both sides of the inner layer portion; and external electrodes provided on both end surfaces of the laminate (see patent document 1). Conventionally, in such a multilayer ceramic capacitor, there has been a problem that peeling occurs at an interface between an inner layer portion and an outer layer portion.
Prior art documents
Patent document
Patent document 1: japanese patent laid-open publication No. 2019-153778
SUMMERY OF THE UTILITY MODEL
Problem to be solved by utility model
An object of the present invention is to provide a laminated ceramic capacitor in which peeling at the interface between the inner layer portion and the outer layer portion is less likely to occur.
Means for solving the problems
In order to solve the above problem, the utility model provides a range upon range of ceramic capacitor possesses: a laminate including an internal layer portion in which internal dielectric layers and internal electrode layers are alternately laminated; a1 st external electrode disposed on one side in a longitudinal direction orthogonal to a lamination direction of the laminate; and 2 nd external electrodes disposed on the other side in the longitudinal direction, the internal electrode layers each having: a1 st external electrode side electrode layer connected to the 1 st external electrode; and a2 nd external electrode side electrode layer connected to the 2 nd external electrode and having a tip facing a tip of the 1 st external electrode side electrode layer with an offset in the lamination direction of 20 μm or less, the internal electrode layers being further alternately arranged: a1 st internal electrode layer, the 1 st external electrode side electrode layer being longer than the 2 nd external electrode side electrode layer; and a2 nd inner electrode layer, the 2 nd outer electrode side electrode layer being longer than the 1 st outer electrode side electrode layer, tip portions including the tips facing each other of the 1 st outer electrode side electrode layer and the 2 nd outer electrode side electrode layer among the inner electrode layers closest to a1 st main surface that is a surface on one side in the lamination direction in the laminated body being bent toward the 1 st main surface side.
Effect of the utility model
According to the present invention, a laminated ceramic capacitor in which peeling at the interface between the inner layer portion and the outer layer portion is not easily caused can be provided.
Drawings
Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1.
Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II.
Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.
Fig. 4 is a flowchart illustrating a method of manufacturing the laminated ceramic capacitor 1.
Description of the reference numerals
1: a laminated ceramic capacitor;
2: a laminate;
3: an external electrode;
3A: 1 st external electrode;
3B: a2 nd external electrode;
4: an inner dielectric layer;
5: an internal electrode layer;
5A: 1 st internal electrode layer;
5B: 2 nd internal electrode layer;
6: an inner layer portion;
7: an outer layer part;
50: an outermost 1 st internal electrode layer;
51. 51A, 51B: 1 st external electrode side electrode layer;
51c, 52c: a front end portion;
52. 52A, 52B: and 2 nd external electrode side electrode layer.
Detailed Description
The multilayer ceramic capacitor 1 according to the embodiment of the present invention will be described below. Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1. Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II. Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.
(multilayer ceramic capacitor 1)
The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape, and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer portion 6, and the inner layer portion 6 includes a plurality of internal dielectric layers 4 and a plurality of internal electrode layers 5 that are stacked.
In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1 is referred to as the longitudinal direction L. The direction in which the internal dielectric layers 4 and the internal electrode layers 5 are stacked is referred to as a stacking direction T. A direction intersecting both the longitudinal direction L and the stacking direction T is defined as a width direction W. In the embodiment, the width direction W is orthogonal to both the longitudinal direction L and the stacking direction T.
Further, a pair of outer surfaces opposed in the lamination direction T among the six outer surfaces of the laminate 2 is defined as A1 st main surface A1 and A2 nd main surface A2, a pair of outer surfaces opposed in the width direction W is defined as A1 st side surface B1 and A2 nd side surface B2, and a pair of outer surfaces opposed in the longitudinal direction L is defined as A1 st end surface C1 and A2 nd end surface C2 of the laminate 2. Fig. 2 is a cross section passing through the center in the width direction W and extending in the stacking direction T and the longitudinal direction L.
In the case where the description is given without particularly distinguishing the 1 st main surface A1 from the 2 nd main surface A2, the description will be given collectively as the main surface a, in the case where the description is given without particularly distinguishing the 1 st side surface B1 from the 2 nd side surface B2, the description will be given collectively as the side surface B, and in the case where the description is given collectively as the end surface C without particularly distinguishing the 1 st end surface C1 from the 2 nd end surface C2.
(laminate 2)
The laminate 2 includes an inner layer 6 and an outer layer 7 disposed on both main surfaces a of the inner layer 6.
(outer layer portion 7)
The outer layer portion 7 is disposed on the 1 st main surface A1 side and the 2 nd main surface A2 side of the inner layer portion 6, and is made of the same ceramic material as the inner dielectric layer 4 of the inner layer portion 6.
(inner layer part 6)
The inner layer portion 6 includes a plurality of internal dielectric layers 4 and a plurality of internal electrode layers 5 that are stacked.
(internal dielectric layer 4)
The thickness of the internal dielectric layer 4 in the stacking direction T is 2 μm or more and 50 μm or less. The internal dielectric layer 4 is mainly composed of a ceramic material containing Ca (calcium) and Zr (zirconium) and having a general formula ABO 3 The perovskite structure shown. The perovskite structure comprises an ABO of off-stoichiometric composition 3 - α. For example, caZrO can be used as the ceramic material 3 (calcium zirconate). Since the perovskite containing Ca and Zr has a small temperature change in electrostatic capacitance, it has a temperature coefficient Tc [ ppm/. Degree.C ]]Such characteristics are small.
(internal electrode layer 5)
The thickness of the internal electrode layers 5 in the stacking direction T is 0.7 μm or more and 2 μm or less. The internal electrode layers 5 are conductive thin films containing Cu (copper) as a main component and a common material containing Ca, zr, and O and not containing an alkali metal. For example, the internal electrode layers 5 are conductive thin films containing Cu as a main component and a common material containing CaZrO 3 And does not contain alkali metals. Further, for example, the internal electrode layers 5 are conductive thin films containing Cu as a main component and a common material containing CaZrO 3 . In addition, for example, the internal electrode layers 5 are conductive thin films containing Cu as a main component and a common material containing only CaZrO 3 。
The internal electrode layers 5 include a plurality of 1 st internal electrode layers 5A and a plurality of 2 nd internal electrode layers 5B. The 1 st internal electrode layers 5A and the 2 nd internal electrode layers 5B are alternately arranged.
The 1 st internal electrode layer 5A has a1 st external electrode side electrode layer 51A and a2 nd external electrode side electrode layer 52A, the 1 st external electrode side electrode layer 51A is connected to the 1 st external electrode 3A, and the 2 nd external electrode side electrode layer 52A is not continuous with the 1 st external electrode side electrode layer 51A and is connected to the 2 nd external electrode 3B. The 1 st external electrode side electrode layer 51A and the 2 nd external electrode side electrode layer 52A are formed on the same plane so as to be insulated from each other. In the 1 st internal electrode layer 5A, the 1 st external electrode side electrode layer 51A is longer than the 2 nd external electrode side electrode layer 52A.
In one 1 st internal electrode layer 5A, a shift T1 in the lamination direction T between the tip 51A of the 1 st external electrode side electrode layer 51A and the tip 52A of the 2 nd external electrode side electrode layer 52A facing each other is 20 μm or less.
The 2 nd internal electrode layer 5B has a1 st external electrode side electrode layer 51B and a2 nd external electrode side electrode layer 52B, the 1 st external electrode side electrode layer 51B is connected to the 1 st external electrode 3A, and the 2 nd external electrode side electrode layer 52B is not continuous with the 1 st external electrode side electrode layer 51B and is connected to the 2 nd external electrode 3B. The 1 st external electrode side electrode layer 51B and the 2 nd external electrode side electrode layer 52B are formed on the same plane so as to be insulated from each other. In the 2 nd internal electrode layer 5B, the 2 nd external electrode side electrode layer 52B is longer than the 1 st external electrode side electrode layer 51B.
In one 2 nd internal electrode layer 5B, a shift T2 in the stacking direction T of the tip 51B of the 1 st external electrode side electrode layer 51B and the tip 52B of the 2 nd external electrode side electrode layer 52B facing each other is also 20 μm or less.
The 1 st external electrode side electrode layer 51A of the 1 st internal electrode layer 5A and the 2 nd external electrode side electrode layer 52B of the 2 nd internal electrode layer 5B adjacent to the 1 st internal electrode layer 5A are both longer electrode layers, and have an overlapping region P overlapping each other at a central portion in the longitudinal direction L. Between the 1 st external electrode side electrode layer 51A and the 2 nd external electrode side electrode layer 52B facing each other in the overlapping region P, electric charges are accumulated and the portions function as capacitors.
The outermost 1 st internal electrode layer 50, which is the internal electrode layer 5 closest to the 1 st main surface A1 in the inner layer portion 6, is the 1 st internal electrode layer 5A in the embodiment. In the outermost 1 st inner electrode layer 50, the tip portion 51c of the 1 st outer electrode side electrode layer 51A including the tip 51A and the tip portion 52c of the 2 nd outer electrode side electrode layer 52A including the tip 52A facing the tip 51A are bent toward the 1 st main surface A1 side, that is, toward the outside.
(side spacer 8)
As shown in fig. 3, the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are not exposed at the side face B in the width direction W of the laminate 2, and this portion becomes the side partition portion 8.
(external electrode 3)
The external electrodes 3 include a1 st external electrode 3A provided on a1 st end face C1 of the laminate 2 and a2 nd external electrode 3B provided on a2 nd end face C2 of the laminate 2. In addition, when the 1 st external electrode 3A and the 2 nd external electrode 3B are not particularly described separately, they are collectively described as the external electrodes 3.
(method of manufacturing multilayer ceramic capacitor 1)
Fig. 4 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment.
(Process for producing ceramic Green sheet S1)
In step S1, the ceramic slurry is formed into a sheet on the mounting film, and a band-shaped ceramic green sheet to be the internal dielectric layer 4 is manufactured. Here, thick portions for bending the leading end portion 51c of the 1 st external electrode side electrode layer 51 and the leading end portion 52c of the 2 nd external electrode side electrode layer 52 are formed on the ceramic green sheet disposed closest to the 1 st main surface A1. The thick portions are formed at a pitch corresponding to the length of the laminate 2 in the longitudinal direction L of the ceramic green sheets such that the longitudinal direction extends in the width direction W of the ceramic green sheets.
(internal electrode layer Pattern printing Process S2)
An internal electrode layer pattern to be the internal electrode layer 5 was printed on the ceramic green sheet. The internal electrode layer pattern is printed intermittently in the longitudinal direction L.
In the ceramic green sheet disposed on the side closest to the 1 st main surface A1, the internal electrode layer pattern is printed such that a region between the internal electrode layer pattern and the internal electrode layer pattern where the internal electrode layer pattern is not present is located in the center of the thick portion, the end portions of the internal electrode layer pattern are located on both sides in the short-side direction of the thick portion, and the end portions thereof climb over the thick portion.
(laminating step S3)
In step S3, a plurality of ceramic green sheets are stacked, and a thick portion of the ceramic green sheet is stacked on the 1 st main surface A1 side, thereby manufacturing a sheet for an inner layer portion.
Further, the ceramic green sheets for the outer layer portion, which become the outer layer portion 7, are stacked on both sides of the sheet for the inner layer portion in the stacking direction T, respectively, to manufacture a laminated sheet.
(Master batch Forming step S4)
Next, in step S4, a mother block is formed by thermocompression bonding in the stacking direction T of the stacked sheets. At this time, the material of the ceramic green sheets for the outer layer portion located outside the thick portion provided on the ceramic green sheet disposed closest to the 1 st main surface A1 side flows to both sides of the thick portion, and the 1 st main surface A1 side becomes flat with respect to the main surface a of the mother block.
(Master block dividing step S5)
Next, in step S5, the mother block is divided to produce a plurality of laminated bodies 2.
(external electrode formation step S6)
In step S6, the external electrodes 3 are formed on both end portions of the laminate 2.
(firing step S7)
Then, in step S7, the external electrodes 3 are fired on the laminate 2 by heating at the set firing temperature for a given time in a nitrogen atmosphere, thereby producing the multilayer ceramic capacitor 1 shown in fig. 1.
(effects of the embodiment)
Generally, in the multilayer ceramic capacitor 1, separation is likely to occur between the inner layer portion and the outer layer portion and at the interface where the internal dielectric layers and the internal electrode layers are laminated.
However, according to the multilayer ceramic capacitor 1 of the present embodiment, the leading end portions 51c and 52c of the 1 st and 2 nd external electrode side electrode layers 51 and 52 including the mutually opposing leading ends 51a and 52a are bent outward toward the 1 st main surface A1 side. Therefore, the bent portion is fitted into the outer layer portion 7, and the outer layer portion 7 and the inner layer portion 6 are improved in adhesion, so that separation is less likely to occur.
While the preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and various modifications can be made.
Claims (3)
1. A multilayer ceramic capacitor is characterized by comprising:
a laminate including an internal layer portion in which internal dielectric layers and internal electrode layers are alternately laminated;
a1 st external electrode disposed on one side in a longitudinal direction orthogonal to a lamination direction of the laminate; and
a2 nd external electrode disposed on the other side in the longitudinal direction,
the internal electrode layers each have:
a1 st external electrode side electrode layer connected to the 1 st external electrode; and
a2 nd external electrode side electrode layer connected to the 2 nd external electrode and having a tip facing a tip of the 1 st external electrode side electrode layer with an offset of 20 μm or less in the stacking direction,
the internal electrode layers are also alternately configured with:
a1 st inner electrode layer, the 1 st outer electrode side electrode layer being longer than the 2 nd outer electrode side electrode layer; and
a2 nd internal electrode layer, the 2 nd external electrode side electrode layer being longer than the 1 st external electrode side electrode layer,
in the internal electrode layers closest to the 1 st main surface that is one surface in the stacking direction in the stacked body,
the 1 st external electrode side electrode layer and the 2 nd external electrode side electrode layer have tip portions including the tips facing each other bent toward the 1 st main surface side.
2. The laminated ceramic capacitor according to claim 1,
the thickness of the internal dielectric layer is 2 [ mu ] m or more and 50 [ mu ] m or less.
3. The laminated ceramic capacitor according to claim 1 or claim 2,
the thickness of the internal electrode layer is 0.7 [ mu ] m or more and 2 [ mu ] m or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221275946.5U CN217768131U (en) | 2022-05-25 | 2022-05-25 | Multilayer ceramic capacitor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221275946.5U CN217768131U (en) | 2022-05-25 | 2022-05-25 | Multilayer ceramic capacitor |
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| Publication Number | Publication Date |
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| CN217768131U true CN217768131U (en) | 2022-11-08 |
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| CN202221275946.5U Active CN217768131U (en) | 2022-05-25 | 2022-05-25 | Multilayer ceramic capacitor |
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| Country | Link |
|---|---|
| CN (1) | CN217768131U (en) |
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