CN217521858U - Multilayer ceramic capacitor - Google Patents
Multilayer ceramic capacitor Download PDFInfo
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- CN217521858U CN217521858U CN202221113181.5U CN202221113181U CN217521858U CN 217521858 U CN217521858 U CN 217521858U CN 202221113181 U CN202221113181 U CN 202221113181U CN 217521858 U CN217521858 U CN 217521858U
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Abstract
Provided is a laminated ceramic capacitor which is less likely to be peeled off. The utility model discloses a laminated ceramic capacitor (1) possesses: a laminate (2) comprising a1 st inner layer (61) and a2 nd inner layer (62) in which an internal dielectric layer (4) and an internal electrode layer (5) are alternately laminated; a1 st external electrode (3A) disposed in one of the longitudinal directions of the laminate (2) that are orthogonal to the lamination direction; and a2 nd external electrode (3B) disposed on the other side in the longitudinal direction, the internal electrode layer (5) having: an overlap region (P) that overlaps the internal electrode layers (5) adjacent to each other in the stacking direction; and a non-overlapping region that does not overlap with the internal electrode layers (5) adjacent in the stacking direction, wherein the 1 st internal layer (61) is located on one main surface side in the stacking direction of the stacked body (2), and the internal electrode layer (5) on the most one main surface side in the 1 st internal layer (61) has a bent portion (Q) that is bent in the stacking direction in the non-overlapping region.
Description
Technical Field
The utility model relates to a range upon range of ceramic capacitor.
Background
A multilayer ceramic capacitor is provided with: a laminate body including an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated, and an outer layer portion provided on both sides of the inner layer portion; and external electrodes provided on both end surfaces of the laminate (see patent document 1). Conventionally, in such a multilayer ceramic capacitor, there has been a problem that peeling occurs at the interface between the inner layer portion and the outer layer portion.
Prior art documents
Patent document
Patent document 1: japanese patent laid-open publication No. 2019-153778
SUMMERY OF THE UTILITY MODEL
Problem to be solved by utility model
An object of the utility model is to provide a be difficult for producing range upon range of ceramic capacitor who peels off.
Means for solving the problems
In order to solve the above problem, the utility model provides a range upon range of ceramic capacitor possesses: a laminate including a1 st inner layer portion and a2 nd inner layer portion in which the internal dielectric layers and the internal electrode layers are alternately laminated; a1 st external electrode disposed in one of longitudinal directions of the laminate orthogonal to the lamination direction; and a2 nd external electrode disposed on the other side in the longitudinal direction, the internal electrode layer including: an overlap region overlapping the internal electrode layers adjacent in the stacking direction; and a non-overlapping region that does not overlap with the internal electrode layers adjacent in the stacking direction, wherein the 1 st inner layer portion is located on one principal surface side in the stacking direction in the stacked body, and the internal electrode layer closest to the one principal surface side in the 1 st inner layer portion has a bent portion that is bent in the stacking direction in the non-overlapping region.
Effect of the utility model
According to the utility model discloses, can provide a range upon range of ceramic capacitor that is difficult for producing and peels off.
Drawings
Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1.
Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II.
Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.
Fig. 4 is an enlarged image of a cross section of the 1 st inner layer 61 or the 2 nd inner layer 62.
Fig. 5 is a flowchart illustrating a method of manufacturing the laminated ceramic capacitor 1.
Description of the reference numerals
A P overlap region;
a Q-bend section;
1a laminated ceramic capacitor;
2, laminating;
3 an external electrode;
3A No. 1 external electrode;
3B a2 nd external electrode;
4 an internal dielectric layer;
5 internal electrode layers;
5A the 1 st internal electrode layer;
6 an inner layer part;
7 outer layer part;
8 side spacing parts;
51A, 51B No. 1 external electrode side electrode layer;
52A, 52B 2 nd external electrode side electrode layers;
61 a1 st inner layer portion;
62 a2 nd inner layer portion;
63 an intermediate dielectric layer.
Detailed Description
The multilayer ceramic capacitor 1 according to the embodiment of the present invention will be described below. Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1. Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II. Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.
(multilayer ceramic capacitor 1)
The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape, and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer portion 6, and the inner layer portion 6 includes a plurality of internal dielectric layers 4 and a plurality of internal electrode layers 5 that are stacked. In the drawings, the number of stacked internal dielectric layers 4 and internal electrode layers 5 is indicated as a small number to facilitate understanding, but the present invention is not limited thereto.
In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1 is referred to as the longitudinal direction L. The direction in which the internal dielectric layers 4 and the internal electrode layers 5 are stacked is referred to as a stacking direction T. The direction intersecting both the longitudinal direction L and the stacking direction T is defined as the width direction W. In the embodiment, the width direction W is orthogonal to both the longitudinal direction L and the stacking direction T.
Further, a pair of outer surfaces facing each other in the stacking direction T among the 6 outer surfaces of the laminate 2 is defined as a1 st main surface a1 and a2 nd main surface a2, a pair of outer surfaces facing each other in the width direction W is defined as a1 st side surface B1 and a2 nd side surface B2, and a pair of outer surfaces facing each other in the longitudinal direction L is defined as a1 st end surface C1 and a2 nd end surface C2 of the laminate 2. Fig. 2 is a cross section passing through the center in the width direction W and extending in the stacking direction T and the longitudinal direction L.
In addition, when it is not necessary to particularly distinguish between the 1 st main surface a1 and the 2 nd main surface a2, the description will be given collectively as the main surface a, when it is not necessary to particularly distinguish between the 1 st side surface B1 and the 2 nd side surface B2, the description will be given collectively as the side surface B, and when it is not necessary to particularly distinguish between the 1 st end surface C1 and the 2 nd end surface C2, the description will be given collectively as the end surface C.
(laminate 2)
The laminate 2 includes an inner layer 6 and outer layers 7 arranged on both main surfaces a of the inner layer 6.
(outer layer portion 7)
The outer layer portion 7 is disposed on the 1 st main surface a1 side and the 2 nd main surface a2 side of the inner layer portion 6, and is made of the same ceramic material as the inner dielectric layer 4 of the inner layer portion 6.
(inner layer part 6)
The inner layer 6 includes a1 st inner layer 61, a2 nd inner layer 62, and an interlayer dielectric layer 63 provided between the 1 st inner layer 61 and the 2 nd inner layer 62.
(1 st inner layer 61 and 2 nd inner layer 62)
The 1 st inner layer portion 61 and the 2 nd inner layer portion 62 alternately stack the internal dielectric layers 4 and the internal electrode layers 5. In the embodiment, the 1 st inner layer 61 is disposed on the 2 nd main surface a2 side as one main surface, and the 2 nd inner layer 62 is disposed on the 1 st main surface a1 side. In the embodiment, the thicknesses of the 1 st inner layer portion 61 and the 2 nd inner layer portion 62 are substantially equal to each other, but the present invention is not limited thereto.
(internal dielectric layer 4)
The inner dielectric layer 4 will have a composition comprising Ca (calcium) and Zr (zirconium) and represented by the general formula ABO 3 The perovskite-structured ceramic material is shown as a main component. The perovskite structure comprises ABO with off-stoichiometric composition 3 - α. For example, CaZrO can be used as the ceramic material 3 (calcium zirconate). Since the perovskite containing Ca and Zr has a small temperature change in electrostatic capacitance, it has a temperature coefficient Tc [ ppm/. degree.C ]]Such characteristics are small.
(internal electrode layer 5)
The internal electrode layer 5 is a conductive thin film containing Cu (copper) as a main component and a common material containing Ca, Zr, and O and containing no alkali metal. For example, the internal electrode layers 5 are conductive thin films containing Cu as a main component and a common material containing CaZrO 3 And does not contain alkali metals. Further, for example, the internal electrode layers 5 are conductive thin films containing Cu as a main component and a common material containing CaZrO 3 . In addition, for example, the internal electrode layers 5 are mainly composed of Cu and contain CaZrO only 3 A conductive film of a common material.
The internal electrode layers 5 include a plurality of 1 st internal electrode layers 5A and a plurality of 2 nd internal electrode layers 5B in the 1 st internal layer portion 61 and the 2 nd internal layer portion 62. The 1 st internal electrode layers 5A and the 2 nd internal electrode layers 5B are alternately arranged.
The 1 st internal electrode layer 5A includes a1 st external electrode side electrode layer 51A connected to the 1 st external electrode 3A, and a2 nd external electrode side electrode layer 52A discontinuous from the 1 st external electrode side electrode layer 51A and connected to the 2 nd external electrode 3B. The 1 st external electrode side electrode layer 51A and the 2 nd external electrode side electrode layer 52A are insulated from each other and formed on the same plane. In the 1 st internal electrode layer 5A, the 1 st external electrode side electrode layer 51A is longer than the 2 nd external electrode side electrode layer 52A.
The 2 nd internal electrode layer 5B includes a1 st external electrode side electrode layer 51B connected to the 1 st external electrode 3A and a2 nd external electrode side electrode layer 52B discontinuous from the 1 st external electrode side electrode layer 51B and connected to the 2 nd external electrode 3B. The 1 st external electrode side electrode layer 51B and the 2 nd external electrode side electrode layer 52B are insulated from each other and formed on the same plane. In the 2 nd internal electrode layer 5B, the 2 nd external electrode side electrode layer 52B is longer than the 1 st external electrode side electrode layer 51B.
The 1 st external electrode side electrode layer 51A of the 1 st internal electrode layer 5A and the 2 nd external electrode side electrode layer 52B of the 2 nd internal electrode layer 5B adjacent to the 1 st internal electrode layer 5A are both longer electrode layers, and have an overlapping region P overlapping each other at a central portion in the longitudinal direction L. Between the 1 st external electrode side electrode layer 51A and the 2 nd external electrode side electrode layer 52B facing each other in the overlap region P, a portion functioning as a capacitor by accumulating electric charges is formed.
The thickness of the internal dielectric layers 4 in the stacking direction T of the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B facing each other including the overlap region P in the 1 st inner layer 61 or the 2 nd inner layer 62 is 2 μm or more and 50 μm or less. The thickness of the internal electrode layers 5 in the stacking direction T is 0.7 μm or more and 2 μm or less. These thicknesses are determined as follows.
First, an LT cross section passing through the center of the multilayer ceramic capacitor 1 is polished to expose the inner layer portion 6. If necessary, the exposed cross section is etched at the observation position to remove the conductor layer stretched by polishing.
Fig. 4 is an enlarged cross-sectional view of the portion of the exposed 1 st inner layer portion 61 or 2 nd inner layer portion 62 where the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B face each other. In the enlarged image shown in the figure, for example, a plurality of straight lines La, Lb, Lc, Ld, Le extending in the stacking direction T are drawn at equal intervals of the pitch S. The pitch S is preferably about 5 to 10 times the thickness of the internal electrode layer 5 to be measured, and for example, when the internal electrode layer 5 having a thickness of about 1 μm is measured, the pitch S is set to 5 μm.
Next, the thicknesses da, db, dc, dd, and de of the internal electrode layers 5 are measured on each of the 5 straight lines La, Lb, Lc, Ld, and Le. However, in the case where the internal electrode layers 5 are broken on the straight lines La, Lb, Lc, Ld, Le and the internal dielectric layers 4 sandwiching the internal electrode layers 5 are connected to each other, or in the case where an enlarged view of the measurement position is unclear, a new straight line is drawn and the thickness of the internal electrode layer 5 is measured.
Then, for example, the thickness of 5 or more internal electrode layers 5 is measured by the above-described method for 5 internal electrode layers 5, and when the number of stacked internal electrode layers 5 is less than 5, the thickness is measured by the above-described method for all internal electrode layers 5, and the average value thereof is defined as the average thickness of the plurality of internal electrode layers 5.
The thickness of the internal dielectric layers 4 can also be determined by measuring and averaging the thicknesses Da, Db, Dc, Dd, and De of the respective internal dielectric layers 4 on each of the 5 straight lines La, Lb, Lc, Ld, and Le, similarly to the internal electrode layers 5.
(bending part Q)
The inner electrode layer 5 closest to the 2 nd main surface a2 in the 1 st inner layer portion 61 is the 1 st inner electrode layer 5A. Of the 1 st external electrode-side electrode layer 51A of the 1 st internal electrode layer 5A, a bent portion Q is provided at a portion of the 2 nd internal electrode layer 5B adjacent to the 1 st external electrode-side electrode layer 51B, which does not extend. That is, the bent portion Q is provided in a non-overlapping region of the 1 st external electrode side electrode layer 51A of the 1 st internal electrode layer 5A, which does not overlap with the 1 st external electrode side electrode layer 51B of the 2 nd internal electrode layer 5B adjacent in the stacking direction T. The bent portion Q is bent convexly toward the 1 st main surface a1 side in the stacking direction T.
(intermediate dielectric layer 63)
The thickness of the intermediate dielectric layer 63 provided between the 1 st inner layer 61 and the 2 nd inner layer 62 in the stacking direction T is greater than the thickness of the inner dielectric layer 4, for example, by a factor of 3 to 10.
(side spacer 8)
As shown in fig. 3, the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are not exposed at the side surface B in the width direction W of the laminate 2, and this portion becomes the side spacer 8.
(external electrode 3)
The external electrode 3 includes a1 st external electrode 3A provided on the 1 st end face C1 of the laminate 2 and a2 nd external electrode 3B provided on the 2 nd end face C2 of the laminate 2. In addition, when it is not necessary to particularly distinguish between the 1 st external electrode 3A and the 2 nd external electrode 3B, the description will be made collectively as the external electrodes 3.
(method of manufacturing multilayer ceramic capacitor 1)
Fig. 5 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment.
(ceramic Green sheet printing Process S1)
In step S1, internal electrode layer patterns to be the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are printed on a band-shaped ceramic green sheet obtained by molding a ceramic slurry into a sheet shape on a carrier film. Thus, the raw material sheet for the 1 st inner layer portion 61 and the raw material sheet for the 2 nd inner layer portion 62 are produced.
(laminating step S2)
In step S2, a plurality of raw material sheets for the 1 st inner layer portion 61 are stacked to produce a stacked raw material sheet for the 1 st inner layer portion 61. A plurality of the raw material sheets for the 2 nd inner layer portion 62 are similarly stacked, thereby manufacturing a stacked raw material sheet for the 2 nd inner layer portion 62. Then, for example, the lamination raw material sheet for the 1 st inner layer portion 61 is pressed so that the bent portion Q is provided in a portion of the 1 st external electrode side electrode layer 51A of the 1 st inner electrode layer 5A closest to the 2 nd main surface a2 side.
Further, ceramic green sheets for the intermediate dielectric layers 63 are disposed between the lamination raw material sheets for the 1 st inner layer portion 61 and the lamination raw material sheets for the 2 nd inner layer portion 62, and further, ceramic green sheets for the outer layer portions to be the outer layer portions 7 are stacked on both sides of these lamination raw material sheets in the lamination direction T, respectively.
(Master batch Forming Process S3)
Next, in step S3, a master block is formed by thermocompression bonding the laminated lamination material sheets in the lamination direction T. At this time, the material of the ceramic green sheets for the outer layer portion flows so as to fill the bent portion Q of the laminated raw material sheet for the 1 st inner layer portion 61.
(Master block dividing step S4)
Next, in step S4, the mother block is divided to produce a plurality of laminated bodies 2.
(external electrode Forming Process S5)
In step S5, the external electrodes 3 are formed on both ends of the laminate 2.
(firing step S6)
Then, in step S6, the laminated ceramic capacitor 1 shown in fig. 1 is manufactured by heating at the set firing temperature for a given time in a nitrogen atmosphere and firing the external electrodes 3 to the laminate 2.
(effects of the embodiment)
Generally, in a multilayer ceramic capacitor, peeling easily occurs between an inner layer portion and an outer layer portion and at an interface where an internal dielectric layer and an internal electrode layer are laminated.
However, according to the multilayer ceramic capacitor 1 of the present embodiment, the bent portion Q is provided in the 1 st outer electrode side electrode layer 51A of the 1 st inner electrode layer 5A closest to the 2 nd main surface a2 of the 1 st inner layer portion 61. The bent portion Q is provided at a portion of the adjacent 2 nd internal electrode layer 5B to which the 1 st external electrode side electrode layer 51B does not extend.
As described above, since the outer layer portion 7 and the 1 st inner layer portion 61 are improved in adhesion by providing the bent portion Q, the multilayer ceramic capacitor 1 according to the embodiment is less likely to be peeled off.
Further, according to the laminated ceramic capacitor 1 of the present embodiment, the intermediate dielectric layer 63 is provided between the 1 st inner layer portion 61 and the 2 nd inner layer portion 62. The thickness of the intermediate dielectric layer 63 in the stacking direction T is greater than that of the internal dielectric layer 4.
Peeling is also likely to occur in the central portion of the laminated ceramic capacitor in the laminating direction T, and the laminated ceramic capacitor 1 of the embodiment is provided with the intermediate dielectric layer 63 in the substantially central portion. Since the intermediate dielectric layer 63 is thicker than the other dielectric layers, the possibility of peeling at this portion is low. Therefore, the possibility of delamination of the multilayer ceramic capacitor 1 of the embodiment is further reduced.
The 2 nd external electrode side electrode layer 52A of the 1 st internal electrode layer 5A and the 1 st external electrode side electrode layer 51B of the 2 nd internal electrode layer 5B are dummy electrodes. The dummy electrode is formed of the same metal as the internal electrode layer 5, and thus has good connectivity with the external electrode 3. Therefore, the connection strength of the external electrode 3 to the laminate 2 is improved.
While the preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and various modifications can be made.
Claims (5)
1. A laminated ceramic capacitor is characterized in that,
the disclosed device is provided with: a laminate including a1 st inner layer portion and a2 nd inner layer portion in which the internal dielectric layers and the internal electrode layers are alternately laminated; a1 st external electrode disposed in one of longitudinal directions of the laminate orthogonal to the lamination direction; and a2 nd external electrode disposed on the other side in the longitudinal direction,
the internal electrode layer has: an overlap region overlapping with the internal electrode layers adjacent in the stacking direction; and a non-overlapping region not overlapping with the internal electrode layers adjacent in the stacking direction,
the 1 st inner layer portion is located on one principal surface side in the stacking direction in the stacked body,
the internal electrode layer closest to the one main surface side of the 1 st internal layer portion has a bent portion bent in the stacking direction in the non-overlapping region.
2. The laminated ceramic capacitor according to claim 1,
the internal electrode layers are alternately arranged with 1 st and 2 nd internal electrode layers,
among the 1 st internal electrode layers, a1 st external electrode side electrode layer connected to the 1 st external electrode is longer than a2 nd external electrode side electrode layer which is discontinuous with the 1 st external electrode side electrode layer and connected to the 2 nd external electrode,
among the 2 nd internal electrode layers, the 2 nd external electrode side electrode layer is longer than the 1 st external electrode side electrode layer,
the 1 st external electrode side electrode layer of the 1 st internal electrode layer and the 2 nd external electrode side electrode layer of the 2 nd internal electrode layer overlap at a central portion in the longitudinal direction,
the bent portion is provided in a portion of the 1 st external electrode side electrode layer of the 1 st internal electrode layer, to which the 1 st external electrode side electrode layer of the 2 nd internal electrode layer does not extend.
3. The laminated ceramic capacitor according to claim 1 or claim 2,
an intermediate dielectric layer is provided between the 1 st inner layer portion and the 2 nd inner layer portion,
the thickness of the intermediate dielectric layer in the stacking direction is greater than the thickness of the internal dielectric layer.
4. The laminated ceramic capacitor according to any one of claims 1 to 3,
the thickness of the internal dielectric layer is 2 [ mu ] m or more and 50 [ mu ] m or less.
5. The laminated ceramic capacitor according to any one of claims 1 to 3,
the thickness of the internal electrode layer is 0.7 [ mu ] m or more and 2 [ mu ] m or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221113181.5U CN217521858U (en) | 2022-05-10 | 2022-05-10 | Multilayer ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221113181.5U CN217521858U (en) | 2022-05-10 | 2022-05-10 | Multilayer ceramic capacitor |
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| Publication Number | Publication Date |
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| CN217521858U true CN217521858U (en) | 2022-09-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221113181.5U Active CN217521858U (en) | 2022-05-10 | 2022-05-10 | Multilayer ceramic capacitor |
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| Country | Link |
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| CN (1) | CN217521858U (en) |
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- 2022-05-10 CN CN202221113181.5U patent/CN217521858U/en active Active
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