CN215527479U - Multilayer ceramic capacitor - Google Patents
Multilayer ceramic capacitor Download PDFInfo
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- CN215527479U CN215527479U CN202121462294.1U CN202121462294U CN215527479U CN 215527479 U CN215527479 U CN 215527479U CN 202121462294 U CN202121462294 U CN 202121462294U CN 215527479 U CN215527479 U CN 215527479U
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Abstract
The utility model provides a laminated ceramic capacitor with improved adhesion between a base electrode layer and a coating layer. A multilayer ceramic capacitor is provided with: a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated with each other, the laminate having principal surfaces on both sides in a lamination direction, end surfaces on both sides in a longitudinal direction intersecting the lamination direction, and side surfaces on both sides in a width direction intersecting the lamination direction and the longitudinal direction; and an external electrode having a base electrode layer that covers the end surfaces provided on both sides of the laminate and a part of the end surface sides of the main surface and the side surfaces that are continuous from the end surfaces, respectively, and a covering layer that covers an outer surface of the base electrode layer and has a connection portion that penetrates the base electrode layer and extends to the laminate.
Description
Technical Field
The present invention relates to a laminated ceramic capacitor.
Background
A multilayer ceramic capacitor is provided with a multilayer body and external electrodes provided on both end faces of the multilayer body, wherein the multilayer body is provided with: an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked; and an outer layer section disposed on both sides of the inner layer section in the stacking direction. The external electrode is provided with a base electrode layer, and the outer surface of the base electrode layer is provided with another coating layer such as a plating layer. In such a laminated ceramic capacitor, peeling of the coating layer has been a problem in the past (see patent document 1).
Prior art documents
Patent document
Patent document 1: japanese laid-open patent publication No. 2006-295077
SUMMERY OF THE UTILITY MODEL
Problem to be solved by utility model
The present invention aims to provide a laminated ceramic capacitor with improved adhesion of coating layers.
Means for solving the problems
In order to solve the above problem, the present invention provides a multilayer ceramic capacitor including: a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated with each other, the laminate having principal surfaces on both sides in a lamination direction, end surfaces on both sides in a longitudinal direction intersecting the lamination direction, and side surfaces on both sides in a width direction intersecting the lamination direction and the longitudinal direction; and an external electrode having a base electrode layer that covers the end surfaces provided on both sides of the laminate and a part of the end surface sides of the main surface and the side surfaces that are continuous from the end surfaces, respectively, and a covering layer that covers an outer surface of the base electrode layer and has a connection portion that penetrates the base electrode layer and extends to the laminate.
Effect of the utility model
According to the present invention, a multilayer ceramic capacitor having improved adhesion to a coating layer can be provided.
Drawings
Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1.
Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II.
Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.
Fig. 4 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line IV-IV.
Fig. 5 is a flowchart illustrating a method of manufacturing the laminated ceramic capacitor 1.
Description of the reference numerals
1: a laminated ceramic capacitor;
2: a laminate;
3: an external electrode;
4: a dielectric layer;
5: an internal electrode layer;
6: an inner layer portion;
7: an outer layer part;
31: a base electrode layer;
31A: 1 st base electrode layer;
31B: the 2 nd base electrode layer;
32: plating a coating layer;
32 a: a nickel plating layer;
32 b: a tin plating layer;
33: a connecting portion.
Detailed Description
The multilayer ceramic capacitor 1 according to the embodiment of the present invention will be described below. Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1. Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II. Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III. Fig. 4 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line IV-IV.
(multilayer ceramic capacitor 1)
The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape, and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The laminate 2 includes an internal layer portion 6 in which a plurality of dielectric layers 4 and a plurality of internal electrode layers 5 are laminated.
In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1 is referred to as the longitudinal direction L. The direction in which the dielectric layers 4 and the internal electrode layers 5 are stacked is referred to as a stacking direction T. A direction intersecting both the longitudinal direction L and the stacking direction T is defined as a width direction W. In the embodiment, the width direction W is orthogonal to both the longitudinal direction L and the stacking direction T.
Further, among the 6 outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the lamination direction T is defined as a1 st main surface a1 and a2 nd main surface a2, a pair of outer surfaces facing each other in the width direction W is defined as a1 st side surface B1 and a2 nd side surface B2, and a pair of outer surfaces facing each other in the longitudinal direction L is not defined as a1 st end surface C1 and a2 nd end surface C2 of the laminate 2. Fig. 2 is a cross section passing through the center in the width direction W and extending in the stacking direction T and the longitudinal direction L.
In addition, when the explanation is made without particularly distinguishing the 1 st main surface a1 from the 2 nd main surface a2, the explanation is made collectively as the main surface a, when the explanation is made without particularly distinguishing the 1 st side surface B1 from the 2 nd side surface B2, the explanation is made collectively as the side surface B, and when the explanation is made without particularly distinguishing the 1 st end surface C1 from the 2 nd end surface C2, the explanation is made collectively as the end surface C.
(laminate 2)
The laminate 2 includes an inner layer 6 and outer layers 7 arranged on both main surfaces a of the inner layer 6. Further, with respect to the laminated body 2 of the embodiment, for example, the length in the lamination direction T is 0.2mm to 0.22mm, the length in the longitudinal direction L is 0.41mm to 0.44mm, and the length in the width direction W is 0.2mm to 0.22 mm.
In the laminate 2 of the embodiment, the length in the lamination direction T may be 0.3mm to 0.33mm, the length in the longitudinal direction L may be 0.6mm to 0.66mm, and the length in the width direction W may be 0.3mm to 0.33 mm.
Further, in the laminate 2 of the embodiment, the length in the lamination direction T may be 0.5mm to 0.55mm, the length in the longitudinal direction L may be 1.0mm to 1.10mm, and the length in the width direction W may be 0.5mm to 0.55 mm.
(inner layer part 6)
The inner layer portion 6 is formed by stacking a plurality of dielectric layers 4 and a plurality of internal electrode layers 5. The inner layer portion 6 includes 30 or more and 50 or less internal electrode layers 5 and dielectric layers 4, respectively.
(outer layer portion 7)
The outer layer portion 7 is disposed on the 1 st main surface a1 side and the 2 nd main surface a2 side of the inner layer portion 6, and is made of the same ceramic material as the dielectric layer 4 of the inner layer portion 6.
(dielectric layer 4)
The thickness of the dielectric layer 4 in the stacking direction T is, for example, 0.7 μm to 1.0 μm. Further, it may be 1.0 μm to 1.2 μm, and may be 3.0 μm to 3.3 μm. The dielectric layer 4 is made of barium titanate (BaTiO)3) Etc. ceramic material.
(internal electrode layer 5)
The thickness of the internal electrode layers 5 of the embodiment in the stacking direction T is 0.5 μm to 1.0 μ n. The internal electrode layers 5 include a plurality of 1 st internal electrode layers 5A and a plurality of 2 nd internal electrode layers 5B. The 1 st internal electrode layers 5A and the 2 nd internal electrode layers 5B are alternately arranged. In addition, when the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are described without particularly distinguishing them, they will be collectively referred to as the internal electrode layers 5.
The 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are alternately arranged with the dielectric layer 4 interposed therebetween. The 1 st and 2 nd internal electrode layers 5A and 5B are opposite in the longitudinal direction L, but have the same shape and the same size.
The 1 st internal electrode layer 5A includes a1 st facing portion 5Aa facing the 2 nd internal electrode layer 5B and a1 st lead-out portion 5Ab led out from the 1 st facing portion 5Aa toward the 1 st end face C1 side. The end of the 1 st lead portion 5Ab is exposed at the 1 st end face C1 and is electrically connected to the 1 st underlying electrode layer 31A, which will be described later.
The 2 nd internal electrode layer 5B includes a2 nd opposing portion 5Ba opposing the 1 st internal electrode layer 5A and a2 nd lead-out portion 5Bb led out from the 2 nd opposing portion 5Ba to the 2 nd end face C2. The end of the 2 nd lead portion 5Bb is electrically connected to the 2 nd underlying electrode layer 31B described later.
The charge is accumulated in the 1 st opposed portion 5Aa of the 1 st internal electrode layer 5A and the 2 nd opposed portion 5Ba of the 2 nd internal electrode layer 5B, and the capacitor characteristic is exhibited.
In the following description, the 1 st facing portion 5Aa and the 2 nd facing portion 5Ba will be collectively referred to as the facing portion 5a without being particularly distinguished. When the 1 st lead-out portion 5Ab and the 2 nd lead-out portion 5Bb are not particularly described separately, they will be collectively referred to as the 1 st lead-out portion 5 b.
As shown in fig. 3, the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are not exposed at the side surface B in the width direction W of the laminate 2, and this portion becomes a side gap portion.
(external electrode 3)
The external electrode 3 includes a1 st external electrode 3A provided on the 1 st end face C1 of the laminate 2 and a2 nd external electrode 3B provided on the 2 nd end face C2 of the laminate 2. In addition, when the 1 st external electrode 3A and the 2 nd external electrode 3B are described without particularly distinguishing them, they will be collectively referred to as the external electrodes 3. The external electrode 3 covers not only the end face C but also a part of the principal face a and the side face B on the side of the end face C. The external electrode 3 includes a base electrode layer 31 and a plating layer 32 as a coating layer.
(underlying electrode layer 31)
The underlying electrode layer 31 is formed by, for example, applying and baking a conductive paste containing a conductive metal and glass.
(plating layer 32)
A plating layer 32 is formed as a coating layer on the outer surface of the base electrode layer 31. The plating layer 32 includes a nickel plating layer 32a and a tin plating layer 32 b. The nickel plating layer 32a is a plating layer of nickel or an alloy containing nickel. The tin plating layer 32b is a plating layer of tin or an alloy containing tin.
(method of manufacturing multilayer ceramic capacitor 1)
Fig. 5 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment.
(ceramic Green sheet printing Process S1)
As shown in the drawing, in step S1, an internal electrode layer pattern to be the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B is printed on a band-shaped ceramic green sheet formed by molding a ceramic slurry containing a ceramic powder, a binder, and a solvent into a sheet shape on a mounting film.
(laminating step S2)
In step S2, a plurality of raw material sheets are stacked such that the internal electrode layer patterns are shifted by half a pitch in the longitudinal direction L between the raw material sheets adjacent to each other in the stacking direction T. Further, ceramic green sheets for the outer layer portion to be the outer layer portion 7 are stacked on both sides in the stacking direction T of the raw material sheets stacked in plural.
(Master batch Forming Process S3)
Next, in step S3, a mother block is formed by thermocompression bonding a product in which ceramic green sheets for an outer layer portion to be the outer layer portion 7 are stacked on both sides in the stacking direction T of the raw material sheets stacked in plural.
(Master block dividing step S4)
Next, in step S4, the mother block is divided into a plurality of laminates 2.
(base electrode layer Forming step S5)
In step S5, the underlying electrode layers 31 are formed on both ends of the laminate 2.
(plating layer Forming step S6)
Then, in step S6, the plating layer 32 including the nickel plating layer 32a and the tin plating layer 32b is formed, and the multilayer ceramic capacitor 1 shown in fig. 1 is manufactured.
In the embodiment, two layers, i.e., a nickel plating layer 32a as a base side plating layer provided on the outer surface of the base electrode layer 31 and a tin plating layer 32b as a surface plating layer provided on the outer surface of the nickel plating layer 32a, are arranged in the plating layer 32 as a coating layer. However, the present invention is not limited thereto, and may be a multilayer having 2 or more layers. Further, the nickel plating layer 32a is thinner than the tin plating layer 32 b.
The nickel plating layer 32a has a plurality of connection portions 33 that penetrate the base electrode layer 31 and extend to the stacked body 2. The connection portion 33 extends to the end face C of the laminate 2 and is connected to the lead portion 5b of the internal electrode layer 5 or the dielectric layer 4. The connection portion 33 is also formed in a portion on the side of the end face C of the main surface a and the side surface B extending from the external electrode 3, and is also connected to the upper layer portion 7 or the side spacer portion of the laminate 2.
The connecting portions 33 are disposed more outward than the central portion of the end face C of the stacked body 2.
Fig. 2 is a cross-sectional view passing through the center in the width direction W and extending in the longitudinal direction L and the stacking direction T. The central portion of the end face C of the laminate 2 is a central portion obtained by trisecting the end face C in the lamination direction T, and the outer portion is a portion located on the 1 st main face a1 and the 2 nd main face a2 side on both sides of the central portion obtained by trisecting.
Fig. 4 is a cross-sectional view passing through the center of the stacking direction T and extending in the longitudinal direction L and the width direction WT. The central portion of the end face C of the laminated body 2 is a central portion obtained by trisecting the end face C in the width direction W, and the outer portion is a portion located on the 1 st side face B1 and the 2 nd side face B2 side of the central portion obtained by trisecting.
As described above, according to the embodiment, the nickel plating layer 32a has the connection portion 33 that penetrates the base electrode layer 31 and extends to the stacked body 2. The connection portion 33 functions as an "anchor" for firmly connecting the base electrode layer 31 and the nickel plating layer 32 a. This anchor effect can improve the adhesion between the nickel plating layer 32a and the underlying electrode layer 31. Therefore, the plating layer 32 becomes less likely to peel off from the underlying electrode layer 31. Further, the connecting portions 33 are disposed more outside the end face C of the laminated body 2 where the peeling of the plating layer 32 is particularly likely to occur, and therefore the peeling prevention effect is high. Further, the connection portion 33 is formed also in the portion on the side of the end face C of the main surface a and the side surface B where peeling of the plating layer 32 starts to occur, and therefore, the peeling prevention effect can be further improved.
While the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made. For example, although the plating layer 32 is a coating layer in the embodiment, the present invention is not limited thereto, and may be a conductive resin layer or the like.
Claims (12)
1. A multilayer ceramic capacitor is characterized by comprising:
a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated with each other, the laminate having principal surfaces on both sides in a lamination direction, end surfaces on both sides in a longitudinal direction intersecting the lamination direction, and side surfaces on both sides in a width direction intersecting the lamination direction and the longitudinal direction; and
and an external electrode including a base electrode layer that covers the end surfaces provided on both sides of the laminate and a part of the end surface sides of the main surface and the side surfaces that are continuous from the end surfaces, and a coating layer that covers an outer surface of the base electrode layer and includes a connection portion that penetrates the base electrode layer and extends to the laminate.
2. The laminated ceramic capacitor according to claim 1,
the connection portion is connected to the internal electrode layer in the stacked body.
3. The laminated ceramic capacitor according to claim 1 or claim 2,
the coating layer is provided with a plurality of layers.
4. The laminated ceramic capacitor according to claim 1 or claim 2,
the connecting portion is disposed more outward of a central portion in the width direction in the end surface, and more outward of a central portion in the stacking direction in the end surface.
5. The laminated ceramic capacitor according to claim 1 or claim 2,
the coating layer is a plating layer, and includes a base-side plating layer on the base electrode layer side and a surface plating layer provided outside the base-side plating layer, and the base-side plating layer is thinner than the surface plating layer.
6. The laminated ceramic capacitor according to claim 1 or claim 2,
the length in the stacking direction is 0.2mm to 0.22mm,
the length in the length direction is 0.41mm to 0.44mm,
the length in the width direction is 0.2mm to 0.22 mm.
7. The laminated ceramic capacitor according to claim 1 or claim 2,
the length in the stacking direction is 0.3mm to 0.33mm,
the length in the length direction is 0.6mm to 0.66mm,
the length in the width direction is 0.3mm to 0.33 mm.
8. The laminated ceramic capacitor according to claim 1 or claim 2,
the length in the stacking direction is 0.5mm to 0.55mm,
the length in the length direction is 1.0mm to 1.10mm,
the length in the width direction is 0.5mm to 0.55 mm.
9. The laminated ceramic capacitor according to claim 1 or claim 2,
the dielectric layer has a thickness of 0.7 to 1.0 [ mu ] m in the stacking direction.
10. The laminated ceramic capacitor according to claim 1 or claim 2,
the thickness of the dielectric layer in the stacking direction is 1.0 [ mu ] m to 1.2 [ mu ] m.
11. The laminated ceramic capacitor according to claim 1 or claim 2,
the thickness of the dielectric layer in the stacking direction is 3.0 μm to 3.3 μm.
12. The laminated ceramic capacitor according to claim 1 or claim 2,
the thickness of the internal electrode layers in the stacking direction is 0.5 μm to 1.0 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121462294.1U CN215527479U (en) | 2021-06-29 | 2021-06-29 | Multilayer ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121462294.1U CN215527479U (en) | 2021-06-29 | 2021-06-29 | Multilayer ceramic capacitor |
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| Publication Number | Publication Date |
|---|---|
| CN215527479U true CN215527479U (en) | 2022-01-14 |
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| CN202121462294.1U Active CN215527479U (en) | 2021-06-29 | 2021-06-29 | Multilayer ceramic capacitor |
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|---|---|
| CN (1) | CN215527479U (en) |
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- 2021-06-29 CN CN202121462294.1U patent/CN215527479U/en active Active
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