CN216119930U - Multilayer ceramic capacitor - Google Patents

Abstract

The utility model provides a laminated ceramic capacitor with improved durability to external stress. A multilayer ceramic capacitor (1) is provided with: a laminated body (2) including a plurality of dielectric layers (4) and a plurality of internal electrode layers (5) which are alternately laminated; and an external electrode (3) having a base electrode layer (31) that covers both end surfaces (C) of the laminate (2) and that includes a metal (33) and a glass (34), wherein a metal internal space (35) is provided in the metal (33) and a glass internal space (36) is provided in the glass (34) in the base electrode layer (31), and the metal internal space (35) is smaller than the glass internal space (36).

Description

Multilayer ceramic capacitor

Technical Field

The present invention relates to a laminated ceramic capacitor.

Background

A multilayer ceramic capacitor is provided with: a laminate body including an inner layer portion in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated; and external electrodes provided on both end surfaces of the laminate. The external electrode includes a base electrode layer and a plating layer provided on an outer surface of the base electrode layer. The base electrode layer is generally formed by applying a conductive paste containing metal particles and glass particles to the laminate and then sintering the applied paste.

Conventionally, there is a laminated ceramic capacitor in which a gap is provided in glass included in a base electrode layer in order to flexibly deform the base electrode layer and relieve thermal stress or mechanical stress when the stress is applied from the outside (see patent document 1).

Prior art documents

Patent document

Patent document 1: japanese laid-open patent publication No. 5-3132

SUMMERY OF THE UTILITY MODEL

Problem to be solved by utility model

The present invention aims to provide a multilayer ceramic capacitor having further improved durability against external stress.

Means for solving the problems

In order to solve the above problem, the present invention provides a multilayer ceramic capacitor including: a stacked body including a plurality of dielectric layers and a plurality of internal electrode layers that are alternately stacked; and an external electrode having a base electrode layer that covers both end surfaces of the laminate and includes metal and glass, wherein a metal internal space is provided in the metal in the base electrode layer, and a glass internal space is provided in the glass, and the metal internal space is smaller than the glass internal space.

Effect of the utility model

According to the present invention, a laminated ceramic capacitor having improved durability against external stress can be provided.

Drawings

Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1.

Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II.

Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.

Fig. 4 is an enlarged view of a portion of the encircled region S of fig. 2.

Fig. 5 is a flowchart illustrating a method of manufacturing the laminated ceramic capacitor 1.

Description of the reference numerals

1: a laminated ceramic capacitor;

2: a laminate;

3: an external electrode;

5: an internal electrode layer;

4: a dielectric layer;

6: an inner layer portion;

7: an outer layer part;

31: a base electrode layer;

32: plating a coating layer;

33: a metal;

34: glass;

35: a metal inner void;

36: a space in the glass.

Detailed Description

The multilayer ceramic capacitor 1 according to the embodiment of the present invention will be described below. Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1. Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II. Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.

(multilayer ceramic capacitor 1)

The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape, and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The laminate 2 includes an internal layer portion 6 in which a plurality of dielectric layers 4 and a plurality of internal electrode layers 5 are laminated.

In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1 is referred to as the longitudinal direction L. The direction in which the dielectric layers 4 and the internal electrode layers 5 are stacked is referred to as a stacking direction T. A direction intersecting both the longitudinal direction L and the stacking direction T is defined as a width direction W. In the embodiment, the width direction W is orthogonal to both the longitudinal direction L and the stacking direction T.

Among the 6 outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the lamination direction T are defined as a1 st main surface a1 and a2 nd main surface a2, a pair of outer surfaces facing each other in the width direction W are defined as a1 st side surface B1 and a2 nd side surface B2, and a pair of outer surfaces facing each other in the longitudinal direction L are defined as a1 st end surface C1 and a2 nd end surface C2 of the laminate 2. Fig. 2 is a cross section passing through the center in the width direction W and extending in the stacking direction T and the longitudinal direction L.

In addition, when the explanation is made without particularly distinguishing the 1 st main surface a1 from the 2 nd main surface a2, the explanation is made collectively as the main surface a, when the explanation is made without particularly distinguishing the 1 st side surface B1 from the 2 nd side surface B2, the explanation is made collectively as the side surface B, and when the explanation is made without particularly distinguishing the 1 st end surface C1 from the 2 nd end surface C2, the explanation is made collectively as the end surface C.

(laminate 2)

The laminate 2 includes an inner layer 6 and outer layers 7 arranged on both main surfaces a of the inner layer 6. Further, with the laminate 2 of the embodiment, the length in the lamination direction T is 200 μm to 230 μm, the length in the longitudinal direction L is 380 μm to 440 μm, and the length in the width direction W is 200 μm to 230 μm.

(inner layer part 6)

The inner layer portion 6 is formed by stacking a plurality of dielectric layers 4 and a plurality of internal electrode layers 5. The inner layer portion 6 includes 30 or more and 50 or less internal electrode layers 5 and dielectric layers 4, respectively.

(outer layer portion 7)

The outer layer portion 7 is disposed on the 1 st main surface a1 side and the 2 nd main surface a2 side of the inner layer portion 6, and is made of the same ceramic material as the dielectric layer 4 of the inner layer portion 6.

(dielectric layer 4)

The thickness of the dielectric layer 4 in the stacking direction T is 0.8 μm to 1.1 μm. The dielectric layer 4 is made of barium titanate (BaTiO)₃) Etc. ceramic material.

(internal electrode layer 5)

The thickness of the internal electrode layers 5 of the embodiment in the stacking direction T is 0.55 μm to 0.7 μm. The internal electrode layers 5 include a plurality of 1 st internal electrode layers 5A and a plurality of 2 nd internal electrode layers 5B. The 1 st internal electrode layers 5A and the 2 nd internal electrode layers 5B are alternately arranged. In addition, when the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are described without particularly distinguishing them, they will be collectively referred to as the internal electrode layers 5.

The 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are alternately arranged with the dielectric layer 4 interposed therebetween. The 1 st and 2 nd internal electrode layers 5A and 5B are opposite in the longitudinal direction L, but have the same shape and the same size.

The 1 st internal electrode layer 5A includes a1 st facing portion 5Aa facing the 2 nd internal electrode layer 5B and a1 st lead-out portion 5Ab led out from the 1 st facing portion 5Aa toward the 1 st end face C1 side. The end of the 1 st lead portion 5Ab is exposed at the 1 st end face C1 and is electrically connected to the 1 st underlying electrode layer 31A, which will be described later.

The 2 nd internal electrode layer 5B includes a2 nd opposing portion 5Ba opposing the 1 st internal electrode layer 5A and a2 nd lead-out portion 5Bb led out from the 2 nd opposing portion 5Ba to the 2 nd end face C2. The end of the 2 nd lead portion 5Bb is electrically connected to the 2 nd underlying electrode layer 31B described later.

The charge is accumulated in the 1 st opposed portion 5Aa of the 1 st internal electrode layer 5A and the 2 nd opposed portion 5Ba of the 2 nd internal electrode layer 5B, and the capacitor characteristic is exhibited.

In the following description, the 1 st facing portion 5Aa and the 2 nd facing portion 5Ba will be collectively referred to as the facing portion 5a without being particularly distinguished. When the 1 st lead-out portion 5Ab and the 2 nd lead-out portion 5Bb are not particularly described separately, they will be collectively referred to as the 1 st lead-out portion 5 b.

As shown in fig. 3, the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are not exposed at the side surface B in the width direction W of the laminate 2, and this portion becomes a side gap portion.

(external electrode 3)

The external electrode 3 includes a1 st external electrode 3A provided on the 1 st end face C1 of the laminate 2 and a2 nd external electrode 3B provided on the 2 nd end face C2 of the laminate 2. In addition, when the 1 st external electrode 3A and the 2 nd external electrode 3B are described without particularly distinguishing them, they will be collectively referred to as the external electrodes 3. The external electrode 3 covers not only the end face C but also a part of the principal face a and the side face B on the side of the end face C. The external electrode 3 includes a base electrode layer 31 and a plating layer 32 as a coating layer.

(underlying electrode layer 31)

Fig. 4 is an enlarged view of a portion of the encircled region S of fig. 2. The underlying electrode layer 31 contains glass 34 as an additive inside a metal 33 such as copper as a base material. Further, a metal inner space 35 is provided inside the metal 33, and a glass inner space 36 is provided inside the glass 34. The metal inner voids 35 are smaller than the glass inner voids 36.

In the embodiment, fig. 2 and 4 are LT cross sections extending in the stacking direction T and the longitudinal direction L of the stacked body 2 and passing through the center in the width direction W, and fig. 4 is an enlarged view of a part of the center in the stacking direction. The metal inner voids 35 are smaller than the glass inner voids 36, which means that the average area of the metal inner voids 35 is smaller than the average area of the glass inner voids 36 in the LT cross section. Specifically, the average area of the metal inner voids 35 is 1/10 or less of the average area of the glass inner voids 36.

The metal inner voids 35 are smaller than the glass inner voids 36, and are not limited to the LT cross section, and the average area of the metal inner voids 35 may be smaller than the average area of the glass inner voids 36 in a WT cross section extending in the width direction W and the length direction L of the laminate 2 and passing through the center in the lamination direction T. Further, the average volume of the metal inner voids 35 may be smaller than the average volume of the glass inner voids 36.

(plating layer 32)

A plating layer 32 is formed as a coating layer on the outer surface of the base electrode layer 31. The plating layer 32 includes a nickel plating layer 32a and a tin plating layer 32 b. The nickel plating layer 32a is a plating layer of nickel or an alloy containing nickel. The tin plating layer 32b is a plating layer of tin or an alloy containing tin.

(method of manufacturing multilayer ceramic capacitor 1)

Fig. 5 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment.

(ceramic Green sheet printing Process S1)

As shown in the drawing, in step S1, an internal electrode layer pattern to be the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B is printed on a band-shaped ceramic green sheet formed by molding a ceramic slurry containing a ceramic powder, a binder, and a solvent into a sheet shape on a mounting film.

(laminating step S2)

In step S2, a plurality of raw material sheets are stacked such that the internal electrode layer patterns are shifted by half a pitch in the longitudinal direction L between the raw material sheets adjacent to each other in the stacking direction T. Further, ceramic green sheets for the outer layer portion to be the outer layer portion 7 are stacked on both sides in the stacking direction T of the raw material sheets stacked in plural.

(Master batch Forming Process S3)

Next, in step S3, a mother block is formed by thermocompression bonding a product in which ceramic green sheets for an outer layer portion to be the outer layer portion 7 are stacked on both sides in the stacking direction T of the raw material sheets stacked in plural.

(Master block dividing step S4)

Next, in step S4, the mother block is divided into a plurality of laminates 2.

(base electrode layer Forming step S5)

In step S5, the underlying electrode layers 31 are formed on both ends of the laminate 2. The base electrode layer forming step of step S5 includes a coating step S51 and a firing step 52.

In the coating step S51, a conductive paste is applied to both ends of the laminate 2. The conductive paste contains conductive metal particles, glass particles having a melting point higher than that of the metal, and a binder.

In the firing step S52, the temperature of the laminate 2 coated with the conductive paste at both ends is raised. Then, first, the metal particles are melted and sintered to be connected, but the metal 33 has a gap. At this time, the glass particles are not yet melted because of the high softening temperature. When the temperature of the laminate 2 is further increased, the glass particles melt and flow into the gaps between the metals 33.

Here, by adjusting the particle diameters and the temperature rise of the metal particles and the glass particles, the molten glass does not completely fill the gap existing inside the metal 33, but a minute metal void 35 remains.

The portion of the region occupied by the glass particles that has melted and flowed into the gap of the metal 33 becomes a void, and an internal glass void 36 is formed inside the glass 34.

In this way, the underlying electrode layer 31 including the metal 33 having the metal internal space 35 provided therein and the glass 34 having the glass internal space 36 provided therein is formed.

Here, in the LT section, the average area of the metal inner voids 35 is smaller than the average area of the glass inner voids 36. Specifically, the average area of the metal inner voids 35 is 1/10 or less of the average area of the glass inner voids 36.

(plating layer Forming step S6)

Next, in step S6, a plating layer 32 including a nickel plating layer 32a and a tin plating layer 32b is formed on the outer surface of the base electrode layer 31, and the multilayer ceramic capacitor 1 shown in fig. 1 is manufactured.

As described above, according to the embodiment, the underlying electrode layer 31 includes the metal 33 and the glass 34, the metal inner space 35 is provided inside the metal 33, and the glass inner space 36 is provided inside the glass 34.

As described above, since the underlying electrode layer 31 includes the metal internal voids 35 and the glass internal voids 36, when thermal stress or mechanical stress is applied from the outside, it can be flexibly deformed, and the stress can be relieved.

If the metal internal voids 35 are too large, the strength of the underlying electrode layer 31 is reduced, and the electrical characteristics are affected. However, in the embodiment, the metal inner space 35 is smaller than the glass inner space 36. Therefore, the durability against external stress can be improved while ensuring appropriate strength.

Further, by including the glass 34 in the base electrode layer 31, the adhesion of the base electrode layer 31 to the dielectric layer 4 of the multilayer body 2 can be improved.

While the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made. For example, a conductive resin layer or the like may be included between the plating layer 32 and the underlying electrode layer 31.

Claims (6)

1. A multilayer ceramic capacitor is characterized by comprising:

a stacked body including a plurality of dielectric layers and a plurality of internal electrode layers that are alternately stacked; and

an external electrode having base electrode layers covering end faces of both sides of the laminate and comprising metal and glass,

in the base electrode layer, a first electrode layer,

a metal inner gap is arranged in the metal,

the inner part of the glass is provided with a glass inner gap,

the metal internal voids are smaller than the glass internal voids.

2. The laminated ceramic capacitor according to claim 1,

in a cross section of the laminate extending in a lamination direction and a longitudinal direction intersecting the lamination direction and passing through a center in a width direction intersecting the lamination direction and the longitudinal direction,

the average area of the metal internal voids is smaller than the average area of the glass internal voids.

3. The laminated ceramic capacitor according to claim 2,

the average area of the metal inner voids is 1/10 or less of the average area of the glass inner voids.

4. The laminated ceramic capacitor according to claim 1 or claim 2,

the length in the stacking direction is 200 to 230 μm,

the length in the length direction is 380 μm to 440 μm,

the length in the width direction is 200 to 230 μm.

5. The laminated ceramic capacitor according to claim 1 or claim 2,

the thickness of the dielectric layer in the stacking direction is 0.8 μm to 1.1 μm.

6. The laminated ceramic capacitor according to claim 1 or claim 2,

the thickness of the internal electrode layers in the stacking direction is 0.55 to 0.7 μm.

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