CN215868985U - Multilayer ceramic capacitor - Google Patents
Multilayer ceramic capacitor Download PDFInfo
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- CN215868985U CN215868985U CN202121462321.5U CN202121462321U CN215868985U CN 215868985 U CN215868985 U CN 215868985U CN 202121462321 U CN202121462321 U CN 202121462321U CN 215868985 U CN215868985 U CN 215868985U
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Abstract
The utility model provides a laminated ceramic capacitor with a simple structure, which prevents insulation breakdown and electrostrictive deformation and improves reliability. A multilayer ceramic capacitor is provided with: a laminate body having an inner layer portion including a plurality of dielectric layers and a plurality of internal electrode layers that are alternately laminated, and outer layer portions that are respectively arranged on both sides of the inner layer portion in a lamination direction; and an external electrode covering end surfaces on both sides of the laminate, the internal layer portion having: an outer region within 10% of a thickness of the inner layer portion in the stacking direction from the outer layer portion side; and a central region which is the remaining 80% of the region other than the outer region, wherein the average thickness of the dielectric layer in the outer region is thicker than the average thickness of the dielectric layer in the central region.
Description
Technical Field
The present invention relates to a laminated ceramic capacitor.
Background
In recent years, a multilayer ceramic capacitor has been required to have a smaller size and a larger capacitance. Such a small-sized large-capacitance laminated ceramic capacitor is likely to cause dielectric breakdown and electrostrictive deformation in the dielectric layer when a high voltage is applied. When dielectric breakdown or electrostrictive deformation occurs in the dielectric layer, insulation failure occurs, and the reliability of the multilayer ceramic capacitor is lowered.
Conventionally, in order to prevent dielectric breakdown and electrostrictive deformation, a multilayer ceramic capacitor has been developed in which two inner layer portions each having a dielectric layer and an internal electrode layer are stacked, and an intermediate layer made of an insulating material is provided between the two inner layer portions. Further, in the two-divided inner layer portion, the thickness of the 1 dielectric layer located on both end sides in the stacking direction is about 2 times thicker than the thickness of the other dielectric layers. This prevents concentration of an electric field at the internal electrode layers at both ends, and prevents dielectric breakdown and electrostrictive deformation (see patent document 1).
Prior art documents
Patent document
Patent document 1: japanese patent laid-open publication No. 2016-197645
SUMMERY OF THE UTILITY MODEL
Problem to be solved by utility model
The utility model provides a multilayer ceramic capacitor with a simpler structure, which prevents insulation breakdown and electrostrictive deformation and improves reliability.
Means for solving the problems
In order to solve the above problem, the present invention provides a multilayer ceramic capacitor including: a laminate body having an inner layer portion including a plurality of dielectric layers and a plurality of internal electrode layers that are alternately laminated, and outer layer portions that are respectively arranged on both sides of the inner layer portion in a lamination direction; and an external electrode covering end surfaces on both sides of the laminate, the internal layer portion having: an outer region within 10% of a thickness of the inner layer portion in the stacking direction from the outer layer portion side; and a central region which is the remaining 80% of the region other than the outer region, wherein the average thickness of the dielectric layer in the outer region is thicker than the average thickness of the dielectric layer in the central region.
Effect of the utility model
According to the present invention, it is possible to provide a multilayer ceramic capacitor having a simple structure, in which insulation breakdown and electrostrictive deformation are prevented, and reliability is improved.
Drawings
Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1.
Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II.
Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.
Fig. 4 is a partially enlarged view of the region Q1 of fig. 2.
Fig. 5 is a partially enlarged view of the region Q2 of fig. 2.
Fig. 6 is a flowchart illustrating a method of manufacturing the laminated ceramic capacitor 1.
Description of the reference numerals
Q1: an outer region;
q2: a central region;
1: a laminated ceramic capacitor;
2: a laminate;
3: an external electrode;
4: a dielectric layer;
5: an internal electrode layer;
6: an inner layer portion;
7: an outer layer portion.
Detailed Description
The multilayer ceramic capacitor 1 according to the embodiment of the present invention will be described below. Fig. 1 is a schematic perspective view of a multilayer ceramic capacitor 1. Fig. 2 is a sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along line II-II. Fig. 3 is a cross-sectional view of the laminated ceramic capacitor 1 shown in fig. 1 taken along the line III-III.
(multilayer ceramic capacitor 1)
The multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape, and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The laminate 2 includes an internal layer portion 6 in which a plurality of dielectric layers 4 and a plurality of internal electrode layers 5 are laminated.
In the following description, as a term indicating the orientation of the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1 is referred to as the longitudinal direction L. The direction in which the dielectric layers 4 and the internal electrode layers 5 are stacked is referred to as a stacking direction T. A direction intersecting both the longitudinal direction L and the stacking direction T is defined as a width direction W. In the embodiment, the width direction W is orthogonal to both the longitudinal direction L and the stacking direction T.
Among the 6 outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the lamination direction T are defined as a1 st main surface a1 and a2 nd main surface a2, a pair of outer surfaces facing each other in the width direction W are defined as a1 st side surface B1 and a2 nd side surface B2, and a pair of outer surfaces facing each other in the longitudinal direction L are defined as a1 st end surface C1 and a2 nd end surface C2 of the laminate 2. Fig. 2 is a cross section passing through the center in the width direction W and extending in the stacking direction T and the longitudinal direction L.
In addition, when the explanation is made without particularly distinguishing the 1 st main surface a1 from the 2 nd main surface a2, the explanation is made collectively as the main surface a, when the explanation is made without particularly distinguishing the 1 st side surface B1 from the 2 nd side surface B2, the explanation is made collectively as the side surface B, and when the explanation is made without particularly distinguishing the 1 st end surface C1 from the 2 nd end surface C2, the explanation is made collectively as the end surface C.
(laminate 2)
The laminate 2 includes an inner layer 6 and outer layers 7 arranged on both main surfaces a of the inner layer 6. Further, the length of the laminate 2 of the embodiment in the lamination direction T is 0.2mm to 0.23mm, the length in the longitudinal direction L is 0.38mm to 0.44mm, and the length in the width direction W is 0.20mm to 0.23 mm.
(inner layer part 6)
The inner layer portion 6 is formed by stacking a plurality of dielectric layers 4 and a plurality of internal electrode layers 5. The inner layer portion 6 includes 30 or more and 50 or less internal electrode layers 5 and dielectric layers 4, respectively. Fig. 2 and 3 are conceptual views, and the number of dielectric layers 4 and internal electrode layers 5 shown in fig. 2 and 3 is described to be smaller than the actual number of dielectric layers in order to facilitate understanding of the structure.
(outer layer portion 7)
The outer layer portion 7 is disposed on the 1 st main surface a1 side and the 2 nd main surface a2 side of the inner layer portion 6, and is made of the same ceramic material as the dielectric layer 4 of the inner layer portion 6.
(dielectric layer 4)
The thickness of the dielectric layer 4 in the stacking direction T is 0.5 μm to 1.2 μm. The dielectric layer 4 is made of barium titanate (BaTiO)3) Etc. ceramic material.
(internal electrode layer 5)
The thickness of the internal electrode layers 5 of the embodiment in the stacking direction T is 0.55 μm to 0.8 μm. The internal electrode layers 5 include a plurality of 1 st internal electrode layers 5A and a plurality of 2 nd internal electrode layers 5B. The 1 st internal electrode layers 5A and the 2 nd internal electrode layers 5B are alternately arranged. In addition, when the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are described without particularly distinguishing them, they will be collectively referred to as the internal electrode layers 5.
The 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are alternately arranged with the dielectric layer 4 interposed therebetween. The 1 st and 2 nd internal electrode layers 5A and 5B are opposite in the longitudinal direction L, but have the same shape and the same size.
The 1 st internal electrode layer 5A includes a1 st facing portion 5Aa facing the 2 nd internal electrode layer 5B and a1 st lead-out portion 5Ab led out from the 1 st facing portion 5Aa toward the 1 st end face C1 side. The end of the 1 st lead portion 5Ab is exposed at the 1 st end face C1 and is electrically connected to the 1 st underlying electrode layer 31A, which will be described later.
The 2 nd internal electrode layer 5B includes a2 nd opposing portion 5Ba opposing the 1 st internal electrode layer 5A and a2 nd lead-out portion 5Bb led out from the 2 nd opposing portion 5Ba to the 2 nd end face C2. The end of the 2 nd lead portion 5Bb is electrically connected to the 2 nd underlying electrode layer 31B described later.
The charge is accumulated in the 1 st opposed portion 5Aa of the 1 st internal electrode layer 5A and the 2 nd opposed portion 5Ba of the 2 nd internal electrode layer 5B, and the capacitor characteristic is exhibited.
In the following description, the 1 st facing portion 5Aa and the 2 nd facing portion 5Ba will be collectively referred to as the facing portion 5a without being particularly distinguished. When the 1 st lead-out portion 5Ab and the 2 nd lead-out portion 5Bb are not particularly described separately, they will be collectively referred to as the 1 st lead-out portion 5 b.
Q1 shown in fig. 2 is an outer region Q1 within 10% from the outer layer portion 7 side in the stacking direction T of the inner layer portion 6. Q2 shown in fig. 2 is the remaining 80% of the central region Q2 other than the outer region Q1 in the stacking direction T of the inner layer portion 6. Fig. 4 is a partially enlarged view of the outside area Q1 shown in fig. 2. Fig. 5 is a partial enlarged view of the central region Q2 shown in fig. 2.
(thickness of dielectric layer 4)
In the embodiment, the average thickness t41 of the dielectric layer 4 in the outer region Q1 shown in fig. 4 is thicker than the average thickness t42 of the dielectric layer 4 in the central region Q2 shown in fig. 5. For example, the thickness t41 of the dielectric layer 4 of the outer region Q1 is 0.6 μm to 1.2 μm, and the thickness t42 of the dielectric layer 4 of the central region Q2 is 0.5 μm to 1.0 μm. The thickness t41 of the dielectric layer 4 in the outer region Q1 is 1.1 to 1.3 times the thickness t42 of the dielectric layer 4 in the central region Q2.
The coefficient of variation CV1 of the thickness t41 of the dielectric layer 4 in the outer region Q1 is smaller than the coefficient of variation CV2 of the thickness t42 of the dielectric layer 4 in the central region Q2. That is, the thickness t41 of the dielectric layer 4 in the outer region Q1 is more uniform than the thickness t42 of the dielectric layer 4 in the central region Q2.
For example, the coefficient of variation CV1 of the thickness t41 of the dielectric layer 4 in the outer region Q1 is 0.7 to 0.9 times the coefficient of variation CV2 of the thickness t42 in the central region Q2. In addition, the coefficient of variation CV1 of the thickness t41 of the dielectric layer 4 in the outer region Q1 is 7.5% to 8.5%, and the coefficient of variation CV2 of the thickness t42 of the dielectric layer 4 is 9.5% to 12%.
The coefficient of variation CV (coefficient of variation) is a value obtained by dividing the standard deviation by the average value.
A method for measuring the thicknesses of the dielectric layer 4 and the conductor layer 4 of the multilayer ceramic capacitor 1 will be described below. First, a WT cross section passing through the center of the laminate 2 in the longitudinal direction L is exposed by polishing. If necessary, the polished surface is etched to remove the internal electrode layer 5 stretched by polishing. Then, the exposed cross section was observed.
When the thicknesses of the dielectric layers 4 and the internal electrode layers 5 of the multilayer ceramic capacitor 1 are measured, first, a straight line extending in the stacking direction T of the multilayer body 2 and passing through the center of the multilayer body 2 is drawn in an enlarged image obtained by observing a cross section. Next, a plurality of straight lines parallel to the straight line are drawn at equal intervals (pitch S). The pitch S may be determined to be 5 to 10 times the thickness of the dielectric layer 4 or the internal electrode layer 5 to be measured, and for example, when the dielectric layer 4 having a thickness of about 1 μm is measured, the pitch S is set to 5 μm. Further, the same number of straight lines are drawn on both sides of the straight line. That is, the straight lines are drawn out by odd number lines in total. Next, the thicknesses of the dielectric layer and the conductor layer were measured on the respective lines, and the average value and the standard deviation were obtained.
(thickness of internal electrode layer 5)
Further, the average thickness t51 of the internal electrode layers 5 in the outer region Q1 is thicker than the average thickness t52 of the internal electrode layers 5 in the central region Q2. For example, the thickness t51 of the internal electrode layer 5 of the outer region Q1 is 0.65 μm to 0.8 μm, and the thickness t52 of the internal electrode layer 5 of the central region Q2 is 55 μm to 0.7 μm. Further, the thickness t51 of the internal electrode layer 5 of the outer region Q1 is 0.9 to 0.95 times the thickness t52 of the internal electrode layer 5 of the central region Q2.
As shown in fig. 3, the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B are not exposed at the side surface B in the width direction W of the laminate 2, and this portion becomes a side gap portion.
(external electrode 3)
The external electrode 3 includes a1 st external electrode 3A provided on the 1 st end face C1 of the laminate 2 and a2 nd external electrode 3B provided on the 2 nd end face C2 of the laminate 2. In addition, when the 1 st external electrode 3A and the 2 nd external electrode 3B are described without particularly distinguishing them, they will be collectively referred to as the external electrodes 3. The external electrode 3 covers not only the end face C but also a part of the principal face a and the side face B on the side of the end face C. The external electrode 3 includes a base electrode layer 31 and a plating layer 32 as a coating layer.
(underlying electrode layer 31)
The underlying electrode layer 31 is formed by, for example, applying and baking a conductive paste containing a conductive metal and glass.
(plating layer 32)
A plating layer 32 is formed as a coating layer on the outer surface of the base electrode layer 31. The plating layer 32 includes a nickel plating layer 32a and a tin plating layer 32 b. The nickel plating layer 32a is a plating layer of nickel or an alloy containing nickel. The tin plating layer 32b is a plating layer of tin or an alloy containing tin.
(method of manufacturing multilayer ceramic capacitor 1)
Fig. 5 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment.
(ceramic Green sheet printing Process S1)
As shown in the drawing, in step S1, an internal electrode layer pattern to be the 1 st internal electrode layer 5A and the 2 nd internal electrode layer 5B is printed on a band-shaped ceramic green sheet formed by molding a ceramic slurry containing a ceramic powder, a binder, and a solvent into a sheet shape on a mounting film.
(laminating step S2)
In step S2, a plurality of raw material sheets are stacked such that the internal electrode layer patterns are shifted by half a pitch in the longitudinal direction L between the raw material sheets adjacent to each other in the stacking direction T. Further, ceramic green sheets for the outer layer portion to be the outer layer portion 7 are stacked on both sides in the stacking direction T of the raw material sheets stacked in plural.
(Master batch Forming Process S3)
Next, in step S3, a mother block is formed by thermocompression bonding a product in which ceramic green sheets for an outer layer portion to be the outer layer portion 7 are stacked on both sides in the stacking direction T of the raw material sheets stacked in plural.
(Master block dividing step S4)
Next, in step S4, the mother block is divided into a plurality of laminates 2.
(base electrode layer Forming step S5)
In step S5, the underlying electrode layers 31 are formed on both ends of the laminate 2.
(plating layer Forming step S6)
Next, in step S6, a plating layer 32 including a nickel plating layer 32a and a tin plating layer 32b is formed on the outer surface of the base electrode layer 31, and the multilayer ceramic capacitor 1 shown in fig. 1 is manufactured.
When a high voltage is applied to the multilayer ceramic capacitor 1, insulation breakdown, electrostrictive deformation, and the like are likely to occur in the internal electrode layer 5 on the outer layer portion 7 side. Further, insulation breakdown, electrostrictive deformation, and the like are less likely to occur when the internal electrode layer 5 is thick.
In the multilayer ceramic capacitor 1 of the present embodiment, the thickness t41 of the dielectric layer 4 in the outer region Q1 on the outer layer portion 7 side in the inner layer portion 6 is greater than the thickness t42 of the dielectric layer 4 in the central region Q2. Therefore, dielectric breakdown, electrostrictive deformation, and the like are less likely to occur when a high voltage is applied to the multilayer ceramic capacitor 1. Therefore, insulation failure of the multilayer ceramic capacitor 1 is less likely to occur, and reliability is improved.
In the multilayer ceramic capacitor 1 of the present embodiment, the thickness t41 of the dielectric layer 4 in the outer region Q1 is made uniform with respect to the thickness t42 of the dielectric layer 4 in the central region Q2. Therefore, the electric field generated in outer region Q1 becomes more uniform than the electric field generated in central region Q2, and thus dielectric breakdown, electrostrictive deformation, and the like in outer region Q1 are less likely to occur. Therefore, insulation failure of the multilayer ceramic capacitor 1 is less likely to occur, and reliability is improved.
Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments.
Claims (7)
1. A multilayer ceramic capacitor is characterized by comprising:
a laminate body having an inner layer portion including a plurality of dielectric layers and a plurality of internal electrode layers that are alternately laminated, and outer layer portions that are respectively arranged on both sides of the inner layer portion in a lamination direction; and
external electrodes covering end surfaces on both sides of the laminate,
the inner layer portion has:
an outer region within 10% of a thickness of the inner layer portion in the stacking direction from the outer layer portion side; and
a central region being the remaining 80% outside the outer region,
the average thickness of the dielectric layer in the outer region is thicker than the average thickness of the dielectric layer in the central region.
2. The laminated ceramic capacitor according to claim 1,
the coefficient of variation of the thickness of the dielectric layer in the outer region is smaller than the coefficient of variation of the thickness of the dielectric layer in the central region.
3. The laminated ceramic capacitor according to claim 1 or claim 2,
the coefficient of variation of the thickness of the dielectric layer in the outer region is 7.5% to 8.5%,
the coefficient of variation of the thickness of the dielectric layer in the central region is 9.5% to 12%.
4. The laminated ceramic capacitor according to claim 1 or claim 2,
the average thickness of the internal electrode layers in the outer region is thicker than the average thickness of the internal electrode layers in the central region.
5. The laminated ceramic capacitor according to claim 1 or claim 2,
the length in the stacking direction is 0.2mm to 0.23mm,
the length in the length direction is 0.38mm to 0.44mm,
the length in the width direction is 0.20mm to 0.23 mm.
6. The laminated ceramic capacitor according to claim 1 or claim 2,
the thickness of the dielectric layer in the stacking direction is 0.5 to 1.2 [ mu ] m.
7. The laminated ceramic capacitor according to claim 1 or claim 2,
the thickness of the internal electrode layers in the stacking direction is 0.55 to 0.8 [ mu ] m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121462321.5U CN215868985U (en) | 2021-06-29 | 2021-06-29 | Multilayer ceramic capacitor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121462321.5U CN215868985U (en) | 2021-06-29 | 2021-06-29 | Multilayer ceramic capacitor |
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| Publication Number | Publication Date |
|---|---|
| CN215868985U true CN215868985U (en) | 2022-02-18 |
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| CN202121462321.5U Active CN215868985U (en) | 2021-06-29 | 2021-06-29 | Multilayer ceramic capacitor |
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| CN (1) | CN215868985U (en) |
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- 2021-06-29 CN CN202121462321.5U patent/CN215868985U/en active Active
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